teaching microprocessor and microcontroller

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HDL. A. Arithmetic Logic Unit (ALU). The ALU is a digital circuit that performs integer arithmetic and logical operations inside the processor. It is a fundamental.
Teaching Microprocessor and Microcontroller Fundamental Using FPGA Karyono Computer Engineering, Universitas Multimedia Nusantara Scientia Garden, Jl. Boulevard Gading Serpong, Tangerang, Indonesia [email protected]

Abstract—Teaching microprocessor and microcontroller fundamental can be done in various ways. From flash animation, computer simulator, model computer, hardware model until using FPGA. This work imply FPGA as the way to help students understand the way microprocessor and microcontroller work, examine the bus condition, timing and follow step by step instructions fetching, decoding up to the execution of instruction. The microprocessor and microcontroller implemented in teaching are ranged from the simple one up to the complex one. The complexity will be limited to the type of FPGA that is used in the process. This approach will be beneficial to the students to get the inside understanding about the microprocessor and microcontroller. The students can have real hardware experiences rather than only having software or simulation experiences. Furthermore, the students can deploy various kind of microprocessor and focus on some highlighted features without having to change the hardware. Keywords— teaching; microprocessor microcontroller fundamental; FPGA; simulation

I.

fundamental;

INTRODUCTION

Conventional ways to teach microprocessor and microcontroller are commonly based on simulators. In practical such approach will not always effective due to the complexity of the microprocessor components. Many approaches have been conducted to improve the teaching methods. These approach starts from flash animation, computer simulator framework, hardware model computer, up to the use of FPGA for teaching purposes. This work imply FPGA as the way to help students understand how microprocessor and microcontroller work, examine the bus condition, timing and follows step by step instruction fetching, decoding up to the execution of instruction. Previous work have been done to implement complex computer model in FPGA for teaching advance subject such as microprocessor design subject [1] and multicore / parallel processing subject [2]. This paper will describe the implementation of creating an FPGA based microprocessor and microcontroller for fundamental subject. The implementation starts from the simplest one, up to the more complex architecture. The use of FPGA in this way of teaching gives students deeper experience and feel in implementing microprocessor and microcontrollers.

Arya Wicaksana Computer Science, Universitas Multimedia Nusantara Scientia Garden, Jl. Boulevard Gading Serpong, Tangerang, Indonesia [email protected]

II.

FUNDAMENTAL OF MICROPROCESSOR COMPONENTS

Basic processor is composed of an arithmetic logic unit, control unit, and memory. These components are important to a processor. This section will show how the fundamental of a processor components can be designed and implemented in FPGA [6]. In the following subsection, the steps needed to develop a fundamental processor will be described. Trivial stages, for instance the creation of the project, will not be exposed in this paper. The parameters shown in this section depends on the FPGA chip, in this case the Altera DE1 board and using Verilog HDL.

A. Arithmetic Logic Unit (ALU) The ALU is a digital circuit that performs integer arithmetic and logical operations inside the processor. It is a fundamental building block of the processor. The operations consist of simple addition, subtraction, multiplication, division, and logic operations—such as OR and AND. A basic ALU requires two data inputs and an opcode. The opcode together with the ALU's carry-in will determine the ALU's function. There will be 16 possible functions of two inputs. The ALU does not have to implement the full set of logical functions. A basic processor's ALU at least must implement addition, subtraction, and one or two bit-wise functions [6]. An adder can be created using Verilog HDL. The bit processing capacity is flexible to the user requirement. The opcode for arithmetic operation within the ALU can be implemented using a global macro definition („define‟) in Verilog HDL and the output value is stored in a register. The ALU module takes two data inputs and one opcode input, and executes the appropriate command based on the opcode. This can be achieved using case statement or if-else statement.

B. Control Unit The control unit is a finite state machine that takes as its inputs the IR, the status register (which is partly filled by the status output from the ALU), and the current major state of the cycle. Its rules are encoded either in random logic, a Programmable Logic Array (PLA), or Read-Only Memory

(ROM), and its outputs are sent across the processor to each point requiring coordination or direction for the control unit [7]. Control Unit Co-ordinates the input and output devices of a computer system. It fetches the code of the every instruction in the micro programs [4]. Following the definition exposed previously, a control unit will be created. This control unit will fetch instructions from the memory and decode it into commands. The fetch operation can be achieved by implementing IR (Instruction Register) and PC (Program Counter) using register data type in Verilog HDL. The instruction is fetched from the memory and then moved into IR. After that the PC will point to the next instruction to be executed.

Fundamental processor in this paper have ability to access the memory component, and also can drive the ALU to perform basic arithmetic and logic operations, such as addition, subtraction, and bit wise function. The final result is stored in the memory to be traced for verification purposes. The top level component module acts as the central processing unit. The top module instantiates all the required components needed in this model. At first, it instantiates control unit which its task is to fetch instructions and data from the memory. After the information required have been fetched, control unit translates the instruction into command and passes it to the ALU. The command then will be executed immediately by the ALU. Finally the result is written in memory by the ALU.

IV.

C. Memory Memory refers to the physical devices used to store programs (sequences of instructions) or data (e.g. program state information) on a temporary or permanent basis for use in a computer or other digital electronic device. For most FPGAs, Random-access memory (RAM) are oftenly used since they efficiently implement large blocks of memory. FPGA use static RAM (SRAM) rather than dynamic RAM (DRAM), because DRAM commonly used for bulk memory requires specialized capacitor structures which cannot be built on the same chip along with high-performance logic transistors. There is also Read-only memory (ROM), as the name implies, can be read but not written [6]. RAM can be implemented as a module in Verilog HDL. It takes address and value as the input and in addition clock and write enable signals. The RAM can be written only when the write enable signal is active. The input value then will be stored in certain address. The difference with ROM is that ROM does not require value as its input; the values are hardcoded within the module. The capacity of the memory, either RAM or ROM can be configured in a flexible manner. It also can be designed either horizontal or vertical, which will give different look and feel for the same memory size.

III.

FUNDAMENTAL OF MICROPROCESSOR

Having created all the basic components of a processor in the previous section, now those components need to be integrated to shape a processor. The processor will have essential components such as ALU, control unit, and memory. Hence it can produce an output according to the input and desired operation. The output later can also be stored in a memory. The illustration of fundamental processor components and cycle can be seen in figure 1.

Fig. 1. Fundamental Processor Components and Cycle.

FPGA DESIGN

FPGA design can be started from scratch by following steps below [9]. 

Make sure there is plenty of time to spare



Find a decent computer



Add a big display if possible



Decide which operating system to use



Consider using a virtual machine (VM)



Select an FPGA vendor



Pick out a suitable development board



Select an embedded processor to use



Download the FPGA design software



Add the latest service packs



Choosing a logic simulator



Choosing a synthesis tool



Learn HDL

The FPGA design process can be achieved in three ways, which are using schematic / block diagram, state machine, and HDL. Each way has its own advantages and disadvantages [8]. The following subsections will expose about each design method.

A. FPGA Design Using Block Diagram The Block Diagram Editor is a tool for graphical entry of VHDL, Verilog and EDIF designs. If the HDL design is in large part structural, it is less hard to enter its description graphically as a block diagram, rather than writing the source code. The Block Diagram Editor will then convert the diagram automatically into structural VHDL, Verilog or EDIF netlist. With Active-HDL, both types of description can be mixed. E.g. the top-level design entity can be a block diagram while the components instantiated in it are described using HDL code/EDIF netlist and/or state diagrams [8]. The sample of this approach is displayed on figure 2.

text editor, HDL editor is preferred due to the syntax checking and reference lookup capabilities, shown in figure 4.

Fig. 2. Designing an FPGA Using Block Diagram [8].

B. FPGA Design Using State Diagram The State Diagram Editor is a tool designed for the graphical editing of state diagrams of synchronous and asynchronous machines. Drawing a state diagram is an alternative approach to the modeling of a sequential device. Instead of writing the HDL code, the description of a logic block can be entered as a graphical state diagram. The editor will then automatically generate the HDL code based on the entered graphical description. Due to the intuitive graphic form, state diagrams are easy-to-learn and far more readable than the HDL code [8]. The sample of this approach can be seen in figure 3.

Fig. 3.

Designing an FPGA Using State Diagram [8].

C. FPGA Design Using HDL The HDL Editor is a text editor designed for editing an HDL source code. It is tightly integrated with the compiler and simulator to enable debugging capabilities. Some of the major features of HDL text editor are Keyword highlighting (VHDL, Verilog/SystemVerilog, C/C++, SystemC, OVA, and PSL), Support for code groups and code structure, Auto-complete and Auto-format, Bookmarks and named bookmarks for easy navigation through source code, Breakpoints and Columns Selection [6]. Although HDL can be created using common

Fig. 4. Designing an FPGA Using HDL [8].

V.

FPGA MICROPROCESSOR IMPLEMENTATION

The simplest way of implementing basic microprocessor is using block diagram. This approach is very well known by the learner since this approach is very common to be used in digital system. More advanced learner will prefer to use the HDL since it will be simpler to use the module for reuse. This module can also be stored for module library [10]. This approach will form structured approach and will be very good for learning purposes. However the use of state diagram for creating the control unit will simplifies the control unit function in simple microprocessor model. The FPGA needed for this basic microprocessor can be of any type (this work use Altera and Xilinx FPGAs). This basic microprocessor will use small amount of components or spaces in FPGA. The components that are mandatory for this implementations are configurable logic blocks, Input Output Blocks, Programmable Interconnect, buffers, clock generator (internal oscillator), and latch [11]. From the basic microprocessor implementation, the students can learn the process implemented in ALU, memory and bus system both data bus and address bus. The most important part is the control unit [12]. From the control unit design, the students can learn about how to control the bus, the instruction fetch, decode and execute and timings. The control bus can be implemented using logic gates, decoder or using lookup table. The students can also gain insight knowledge about the instruction cycles in accordance with timing cycles. Upon the completion of this basic model, the students can have very fast basic microprocessor since the FPGA tends to have very fast processing speed. Some modification can be done to increase the capability of this basic microprocessor. The additional capabilities can be the additional of bits for the microprocessor, for example from only four bits to eight bits processor, memory with wider data capabilities or more addresses, wider data or address bus and many modifications that also can increase the knowledge of the students.

In this work complex microcontroller is also implemented to give an example how real microprocessor can be implemented using FPGA. The microcontroller is an Intel MCS 51 family microcontroller. The architecture view on this microcontroller can be seen in figure 5.

B. Area Optimization Area is one of three main physical characteristics in digital design. Area can be shrinked by chosing the right topology. Topology is a design organization in the higher level and not device specific. Topology which optimizes the area is one the reuse logic resources as many as possible, most of the times this will sacrifice the throughput of the design [5]. Area optimization can be achieved by implementing “rolling up the pipeline” method. By implementing this method, there will be a trade-off between area and throughput. The key of this method is to cut pipeline as many as possible, because having more pipeline implicitly imply that it requires more resource to keep the temporary result. This will make the area bigger because it contains more elements in it [5].

C. Power Optimization Power is important physical characteristic in digital design. Compare to ASICs (Application Specific Integrated Circuits), FPGA waste more power and not applicable for ultralowpower design. Some FPGA vendors provide lowpower CPLDs (Complex Programmable Logic Devices), however it still limited in size and capability, hence not suitable for applications that require certain computing power [5]. In CMOS technology, dynamic power consumption related to charging and discharging parasitic capacitances in gates and metal traces. General equation to calculate power dissipation from capacitor: Fig. 5. MCS 51 Microcontroller Architecture [13].

VI. FPGA DESIGN OPTIMIZATION FPGA design can be optimized in term of speed, area, and power. There are several ways to optimize the design based on each section. The following subsection will expose about method that is useful for opimizing the design [5].

A. Speed Otimization There are three main definitions for speed: throughput, latency, and timing. In the context of data processing in FPGA, throughput means the total of data that processed per clock cycle. Metric for measuring throughput is bits per second. Latency means time between input and output. Its metric is clock cycles. Timing is logic delays between sequential elements. Where delay on the critical path is bigger than the clock period target. The metric for timing is clock period and frequency. The optimizations within this area are [5]: 

High-throughput architectures for optimizing the number of bits per second which can be processed by the design



Low-latency architectures for minimizing the delay of the process



Timing optimizations for minimizing the combinatorial delay in critical path.

I=V*C*f

(1)

where I is total dissipation, V is voltage, C is capacitance, dan f is frequency [5]. In FPGA design, voltage is constant, only C and f can be manipulated to result in low power dissipation. The value of capacitance depends on number of gates and also the length of the route which connect each gates. The value of f depends on clock frequency. All power-reduction technique at last will lead to reduction of one of these two variables [5].

D. Optimization Result For basic processor implementation this FPGA design optimization will not affect much. In MCS 51 implementation, using Xilinx XC4010XL, the whole FPGA‟s configurable logic blocks will be occupied even with only 3 MCS 51 microcontroller instructions implemented in FPGA. After the optimization, 28 MCS 51 microcontroller instructions only occupied 97% of the FPGA‟s configurable logic blocks (CLB). Using this model, the area that are occupied by the microcontroller‟s components can also visible. This result can also be used to get an additional knowledge regarding on the performance of the model built on FPGA. The area usage of the MCS 51 microcontroller components implemented on Xilinx XC4010XL FPGA can be seen in Table I.

TABLE I. AREA USAGE OF THE MCS 51 ON XC4010XL FPGA

Register and Parity

40

Internal RAM

42

can deploy various kind of microprocessor and focus on some highlighted features without having to change the hardware. The complexity of the microprocessor will be limited to the type of FPGA that is used in this process. The use of FPGA in this way of teaching gives students deeper experience in implementing microprocessor and microcontrollers.

Internal ROM

132

REFERENCES

Control Unit

65

Components

Number of CLB

ALU

243

The sample of the timing result on one of the instruction is displayed in figure 6.

[1]

[2]

[3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13]

Fig. 6. MCS 51 Timing Simulation for DIV instruction [12].

VII. CONCLUSION One of the tools to study basic microprocessor and microcontroller is through the use of FPGA. The microprocessor and microcontroller implemented in teaching are ranged from the simple one up to the complex one. The students can learn how microprocessor work, examine the bus condition, timing and follows step by step instruction fetching, decoding up to the execution of instruction. The students can have real hardware experiences rather than only having software or simulation experiences. Furthermore, the students

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