Table V is an illustration of the merging process of control words for the merged test pairs of the CUT c 17. ... CS6=11000. C10=XXXX0 C12,21=00101. CS3= ...
Theoretical and Applied Informatics ISSN 1896-5334 Vol. 19 (2007), no. 1 pp. 19 - 36
Test Pattern Generator for Delay Faults TOMASZ RUDNICKI, ANDRZEJ HŁAWICZKA a a
Institute of Electronics Silesian University of Technology, Poland Received 22 March 2007, Revised 20 May 2007, Accepted 1 June 2007
Abstract: One of the recently proposed solutions to the problem generation of test pairs’ patterns to target delay faults is a Multiple Input Signature Register (MISR). The paper proposes a method to minimize control words and to modify the operation diagram of the Test Pattern Generator (TPG) aiming at achieving acceptable test times while ensuring a very high coverage of Path Delay Faults (PDF). Experimental results are presented, in which the method of test pairs for benchmarks of the International Symposium on Circuits and Systems in 1989 (ISCAS’89) has been employed [6]. Benchmarks presented in ISCAS’89 are sequential circuits. These results confirm a high effectiveness of this method compared to other solutions. Keywords: Delay Faults, Test Pairs, MISR, ROM, TPG
1. Introduction With a growing number of transistors on-chip, the problem of manufacturing defects becomes more serious as they translate in physical defects such as leakage conductance between pins, surface contamination and high humidity that might, in turn, produce path delay faults. These types of defects may also appear during normal operation of circuits due ageing forced by the working conditions such as: supply voltage, temperature, humidity or pressure. Path delay fault model is presented in Fig. 1. The path delay fault model features the advantageous capability of modeling distributed failures, which are typically caused by statistical variations in the manufacturing process. In addition, it is extremely useful for circuit designs based upon statistical timing, since those circuits are known to have a nonzero probability for the occurrence of delay faults, even when all gate delays are within their specified worst case ranges. In order to detect path delay faults we use a test tool in the form of a compound pair of two vectors P={V1,V2}. The first vector V1 serves to initialize the Circuit Under Test (CUT) whilst the second one, V2, is required to launch the appropriate transition (01 or 10) and propagate the fault effect to the CUT output. Such testing method
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is commonly referred to as Two-Pattern-Testing (TPT) [1]. A TPG that consists of a MISR, a ROM and a counter is presented in Fig. 2. The MISR is a direct source for test pairs of the CUT.
Fig. 1. Path delay fault model
Fig. 2. A Test Pattern Generator with a ROM
The ROM was used for storage of Ls n-bits of the MISR’s control words. The counter serves to address the ROM. The f is a frequency of TPG. The g is a number of clock cycles the MISR is generating sequence for each control word. The advantage of this structure is its scalability and independence of the CUT functions. This means in practice that any change in the CUT function does not imply changes in the TPG’s structure. The only change is that associated with the control words stored in the ROM. However, the order of appearance of control words has no importance. The operation diagram of the TPG is presented in Fig. 3.
Fig. 3. The operation diagram of the TPG
The potential of this structure for generating test pairs was discussed in [2,3]. Here, it was assumed, that the linear feedback of an n-bit MISR consisted of a primitive polynomial, ensuring a 2n-1 operation cycle of this register. Because the counter works g times slower than the MISR, this latter operates at each control in a reduced working cycle, containing only g
