An Automatic Test Pattern Generator for Large Sequential Circuits based on Genetic Algorithms P. Prinetto, M. Rebaudengo, M. Sonza Reorda Politecnico di Torino Dipartimento di Automatica e Informatica Torino, Italy Abstract* This paper is concerned with the question of automated test pattern generation for large synchronous sequential circuits and describes an approach based on Genetic Algorithms suitable for even the largest benchmark circuits, together with a prototype system named GATTO. Its effectiveness (in terms of result quality and CPU time requirements) for circuits previously unmanageable is illustrated. The flexibility of the new approach enables users to easily trade off fault coverage and CPU time to suit their needs.
1. Introduction Automated Test Pattern Generation (ATPG) for digital circuits is a major research topic. As far as the single stuck-at fault model is considered, efficient algorithms have been devised for combinational networks. Very large sequential circuits, however, still constitute a problem. None of the methods proposed can fully handle all the real-world circuits test engineers have to deal with, since they either definitely get off or generate sequences with very low fault coverages. Three types of approaches have been suggested: • topological: extension to sequential ones of the algorithms for combinational circuits, by adopting the Huffman Model [NiPa91], [KSLe93]; • simulation-based: employment of the results provided by a fault simulator [ACAg88], [HIHH92]; methods based on Genetic
* This work has been partially supported by ESPRIT BRA 6575 ATSEC, and by the MURST 40% project Affidabilità e Diagnostica in Elettronica. Contact address: Paolo Prinetto, Politecnico di Torino, Dipartimento di Automatica e Informatica, Corso Duca degli Abruzzi 24, I-10129 Torino (Italy), e-mail
[email protected]
Algorithms [SSAb92], [RHSP94] also belong to this group; • symbolic: use of the knowledge of both the output and the next-state functions of the circuit [CHSo93]. Very large sequential circuits have been the subject of two approaches: • circuit modifications, e.g., through manual or automatic insertion of Design for Testability structures, such as full or partial scan; • resort to parallel and/or distributed systems to enhance capabilities in terms of CPU time required and maximum circuit size. [RaBa92] describes a portable code that implements a parallel/distributed version of a topological ATPG for sequential circuits. A distributed version of a commercial ATPG tool is reported in [AAVi93]. A new approach based on Genetic Algorithms [Holl75] is presented in this paper. Its main advantage is the provision of good results with reduced CPU times, even for the largest benchmark circuits, and it allows the user to easily trade off fault coverage and CPU time. A similar approach has been previously followed in [SSAb92] and [RHSP94]. In the former paper, test vectors are generated on the basis of an Objective Function which measures the extent to which the activity is balanced within the circuit. The method considers both combinational and sequential circuits, and logic simulation is used to compute the objective function. By comparison with [SSAb92], the approach presented here is solely concerned with very large sequential circuits and adopts techniques especially suited for them, resulting in a comparable efficiency but shorter test sequences. The method described in [RHSP94] is based on a Fitness Function which exploits the results produced by a Fault Simulator; one vector at a time is generated, following a three phases
approach, as in CONTEST [ACAg88]. Our approach uses a Fitness Function defined in a similar way, but the meaning of the three phases is completely different; moreover, it optimizes the whole test sequence, and is significantly faster. A description will now be given of our prototype algorithm named GATTO (Genetic Algorithm for Test paTtern generatiOn). In particular, Section 2 briefly outlines Genetic Algorithms; Sections 3 describes the algorithm and Section 4 draws some conclusions.
2. Genetic Algorithms Genetic Algorithms [Holl75] (GAs) have long been investigated as a possible solution for many search and optimization problems. GAs are evolutionary algorithms that mimic the way nature improves the characteristics of living beings. Each solution (individual) is represented as a string (chromosome) of elements (genes) and is assigned a fitness value based on the value given by an evaluation function. The fitness value measures how close the individual is to the optimum solution. A set of individuals constitutes a population that evolves from one generation to the next through the creation of new individuals and the deletion of some old ones. The process starts with an initial population created in some way, e.g., randomly. Evolution can take two forms: • cross-over: the chromosomes of two individuals are combined to obtain a new individual for insertion in the population to replace another individual, e.g., the one with the lowest fitness (elitism). The cross-over is generally backed by techniques ensuring that the selection probability of each individual is proportional to its fitness. New individuals are thus likely to have a higher fitness than those they replace. The process is oriented towards those sub-regions of the search space where optimal solutions are supposed to exist. • mutation: a gene of a selected individual is randomly changed. This provides additional chances of entering unexplored sub-regions. Evolution is stopped when either the goal is reached or a maximum CPU time has been spent.
3. The ATPG Algorithm The three phases of the test generation process are illustrated in the algorithm’s pseudo-code (Fig. 1): • phase 1: selection of a fault (target_fault) from the undetected faults;
• phase 2: generation of a test sequence (new_sequence), if any, for the target fault; • phase 3: fault simulation of the test sequence and search for additionally detected faults (fault dropping). The three phases are repeated until either all the faults have been processed, or a pre-defined maximum number of iterations MAX_CYCLES has been reached. Fault simulation for stuck-at faults on synchronous sequential circuits is amply catered for by many efficient algorithms and tools [NTPa92], [LeHa92]: we can therefore concentrate on phases 1 and 2.
3.1. The Genetic Algorithm for ATPG Generation of a fault-detecting sequence is a search in the space of all the possible sequences applicable to the Primary Inputs (PIs) of the circuit. A GA can be used for this purpose, provided that both a suitable encoding for the generic solution, and an effective evaluation function are found. For encoding, an individual corresponds to a sequence composed of a variable number of input vectors to be applied starting from the reset state. A population is a set of individuals. Finding an effective evaluation function is a much more complex task. It is easy to understand whether a given sequence is a solution (i.e., whether it detects the fault). Its closeness to the goal, however, is much more difficult to determine. Our approach uses two heuristic parameters: • the weighted number of gates with different values in the good and in the faulty circuits. A weight associated with each gate measures its observability, i.e., the easiness of propagating its value to a Primary Output (PO) or to a Flip-Flop; • the weighted number of Flip-Flops (whose inputs will hereinafter be referred to as Pseudo Primary Outputs or PPOs) with different values in the good and in the faulty circuits. A weight associated with each Flip-Flop measures its observability, i.e., the easiness of propagating its value to a PO. The following function has been defined to rank sequences according to their distance from being testing sequences; for the k-th input vector vjk of a sequence sj, and for each fault fi, the function h estimates how close the fault is to being detected by the vector:
ngate
nFF
p=1
m =1
h(vjk,fi ) = c1 ∑ wp'd p'(vjk,fi ) + c2 ∑ wp''d p''(vjk,fi ) (1) where: • ngate and nFF are the number of gates and FlipFlops, respectively • w'p is the weight of the p-th gate, defined as w'p= M'-min_path_len(p) being min_path_len(p) the minimum number of gates on any path between the p-th gate and a PO or PPO, and M'=maxp(min_path_len(p)) p ∈ [1..ngate] • the function d’p(vjk,fi) returns 1 (0) iff, as a consequence of the application of vjk, the value of the p-th gate is different (equal) in the good and in the faulty circuit for fault fi • w’’m is the weight of the m-th Flip-Flop, defined as w’’m= M’’-depthm being depthm the minimum number of FlipFlops on any acyclic path between the m-th FlipFlop and a PO, and M’’=maxm(depthm) m∈[1..nFF] • the function d’’m(vjk,fi) returns 1 (0) iff, as a consequence of the application of vjk, the value of the m-th Flip-Flop is different (equal) in the good and in the faulty circuit for fault fi. The values for c1 and c2 in (1) are chosen so that the value of h for any fault whose effects have not reached any PPO is less than for any fault whose effects have reached at least one PPO. An evaluation function H(sj,fi) is associated with each sequence sj; H corresponds to the maximum value of the function h defined in (1): H(sj,fi)=maxk(h(vjk,fi)) vjk ∈sj Once the individual encoding and the evaluation function have been defined, the whole process can be organized in two steps: several random sequences are generated until the evaluation function of a particular fault becomes greater than zero. This fault is then chosen as the target one, and a test sequence for it is generated. These two steps constitute phase 1 and phase 2, and require more detailed investigation. 3.1.1. Phase 1: choosing the target fault Sequences are randomly generated in groups of NUM_SEQ, and are all composed of L vectors. Each sequence is fault-simulated with respect to all the not
yet detected faults. If no fault produces an H greater than zero, a new set of NUM_SEQ random sequences is generated, whose length L is increased. Otherwise, the fault with the maximum value of the evaluation function is selected as target fault. The whole process is stopped when a maximum number MAX_ITER of iterations is reached. Faults detected during this phase are dropped from the fault list, and the corresponding sequences are inserted in the final set of test sequences. It must be noted that phase 1 is purely random and does not exploit GAs, because neither the cross-over, nor the mutation operators are applied. L is not known and must be assigned an initial value for the first activation of phase 1 (Lin) based on the topological characteristics of the circuit. This is then dynamically updated by using for each phase 1 the length of the test sequence generated by the last phase 2. The pseudo-code of phase 1 is reported in Fig. 2. 3.1.2. Phase 2: Generating a Test Sequence for the Target Fault Phase 2 is based on a GA. Each sequence is an individual and NUM_SEQ sequences constitute a population. The initial population is composed of the last NUM_SEQ sequences generated in phase 1. The target fault ft only is considered in this phase. The fitness function F(sj) is obtained from the evaluation function H(sj,ft)via linearization: the individuals are sorted in decreasing order with respect to H, and the fitness value NUM_SEQ is assigned to the first individual, the value NUM_SEQ-1 to the second, and so on. A new population is generated from the previous one through evolution: NEW_IND newly created individuals replace the worst individuals in the previous generation. The survival of the best NUM_SEQ-NEW_IND individuals from one generation to the next (elitism) is thus ensured. Evolution proceeds through two operators: • the cross-over operator (Fig. 3) selects two parent individuals from the current population, randomly generates two numbers x1 and x2, and builds a new individual composed of the first x1 vectors of the first parent and the last x2 vectors of the second; • the mutation operator randomly selects a newly generated test sequence and complements a single bit within it. This operator is activated with probability pm.
Candidates for the cross-over operator are selected on a probabilistic basis: the likelihood that an individual will be selected is proportional to its fitness, so that the best sequences are more likely to provide vectors for the new individuals. Once a new population has been generated, the fitness function is repeatedly evaluated for the target fault and for each sequence until one of the following conditions is met: • the target fault is detected: the corresponding sequence is then inserted in the final set of test sequences; • a given maximum number of generations MAX_GEN is generated without detecting the fault: this is then marked as aborted and discarded as a possible target fault. If phase 1 ends without identifying a target fault, it should be repeated with all the faults. This gives the aborted faults a final chance of becoming target faults, and prevents some experiments from stopping too early. The pseudo-code of phase 2 is reported in Fig. 4.
3.2. Experimental Results The mono-processor version of GATTO has been implemented in the ANSI-C language and corresponds to about 3,000 lines of code. The largest circuits in the standard set of synchronous sequential benchmarks proposed at the ISCAS’89 conference [BBKo89] have been considered. The values of the algorithm’s main parameters are shown in Tab. 1. Changes in these values result in a trade-off between accuracy and computational complexity, as will be shown below: the values in Tab. 1 are biased towards reducing the CPU time required. The computational cost of GATTO is mainly determined by the fault simulation task and an efficient fault simulation algorithm is therefore essential. The single-fault propagation, parallel-fault technique [NTPa92] (the state-of-the-art approach) was adopted. The power of the parallel-fault approach was able to be fully exploited in phase 2, where only the target fault has to be simulated, by forcing the algorithm to concurrently select a packet of 64 faults (to match the 64 bit hardware parallelism of the latest generation of processors) for use as target faults. The goal of phase 2 was thus the generation of a set of test sequences able to detect all of them. Tab. 2 shows the results obtained when GATTO was run on a DEC Alpha AXP 3000/500 workstation with a 32 Mbyte memory. Only the largest ISCAS’89 circuits
were considered. Very few methods ([NiPa91], [SSAb92], [HHIH92], [KSLe93], [RHSP94]) are able to produce any test sequence for such circuits, whereas GATTO handled them all. The results (measured by the percent Fault Coverage on the complete standard Fault List and by the number of sequences and vectors generated) are comparable with those of the other methods. CPU times are generally quite low, and do not explode. They are compared with those in the literature in Tab. 3. The hardware platform used is reported in the third row. The method described in [CHSo93] is fast, but its applicability is limited to the circuits with less than some tens of Flip-Flops. [NiPa91], [SSAb92] and [RHSP94] can deal with some of the largest circuits, although the last requires long CPU times compared with GATTO. It will be noted that GATTO was able to handle the largest circuit of all in less than 3 hours. GATTO’s memory occupation requirement is small, as it is substantially confined to storage of the sequences and to the space needed for the fault simulation. Effectiveness of the evolutionary approach is often evaluated by comparing its performance with that of a purely random one. In GATTO phase 1 is random, since the faults it detects are those that would be detected by a purely random method. The GA further increases the final coverage through the faults detected in phases 2 and 3. Tab. 4 shows the number of faults detected in each phase, together with a parameter denoted GA Efficiency, namely the ratio between the number of faults detected in either phase 2 or 3, and those detected in phase 1. The effects of phase 1 are dominant for circuits with a high percentage of easy-totest faults. However, for some other circuits (especially the largest ones) the GA’s contribution is essential to improve the final coverage. The user can trade off accuracy against the CPU time by choosing the value of MAX_GEN, MAX_CYCLES and NUM_SEQ. For example, more MAX_CYCLES will select more target faults and improve the coverage at the expense of a greater computational cost, as illustrated for circuit S38584 in Tab. 5. GA Efficiency increases with the length of the experiment, proving that the effectiveness of the evolutionary approach surpasses that of the random approach in medium and long-length experiments. Fault Coverage is plotted against CPU time for the same circuit for different values of MAX_CYCLES in Fig. 5.
Fault sampling and fault collapsing would further improve the algorithm by significantly reducing the CPU time, as they cut down the size of the fault list without impairing the fault coverage.
4. Conclusions Existing ATPG tools for synchronous sequential circuits cannot adequately handle very large circuits, due to their unacceptable memory size and CPU time requirements. This paper presents GATTO, a system based on Genetic Algorithms, which is particularly suited for such large circuits. Experiments have shown that GATTO produces good fault coverage and test lengths for all the largest ISCAS’89 circuits. Its memory occupation and CPU time requirements are very limited, and do not explode when the circuit size increases. Its results quality and CPU time requirements compare very well with those of other methods. The user can trade off accuracy and CPU time by simply changing the value of some parameters. The approach is flexible, as it can easily handle mixed-level circuit descriptions and fault models different from the single stuck-at, provided a suitable fault simulator is available and an appropriate fitness function is used. In conclusion, this paper demonstrates that GAs are an effective approach to large problems, for which other methods cannot be adopted.
5. References [AAVi93] P. Agrawal, V.D. Agrawal, J. Villoldo, “Sequential Circuit Test Generation on a Distributed System,” Proc. 30th Design Automation Conference, 1993, pp. 107-111 [ACAg88] V.D. Agrawal, K.-T. Cheng, P. Agrawal, “CONTEST: A Concurrent Test Generator for Sequential Circuits,” Proc. 25th Design Automation Conference, 1988, pp. 84-89 [BBKo89] F. Brglez, D. Bryant, K. Kozminski, “Combinational profiles of sequential benchmark circuits,” Proc. Int. Symp. on Circuits And Systems, 1989, pp. 1929-1934 [CHSo93] H. Cho, G.D. Hatchel, F. Somenzi, “Redundancy Identification/Removal and Test Generation for Sequential Circuits Using Implicit State Enumeration,” IEEE Transactions on ComputerAided Design, Vol. CAD-12, No. 7, pp. 935-945, July 1993 [GBDJ93] A. Geist, A. Beguelin, J. Dongarra, W. Jiang, R. Manchek, V. Sunderam, “PVM 3 User’s Guide and Reference Manual,” Oak Ridge Nat. Lab., Internal Report ORNL/TM-12187, May 1993
[HHIH92] K. Hatayama, K. Hikone, M. Ikeda, T. Hayashi, “Sequential Test Generation based on RealValued Logic Simulation,” Proc. Int. Test Conf., 1992, pp. 41-48 [Holl75] J.H. Holland, “Adaption in Natural and Artificial Systems,” University of Michigan Press, Ann Arbor (USA), 1975 [KSLe93] T.P. Kelsey, K.K. Saluja, S.Y. Lee, “An Efficient Algorithm for Sequential Circuit Test Generation,” IEEE Transactions on ComputerAided Design, Vol. 42, No. 11, pp. 1361-1371, November 1993 [LeHa92] H.K. Lee, D.S. Ha, “HOPE: An Efficient Parallel Fault Simulator for Synchronous Sequential Circuits,” Proc. 29th Design Automation Conference, 1992, pp. 336-340 [NiPa91] T. Niermann, J.H. Patel, “HITEC: A Test Generator Package for Sequential Circuits,” Proc. European Design Automation Conference, 1991, pp. 214-218 [NTPa92] T.M. Niermann, W.-T. Cheng, J.H. Patel, “PROOFS: A Fast, Memory-Efficient Sequential Circuit Fault Simulator,” IEEE Transactions on Computer-Aided Design, Vol. 11, No. 2, pp. 198-207, February 1992 [RaBa92] B. Ramkumar, P. Banerjee, “Portable Parallel Test Generation for Sequential Circuits,” Proc. Int. Conf. on Computer Aided Design, 1992, pp. 220-223 [RHSP94] E.M. Rudnick, J.G. Holm, D.G. Saab, J.H. Patel, “Application of Simple Genetic Algorithms to Sequential Circuit Test Generation,” Proc. European Design & Test Conf., 1994, pp. 40-45 [SSAb92] D.G. Saab, Y.G. Saab, J. Abraham, “CRIS: A Test Cultivation Program for Sequential VLSI Circuits,” Proc. Int. Conf. on Computer Aided Design, 1992, pp. 216-219
L=Lin; /* initial length of sequences */ for( i=0; i
