testing in deep submicron - IEEE Xplore

A New Scheme for Effective

IDDQ

Testing in Deep Submicron

Y. T~iatouhas”~, Y. Moisiadis2, Th. H a n i ~ t a k i s ~D., ~Nikolos3 , and A. Arapoyanni2 ‘ISD S.A. 22,K. Varnali Str. I52 33, Chalandri, Greece e-mail: y.tsiatouhasaieee. org

’Uniersity ofAthens Dept. of Informatics, TYPA Bld. 157 84, Athens, Greece e-mail: arapogiaodi. uoa.gr

to O.lpm [l]. In addition the number of transistors in a single chip is increased rapidly resulting in a further increase of the background current. A lot of effort has been spent from the scientific community to determine the components of transistor leakage current that contribute to the total defect-free IDDQ current of a circuit [I-111. The leakage current is influenced by the channel length (short channel effects [4]), the threshold voltage, the gate oxide thickness, the drain and source junction depth, the doping profile, the power supply and the temperature. The major leakage mechanisms can be summarized as follows: a) The reverse-bias pn junction leakage current, b) The weak inversion current between source and drain when IV,, I < IVTHl (sub-threshold leakage). c) The gate oxide tunneling, as gate oxide is getting thinner. d) The hot carrier injection, as the effective channel length L,ff is reduced. e) The gate induced drain leakage (GIDL) current for low V, and high Vd. f) The drain induced barrier lowering (DIBL) leakage current as L,E is shorten and g) The punchthrough current (depending on substrate doping profile). In technologies above 1pm the reverse-bias pn junction leakage current dominates. For submicron technologies below 0.5pm the dominant component of transistor leakage current is the weak inversion current [5, 71, The weak inversion current depends exponentially on VTH and temperature and increases as the VTH is reduced andlor the temperature is increased. Various techniques have been proposed 19, 211 aiming to reduce the leakage current and make lDDQ testing feasible in deep submicron technologies. The exponential dependence of leakage current on temperature can be exploited applying IDDQ testing at lower temperatures where the leakage current is reduced [7] or applying IDDQ testing at two different temperatures [4] since the current due to defects will not have an exponential growth with temperature. Another common practice is the partition of the CUT into small subcircuits, obviously with the penalty

Abstract testing has become a widely accepted defect detection technique in CMOS ICs. However its eflectiveness in deep submicron is threatened by the increased transistor sub-threshold leakage current. In this paper, a new lIjilc~ testing scheme is proposed based on the use of a compensation circuit. The compensation circuit is used to eliminate, during testing, normal leakage current f r o m the sensing node of the circuit under test so that already known in the open literature IijiIQ sensing techniques can be applied in deep submicron. lIjDQ

1. Introduction IDDQ testing has been recognized as an effective testing technique for the detection of defects in CMOS circuits. IDDQ testing is based on the fact that defect free CMOS circuits exhibit very low quiescent (or IDDQ) current than the defective one. According to lDDQ testing every factor that causes excessive quiescent current, outside the specified limits of the circuit under test (CUT), is considered defective. Obviously, in order to detect those defective quiescent currents they should be significantly higher (more than an order of magnitude) than the normal defect-free quiescent current (here after called background current, IB) of the CUT. Moreover, this technique requires accurate measurements of extremely small currents at the power supply terminals of the CUT. Typically, the IDDQ threshold current (ITH) for the discrimination of defect free and defective circuits is set in the range of few pA [ 1-21, However, for current and future short channel, low threshold voltage (VTH)technologies the effectiveness of IDDQ testing seems to be restricted. This is due to the fact that technology scaling leads to a remarkable increase of the background leakage current [ 1- 1 11 while in parallel the defective quiescent current is decreased [6]. The leakage current is expected to increase at least by a factor of 100 as the minimum feature size is reduced from 0.5pm

9 0-7695-0637-2/00 $10.000 2000 IEEE

University of Patras Dept. of Comp. Engin. & Informatics 26 500, Patras, Greece e-mail: nikolosdo cti.gr e-mail: haniotakoceid. upatras. gr

of area overhead [22]. A third technique is to apply substrate biasing, during testing, to increase threshold voltage [ 1 , 7, 91. Although this is an effective technique it is not so easy to be implemented in CMOS. The use of dual threshold voltage design techniques for the transistors at the slow paths of the CUT has also been proposed [9, 121 for the reduction of defect-free IDDQ current. Finally, an altemative way to reduce the leakage is to apply a lowered power supply in quiescent state but there is a need to determine its effect on signal to noise ratio of detectable defects [7]. In addition to the previous techniques and considering the dependence of leakage current on the applied input vector to the CUT, methods to select a proper set of IDDQ test vectors have been proposed so that low defect-free IDDQ current to be achieved during testing [ 13- 141. In this paper the problem of IDDQ testing in deep submicron designs is approached from a different point of view. This is based on the assumption that if we are able during testing to eliminate the background current (defectfree IDDQ) of the CUT from the IDDQ sensing node then all the current monitoring methods proposed until now can be applied effectively in the new millennium deep submicron world. The paper is organized as follows: the new scheme is presented in section 2 while in section 3 simulation results are discussed.

sensitive in the range of defect free I D ~ Qcurrents of the CUT and thus its threshold current should be selected carefully. IDDQ current is the sum of two components, the defect free IDDQ current (background current - IB) and any possible defective current (IDF) of the CUT. The problem with IDDQ testing in submicron technologies is that the background current, IB, of a CUT increases and may approach the value of the defective current, IDF. IDDQ testing is further limited considering that in deep submicron technologies the range of resistances of the defects majority is raised from a few hundreds Ohms [ 151 to the order of few KOhms [6, 161, reducing the value of IDF.

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A promising technique to overcome the above problems with IDDQ testing can be summarized as follows. A Leakage Compensation Circuitry (LCC) is used in order to compensate at the sensing node the expected background current IB of the CUT during testing. The topology of the proposed IDDQ testing scheme is given in Fig. 2. During each test session the LCC bypass a current I C M p from the sensing node V-Gnd to the ground equal to the expected background current IB of the CUT minus the leakage current I m G of transistor MNG.

Gnd Figure 1. Conventional IDDQ testing scheme

I C M P = IB

2. IDDQtesting technique for deep submicron technologies

- IMNG

This way the threshold current ITH of the BICS can be kept low without the risk of sensor activation during testing in the defect free case, while any additional, over the threshold current ITH, defective IDDQ current (IDF) to the sensing node will be detected by the BICS. The LCC can be designed using a small reference current source IN along with a current amplifier in order to produce a compensation current I c M P = P I N from the virtual ground V-Gnd to the ground Gnd equal to the background current I B of the CUT (more precisely I C M p = P I R L = I B - IMNG), as it is illustrated in Fig. 3. Obviously, this reference current IN should be as small as possible. A drawback of the above scheme, that uses a fixed reference current, is that it is not possible to encounter the leakage current variations of the CUT arising due to the

In Fig. 1 the general structure for IDDQ testing using a Built-In Current Sensor (BICS) is given. The Circuit Under Test (CUT) is isolated from the ground supply (Gnd) with the use of an NMOS transistor MNG while the BICS is connected to virtual ground (V-Gnd) of the CUT. During the normal mode of operation T-ENB is high, thus the transistor MNG is on and V-Gnd E Gnd while the current sensor is disabled. In the test mode of operation the signal T-ENB turns low, the transistor MNG is at the off state while the BICS is active and capable to detect any excessive IDDQcurrent stemming from a defect in the CUT. Considering this topology the BICS should not be

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accomplished with the transistor M N G that gives the virtual ground at the sensing node and enables the testing operation. The parasitic capacitance at the sensing node is supposed to be Cv~ND=500fF. The range of bridging faults resistances’ R was from lKOhm to 3OOKOhms with a power supply of 1.W. The simulation results are presented in Fig. 7. According to these simulations, the BICS is efficiently activated when the bridging fault is present and the LCC is active (Fig 7c). Furthermore, the erroneous activation of the BICS due to the background current of the CUT when the LCC

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is inactive, utilizing the transistor M N S , which is controlled by the signal SEL, is illustrated Fig 7d. Note the faster response of the sensor in the detection of the 300KOhm resistive fault in the case where the LCC is inactive due to the contribution of the background current.

4. Conclusions IDDQ testing has become an important contributor to quality improvement of CMOS ICs. However, for future deep submicron technologies, the discrimination of the 13

defective and the non-defective I D o Q currents is expected to become more critical due to the manufacturing improvements which have enabled a reduction of the minimum feature size as well as an increase of chip sizes. In order to be able to exploit IDDQ benefits in the deep submicron world it is of major concern to provide new solutions. Towards this direction, a new scheme for lDDQ testing has been presented that during testing eliminates the leakage current from the sensing node enabling current sensors to detect currents stemming from defects. The efficiency of the proposed technique has been validated by simulations.

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5. References M. Sachdev, “Deep Sub-micron IDDO Testing: Issues and Solutions”, European Design and Test Conference (ED&TC), pp. 271-278, 1997. A.E. Gattiker and W. Maly, “Toward Understanding “lll~~o-Only” Fails”, International Test Conference, 1998. T.Wr Williams, R.H. Dennard, R. Kapur, M.R. Mercer and W. Maly, “IDl10 Test: Sensitivity Analysis ofScaling”, International Test Conference, pp. 786-792, 1996. S. Kundu, “IDDO Defect Detection in Deep Submicron CMOS ICs”, Asian Test Symposium, 1998. A. Ferre and J. Figueras, “IDD0 Characterization in Submicron CMOS’, International Test Symposium, pp. 136-145, 1997. R.R. Montanes and J. Figueras, “Estimation of the Defective Ill,lO Caused by Shorts in Deep Submicron CMOS ICs”, Design Automation and Test in Europe (DATE’98), 1998. A. Keshavarzi, K. Roy and C.F. Hawkins, “Intrinsic Leakage in Low Power Deep Submicron CMOS ICs”, International Test Conference, 1997. J.M. Soden, C.F. Hawkins and A.C. Miller, “Identrfiing Defects in Deep Submicron CMOS ICs” IEEE Spectrum, pp. 66-71, September 1996. J.M. Soden and C.F. Hawkins, “Illllo Testing: Issues Present and Future”, IEEE Design and Test of Computers, pp. 6 1-65, Winter 1996. S. Borkar, “Design Challenges of Technology Scaling”, IEEE Micro, pp. 23-29, July-August, 1999. M. Haond, M-T Basso, W. deCoster, E. Gerritsen, J. Guelen and C. Lair, “Developing a 0.I8p CMOS Process”, IEEE Micro, pp. 16-22, Sept.-Oct. 1999.

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