are the source degeneration, double differential pair and the adaptive biasing. Two current division networks (CDNs) are used to control the value of the ...
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Third-Order Elliptic Lowpass Filter for Multi-Standard Baseband Chain Using Highly Linear Digitally Programmable OTA To cite this article: Mohamed B. Elamien and Soliman A. Mahmoud 2018 IOP Conf. Ser.: Mater. Sci. Eng. 341 012005
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International Conference on Applied Electronic and Engineering 2017 (ICAEE2017) IOP Publishing IOP Conf. Series: Materials Science and Engineering 341 (2018) 012005 doi:10.1088/1757-899X/341/1/012005 1234567890‘’“”
Third-Order Elliptic Lowpass Filter for Multi-Standard Baseband Chain Using Highly Linear Digitally Programmable OTA Mohamed B. Elamien and Soliman A. Mahmoud Department of Electrical and Computer Engineering, University of Sharjah, UAE E-mail: {melamien, solimanm}@sharjah.ac.ae Abstract. In this paper, a third-order elliptic lowpass filter is designed using highly linear digital programmable balanced OTA. The filter exhibits a cutoff frequency tuning range from 2.2 MHz to 7.1 MHz, thus, it covers W-CDMA, UMTS, and DVB-H standards. The programmability concept in the filter is achieved by using digitally programmable operational transconductors amplifier (DPOTA). The DPOTA employs three linearization techniques which are the source degeneration, double differential pair and the adaptive biasing. Two current division networks (CDNs) are used to control the value of the transconductance. For the DPOTA, the third-order harmonic distortion (HD3) remains below -65 dB up to 0.4 V differential input voltage at 1.2 V supply voltage. The DPOTA and the filter are designed and simulated in 90 nm CMOS technology with LTspice simulator.
1. Introduction Multi-standard systems have become indispensable in today wireless and wireline communication. Through these systems, it is possible to connect to networks using a variety of communication standards inducing Bluetooth, W-CDMA, UMTS, DVB-H and IEEE 802.11a/g standards. The multi-mode filter is a fundamental component in these systems. It serves as a channel selector by adjusting its bandwidth with regards to the targeted standard specifications[1], [2]. The main adopted structures for implementing the multi-mode filter are the Gm-C, activeRC and MOSFET-C. For high frequency and low power application, the Gm-C structure is preferable due to the open loop operation of the operational transconductor amplifier (OTA). On the other hand, the active-RC and MOSFET-C structures consume high power in the highfrequency applications because they use local feedback around the active elements [3]. The main disadvantage of the Gm-C filter is the high nonlinearity due to the open loop operation of the used OTA. Hence, many techniques have been reported in the literature in order to enhance the linearity of the OTA [4]. The paper is organized as follow: Sec. 2 presents the design of the digitally programmable OTA and the current division network. Sec. 3 illustrates the proposed third-order elliptic lowpass filter. The simulation results of the DPOTA and the complete filter are given in Sec. 4. In [5], the same proposed DPOTA is used to implement a 4th-order Butterworth lowpass filter for multi-standard receiver baseband chain. However, the elliptic transfer function has the best selectivity among all other types.
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International Conference on Applied Electronic and Engineering 2017 (ICAEE2017) IOP Publishing IOP Conf. Series: Materials Science and Engineering 341 (2018) 012005 doi:10.1088/1757-899X/341/1/012005 1234567890‘’“”
2. Digitally Programmable OTA The presented DPOTA circuit employs three different linearization techniques [6], [5]. The first technique is the source degeneration using MOS transistors [7] in which a resistance is connected between the two sources of the differential pair’s transistors. The resistance can be implemented by a resistor or by MOS transistors working in the linear region. In the case of using a resistor of value (R), to improve the linearity significantly a large R is needed. However, the overall transconductance will be limited (Gm ≈ (1/R)). The second technique is the adaptive biasing [8], the concept of adaptive biasing allows the input voltage to contribute in the biasing current. Hence, the non-linear term is canceled by the input voltage. The third technique is the double differential pair, which enhances the linearity performance by canceling the third-order distortion[9]. A common mode feedback circuit (CMFB) is added to the balanced OTA. The CMOS realization of the balanced OTA is shown in Fig. 1. Each of the following pairs of transistors are identical (M1 , M2 ), (M3 , M4 ), (M5 , M6 ) and (M7 , M8 ). The transistors M5 , M6 , M7 , M8 operate in linear region. Then the output differential current of the first source degenerated differential pairs is given by √ Kn1 V 2 2Kn1 IT 1 Vd 1 − 2 d (1) Io = I1 − I2 = a1 8a1 IT 1 where a1 = 1 + (Kn1 /4Kn5 ). From Taylor expanding, the third-order distortion is canceled if the following condition is satisfied IT 1 Kn1 3 a2 6 =( ) ( ) IT 2 Kn3 a1
(2)
By proper transistors sizing and choosing proper biasing currents according to (2), the thirdorder harmonic distortion can be eliminated. However, due to mobility degradation effect, the third-order harmonic can be reduced only. The biasing voltage Vb is used to bias the squaring circuits in order to achieve the maximum linearity. VDD
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Figure 1. The CMOS realization of the proposed OTA. The squaring circuit [8] is added to the proposed OTA to make the biasing currents adaptive to the input voltage. Then the non linear terms in each differential pair is reduced. 2
International Conference on Applied Electronic and Engineering 2017 (ICAEE2017) IOP Publishing IOP Conf. Series: Materials Science and Engineering 341 (2018) 012005 doi:10.1088/1757-899X/341/1/012005 1234567890‘’“”
NMOS CDC 2
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Figure 2. Three-bit CDN CMOS realization [10]. 2.1. The current division network The programmability concept in the presented DPOTA is introduced by using two current division network circuits [10] as shown in Fig. 2. The adopted CDN based on cascaded NMOS current division cell (CDC) by PMOS CDC. It has no restriction on the number of the controlling bits due to the supply voltage limitation where the voltage levels are generated from one cell to another. Moreover, the structure of the CDC has the advantages of the low input impedance and high output impedance. Hence, no need for virtual ground nodes [10]. Also, this CDN can divide bidirectional input current and the transistors matching requirements are relaxed since only the transistors within each CDC required to be matched. Each of the two output currents (Io1 ,Io2 ) of the proposed OTA in Fig. 1 is connected as input for one CDN. The two CDNs are controlled by 3-bit word (a0 ,a1 ,a2 ). The 3-bit CDN circuit divides the input current with controlling factor (α), that can be expressed as i=n−1 1 2i a i α= n 1+ 2 i=0
(3)
where n is the number of the digital control bits. The adopted tuning technique preserve the overall linearity performance of the proposed OTA. The overall output currents of the proposed digital programmable OTA is given by Iout1 = −Iout2 = α(a0 , a1 , a2 )Gm (V1 − V2 )
(4)
where Gm is the transconductance value. The current gain α(a0 , a1 , a2 ) is a function of the digital control bits as explained in (3). 3. Third-Order Elliptic Lowpass Filter Design A third-order elliptic lowpass filter is designed using the presented DPOTA. The elliptic transfer function has the best selectivity, however it suffers from the ripples in pass and stop bands. The passive implementation of the filter is shown in Fig. 3. F ully differential implementation of the filter using seven identical DPOTA and five capacitors is shown in Fig. 4, where the passive inductor is implemented by four DPOTA (Gm3 − Gm6 ) based on gyrator-C structure. Gm2 and Gm7 implement active resistors and Gm1 acts as buffer transconductance. The values of the capacitors are extracted such that to make the tuning over WCDMA (2.2 MHz), UMTS (5 MHz) and DVB-H (7 MHz) standards. The capacitance of C1 , C2 , C3 and Ci are 0.2 pF, 0.2 pF, 50 fF and 0.2 pF, respectively. The cutoff frequency of filter can be tuned digitally from 3
International Conference on Applied Electronic and Engineering 2017 (ICAEE2017) IOP Publishing IOP Conf. Series: Materials Science and Engineering 341 (2018) 012005 doi:10.1088/1757-899X/341/1/012005 1234567890‘’“”
2.2 kHz to 7.1 MHz by changing the digital input of the DPOTA. More pass-band gain can be achieved by increasing the transconductance of Gm1 . L1 C3
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Figure 3. The passive prototype of the third-order elliptic lowpass filter.
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Figure 4. The active implementation of the third-order elliptic lowpass filter.
4. The Simulation Results 4.1. DPOTA simulation The proposed circuit is validated through simulation tests. LTspice simulator is used with 90 nm BSIM4 (level 54) technology under ±0.6 V supply voltage. Fig. 5 shows the transconductance of the proposed programmable OTA while α is varied from 0.125 to 1 with 0.125 steps. The values of the transconductance can be controlled from 11.65 μA/V to 93.5 μA/V. The output differential current versus the input differential voltage is shown in Fig. 6. The linearity performance of the proposed OTA is evaluated by measuring the third harmonic distortion (HD3) of the differential output current while the input voltage frequency is 10 MHz and peak to peak amplitude is varied from 0.1 V to 0.5 V. Fig. 9 shows that the HD3 remains below -60 dB. The bandwidth of the OTA is varying from 68 MHz to 74.2 MHz as shown in Fig. 10. Fig. 7 shows the input referred noise spectral density which is inversely proportional to α, at 1 MHz and for (α = 0.125) it is √ √ 268 nV/ Hz while for (α = 1) it is 139.6 nV/ Hz. The overall power consumption of the OTA is 669 μW as shown in Fig. 8. 4.2. The filter simulation The proposed filter in Fig. 4 is simulated in 90 nm CMOS technology with LTspice simulator. The filter consumes 4.68 mW under 1.2 V supply voltage. The magnitude response of the filter in Fig .11 shows the tuning range from 2.2 MHz to 7.1 MHz. The filter simulation results are summarized in table 2. The DC gain, cutoff frequency, the input referred noise and the thirdorder inter-modulation distortion at an input voltage of 200 mVpp amplitude with frequencies 0.8 MHz and 0.9 MHz for LPF are given.
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International Conference on Applied Electronic and Engineering 2017 (ICAEE2017) IOP Publishing IOP Conf. Series: Materials Science and Engineering 341 (2018) 012005 doi:10.1088/1757-899X/341/1/012005 1234567890‘’“”
40
α=1 α=0.875 α=0.75 α=0.625 α=0.5 α=0.375 α=0.25 α=0.125
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Figure 5. The transconductance of the proposed programmable OTA while α is varied from 0.125 to 1 with 0.125 steps.
Figure 6. The output differential current of the proposed programmable OTA while α is varied from 0.125 to 1 with 0.125 steps.
120
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Input Referred Noise (μV/ Hz)
α=1 α=0.875 α=0.75 α=0.625 α=0.5 α=0.375 α=0.25 α=0.125
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Figure 7. The input referred noise for minimum and maximum α.
Figure 8. The total power consumption.
Table 1. Main specifications of the proposed DPOTA Specifications
This work
Supply volyage (V) Power dissioation (μW) Transconductance (μA/V) Controlling bits √ Input referred noise (nV/ Hz) Technology
± 0.6 669 11.65 - 93.5 3 268.5 - 139.6 90 nm
5
International Conference on Applied Electronic and Engineering 2017 (ICAEE2017) IOP Publishing IOP Conf. Series: Materials Science and Engineering 341 (2018) 012005 doi:10.1088/1757-899X/341/1/012005 1234567890‘’“”
-60
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Transconductance (μA/V)
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Figure 10. The frequency response of the proposed programmable OTA while α is varied from 0.125 to 1 with 0.125 steps.
Figure 9. The third-order harmonic distortion of the differential output current at the maximum transconductance value.
Magnitude Response (dB)
10 0 -10 -20 -30 -40 -50 2 10
W-CDMA UMTS DVB-H 3
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Figure 11. The magnitude response of the filter.
Table 2. Third-order elliptic lowpass simulation results for different standards. Parameter
W-CDMA
UMTS
DVB-H
Cutoff Frequency (MHz) DC Gain (dB) IM3 (dB) √ Input referred noise (nV/ Hz)
2.2 -1.15 -27 451.6
4.5 0.09 -36.54 370.7
7.1 0.99 -47.3 447.3
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International Conference on Applied Electronic and Engineering 2017 (ICAEE2017) IOP Publishing IOP Conf. Series: Materials Science and Engineering 341 (2018) 012005 doi:10.1088/1757-899X/341/1/012005 1234567890‘’“”
5. Conclusion A digital programmable OTA with linearity enhancement has been proposed. The adopted linearity techniques are the source degenerated using MOS transistor, double differential pair and the adaptive biasing. The tuning capability is introduced by using 3-bit current division network. The adopted tuning technique preserves the overall DPOTA linearity performance. The DPOTA consumes 669 μW under 1.2 V supply voltage. The proposed DPOTA performance has been evaluated through LTspice simulator using 90 nm technology. The simulation results shows HD3 of the DPOTA is below -60 dB up to 0.5 V differential input voltage. A third-order elliptic lowpass filter is designed using the proposed DPOTA. The filter cutoff frequency can be tuned from 2.2 MHz to 7.1 MHz which makes it suitable for multi-standard systems. References [1] S. Hori, T. Maeda, N. Matsuno, and H. Hida, “Low-power widely tunable gm-c filter with an adaptive dcblocking, triode-biased mosfet transconductor,” in Solid-State Circuits Conference, 2004. ESSCIRC 2004. Proceeding of the 30th European, pp. 99–102, IEEE, 2004. [2] S. A. Mahmoud and E. A. Soliman, “Multi-standard receiver baseband chain using digitally programmable ota based on ccii and current division networks,” Journal of Circuits, Systems and Computers, vol. 22, no. 04, p. 1350019, 2013. [3] J. Chen, E. Sanchez-Sinencio, and J. Silva-Martinez, “Frequency-dependent harmonic-distortion analysis of a linearized cross-coupled cmos ota and its application to ota-c filters,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 53, no. 3, pp. 499–510, 2006. [4] D. A. Johns and K. Martin, Analog integrated circuit design. John Wiley & Sons, 2008. [5] M. B. Elamien and S. A. Mahmoud, “Multi-standard lowpass filter for baseband chain using highly linear digitally programmable ota,” in 40th International Conference on Telecommunications and Signal Processing, (Barcelona, Spain), 2017 (unpublised yet). [6] M. B. Elamien and S. A. Mahmoud, “A linear cmos balanced output transconductor using double differential pair with source degeneration and adaptive biasing,” in IEEE 59th MWSCAS, pp. 253–256, 2016. [7] F. Krummenacher and N. Joehl, “A 4-mhz cmos continuous-time filter with on-chip automatic tuning,” Solid-State Circuits, IEEE Journal of, vol. 23, no. 3, pp. 750–758, 1988. [8] K.-C. Kuo and A. Leuciuc, “A linear mos transconductor using source degeneration and adaptive biasing,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 48, no. 10, pp. 937–943, 2001. [9] C. Popa and O. Mitrea, “Constant g m rail-to-rail cmos input stage with improved linearity,” in Image and Signal Processing and Analysis, 2001. ISPA 2001. Proceedings of the 2nd International Symposium on, pp. 511–515, IEEE, 2001. [10] S. A. Mahmoud, M. A. Hashiesh, and A. M. Soliman, “Low-voltage digitally controlled fully differential current conveyor,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 52, no. 10, pp. 2055– 2064, 2005.
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