Tutorial on Digital Phase-Locked Loops

Tutorial on Digital Phase-Locked Loops CICC 2009 Michael H. Perrott September 2009

Copyright © 2009 by Michael H. Perrott

Why Are Digital Phase-Locked Loops Interesting?

ƒ

Performance is important

ƒ

The standard analog PLL implementation is problematic in many applications

- Phase noise can limit wireless transceiver performance - Jitter can be a problem for digital processors - Analog building blocks on a mostly digital chip pose design and verification challenges - The cost of implementation is becoming too high … Can digital phase-locked loops offer excellent performance with a lower cost of implementation?

M.H. Perrott

2

Just Enough PLL Background …

What is a Phase-Locked Loop (PLL)? ref(t)

ref(t)

out(t)

out(t)

e(t)

v(t) ref(t)

Phase Detect

e(t)

e(t)

v(t)

v(t) Analog Loop Filter

out(t)

VCO

ƒ ƒ

de Bellescize Onde Electr, 1932

VCO efficiently provides oscillating waveform with variable frequency PLL synchronizes VCO frequency to input reference frequency through feedback

- Key block is phase detector

ƒ Realized as digital gates that create pulsed signals M.H. Perrott

4

Integer-N Frequency Synthesizers ref(t) div(t) e(t)

v(t) Fout = N Fref

ref(t)

Phase Detect

e(t)

v(t) Analog Loop Filter

out(t)

VCO div(t)

Divider

Sepe and Johnston US Patent (1968)

N

ƒ

Use digital counter structure to divide VCO frequency

ƒ

Use PLL to synchronize reference and divider output

- Constraint: must divide by integer values

Output frequency is digitally controlled M.H. Perrott

5

Fractional-N Frequency Synthesizers Kingsford-Smith US Patent (1974)

ref(t)

Wells US Patent (1984)

div(t) e(t)

v(t)

Fout = M.F Fref ref(t)

Phase Detect

e(t)

v(t) Analog Loop Filter

out(t)

VCO div(t) Nsd[k]

ƒ

Divider Σ−Δ Modulator

N[k]

Riley US Patent (1989) JSSC ‘93 M.F

Dither divide value to achieve fractional divide values

- PLL loop filter smooths the resulting variations

Very high frequency resolution is achieved M.H. Perrott

6

The Issue of Quantization Noise ref(t) div(t) e(t)

v(t) Fout = M.F Fref

ref(t)

Phase Detect

e(t)

v(t) Analog Loop Filter

out(t)

VCO div(t) Nsd[k]

ƒ ƒ

Divider Σ−Δ Modulator

N[k]

M.F

Σ−Δ Quantization Noise

Limits PLL bandwidth Increases linearity requirements of phase detector

M.H. Perrott

f 7

Striving for a Better PLL Implementation

Analog Phase Detection

ref(t)

1 D Q reset

div(t)

1 D Q Reg

ref(t)

phase error

error(t)

Phase Detect

ref(t) div(t) error(t)

out(t)

Analog Loop Filter VCO

div(t)

ƒ ƒ

M.H. Perrott

Divider

Pulse width is formed according to phase difference between two signals Average of pulsed waveform is applied to VCO input

9

Tradeoffs of Analog Approach

ref(t) div(t) error(t)

ref(t)

Phase Detector Characteristic

Average of error(t)

Phase Detector Signals

phase error

Phase Detect

out(t)

Analog Loop Filter VCO

div(t)

ƒ ƒ

Divider

Benefit: average of pulsed output is a continuous, linear function of phase error Issue: analog loop filter implementation is undesirable

M.H. Perrott

10

Issues with Analog Loop Filter

error(t)

Charge Pump

Vout Icp Cint

ref(t)

Phase Detect

out(t)

Analog Loop Filter VCO Divider

ƒ ƒ M.H. Perrott

Charge pump: output resistance, mismatch Filter caps: leakage current, large area 11

Going Digital … ref(t)

Phase Detect

out(t)

Analog Loop Filter VCO Divider

ref(t)

Time -toDigital

out(t)

Digital Loop Filter DCO Divider

ƒ ƒ M.H. Perrott

Staszewski et. al., TCAS II, Nov 2003

Digital loop filter: compact area, insensitive to leakage Challenges:

- Time-to-Digital Converter (TDC) - Digitally-Controlled Oscillator (DCO)

12

Outline of Talk

ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ

M.H. Perrott

Overview of Key Blocks (TDC and DCO) Modeling & CAD Tools High Performance TDC design Quantization Noise Cancellation DCO based on an efficient passive DAC structure Divider Design Loop Filter Design Prototype with measured Results

13

Classical Time-to-Digital Converter div(t)

Delay

Delay

Delay

Delay

div(t) D Q

D Q

D Q

Reg

Reg

Reg

1 1 1 0 0

e[k]

e[k]

ref(t)

ref(t)

ref(t)

Time -toDigital div(t)

out(t)

Digital Loop Filter DCO Divider

ƒ

Resolution set by a “Single Delay Chain” structure

ƒ

Corresponds to a flash architecture

M.H. Perrott

- Phase error is measured with delays and registers

14

Impact of Limited Resolution and Delay Mismatch div(t)

1 1 1 0 0

e[k]

Phase Detector Characteristic

detector output

Delay varies due to mismatch

phase error

ref(t)

ref(t)

Time -toDigital div(t)

ƒ

Integer-N PLL

ƒ

Fractional-N PLL

out(t)

Digital Loop Filter DCO Divider

- Limit cycles due to limited resolution (unless high ref noise) - Fractional spurs due to non-linearity from delay mismatch

M.H. Perrott

15

Modeling of TDC quantization error

detector output

Phase Detector Characteristic

tq[k]

1 Δtdel time error

ref(t) T reference period

Time -toDigital div(t)

phase error[k]

T 2π

TDC Gain 1 Δtdel

e[k]

out(t)

Digital Loop Filter DCO Divider

ƒ Phase error converted to time error by scale factor: ƒ TDC introduces quantization error: tq[k] ƒ TDC gain set by average delay per step: Δtdel M.H. Perrott

T/2π

16

A Straightforward Approach for Achieving a DCO

ref(t)

Time -toDigital div(t)

ƒ M.H. Perrott

Varactor

Varactor

DAC

Analog Control

out(t)

Digital Loop Filter DCO Divider

Ferriss ISSCC 2007 Hsu ISSCC 2008

Use a DAC to control a conventional LC oscillator

- Allows the use of an existing VCO within a digital PLL - Can be applied across a broad range of IC processes

17

A Much More Digital Implementation

Varactor

Varactor ref(t)

Time -toDigital div(t)

ƒ M.H. Perrott

Digital Control

out(t)

Digital Loop Filter DCO Divider

Staszewski et. al., TCAS II, Nov 2003

Adjust frequency in an LC oscillator by switching in a variable number of small capacitors

- Most effective for CMOS processes of 0.13u and below

18

Leveraging Segmentation in Switched Capacitor DCO

Varactor

Fine Control

Varactor

Coarse Control

Binary Array 1x

2x

4x

2 nx

Unit Element Array 1x

1x

1x

1x

ƒ

Similar in design as segmented capacitor DAC structures

ƒ

Coarse and fine control segmentation of DCO

- Binary array: efficient control, but may lack monotonicity - Unit element array: monotonic, but complex control

- Coarse control: active only during initial frequency tuning (leverage binary array) - Fine control: controlled by PLL feedback (leverage unit element array to guarantee monotonicity)

M.H. Perrott

19

Leveraging Dithering for Fine Control of DCO

out(t)

Varactor

Varactor

ref(t)

Tuning Fine Control

in[k] Digital Loop Filter

Digital Σ−Δ Modulator

Divide-by-K T c=T/M

ƒ ƒ

T

Coarse Initial Control Frequency

DCO

TDC out

Increase resolution by Σ−Δ dithering of fine cap array Reduce noise from dithering by

- Using small unit caps in the fine cap array - Increasing the dithering frequency (defined as 1/T ) c

M.H. Perrott

ƒ We will assume 1/Tc = M/T (i.e. M times reference frequency)

20

Calculation of Noise Spectrum: Switched Cap DCO

Phase noise

- Same as for

conventional VCO (tank Q, etc.)

ƒ

Varactor

Varactor

ƒ

Digital Control

Quantization Noise

Hntf(z)

Quantization noise from dithering

- See Section 3

of Supplemental Slides

M.H. Perrott

f

Phase Noise

qraw[k] z=ej2πfTc

f

q[k]

in[k] M

Tc

2πKv s

Φout(t)

s=j2πf 21

Modeling

Overall Digital PLL Model TDC

DCO DCO-referred Noise S Φn(f)

TDC-referred Noise S tq(e j2πfT) f tq[k] Φref[k]

T 2π

-20 dB/dec

f TDC Gain 1 Δtdel

Loop Filter

DT-CT

e[k] H(z)

T

z=ej2πfT Φdiv[k]

Φn(t) 2πKv s s=j2πf

Φout(t)

Divider CT-DT 1 N

ƒ ƒ

1 T

TDC and DCO-referred noise influence overall phase noise according to associated transfer functions to output Calculations involve both discrete and continuous time

M.H. Perrott

23

Key Transfer Functions tq[k] Φref[k]

T 2π

TDC Gain 1 Δtdel

Loop Filter

DT-CT

e[k] H(z)

T

z=ej2πfT

Φdiv[k]

Φn(t) 2πKv s

Φout(t)

s=j2πf CT-DT

1 N

ƒ

TDC-referred noise

ƒ

DCO-referred noise

M.H. Perrott

1 T

24

Introduce a Parameterizing Function tq[k] Φref[k]

T 2π

TDC Gain 1 Δtdel

Loop Filter

DT-CT

e[k] H(z)

Φn(t)

T

2πKv s

z=ej2πfT

Φdiv[k]

Φout(t)

s=j2πf CT-DT

1 N

1 T

ƒ

Define open loop transfer function A(f) as:

ƒ

Define closed loop parameterizing function G(f) as:

- Note: G(f) is a lowpass filter with DC gain = 1

M.H. Perrott

25

Transfer Function Parameterization Calculations

ƒ

TDC-referred noise

ƒ

DCO-referred noise

M.H. Perrott

26

Key Observations tq[k] Φref[k]

T 2π

TDC Gain 1 Δtdel

Loop Filter

DT-CT

e[k] T

H(z) z=ej2πfT

Φdiv[k]

Φn(t) 2πKv s

Φout(t)

s=j2πf CT-DT

1 N

ƒ

1 T

TDC-referred noise Lowpass with a DC gain of 2πN

ƒ

DCO-referred noise Highpass with a high frequency gain of 1 How do we calculate the output phase noise?

M.H. Perrott

27

Spectral Density Calculations x(t) CT

CT

y(t) H(f)

x[k] DT

y[k] H(ej2πfT)

DT

y(t)

x[k] DT

ƒ

CT

CT

ƒ

DT

DT

ƒ

DT

CT

M.H. Perrott

CT

H(f)

28

Phase Noise Calculation TDC-referred Noise S tq(e j2πfT)

DCO-referred Noise S Φn(f)

-20 dB/dec

f tq[k] fo

ƒ

f Φn(t)

2πN G(f)

TDC noise

- DT to CT calculation - Dominates PLL phase

noise at low frequency offsets

1-G(f)

fo

ƒ

Φout(t)

DCO noise

- CT to CT calculation - Dominates PLL phase

noise at high frequency offsets

2 1 2πN G(f) S tq(e j2πfT) T 2

1- G(f) S Φn(f) dBc/Hz

fo M.H. Perrott

f 29

Example Calculation for Delay Chain TDC

ƒ

Ref freq = 1/T = 50 MHz, Out freq = 3.6 GHz

2

Δtdel 12

S tq(e j2πfT)

f tq[k]

ƒ

Inverter delay = Δtdel = 20 ps

fo

S Φout(f)

2πN G(f)

1 2πN G(f) T

2 2 Δtdel

12

tdc

fo

ƒ

f

Note: G(f) = 1 at low offset frequencies

M.H. Perrott

30

CAD Tools

Closed Loop PLL Design Approach

Closed-Loop Performance Specifications {f o, type, order}

Open-Loop Design Approach

Open-Loop Characteristics |A(f)| A(f) {K,f p,f z, ...}

G(f) =

A(f) =

A(f) 1+A(f)

G(f) 1-G(f)

Proposed Closed Loop Design Approach

ƒ

Classical open loop approach

ƒ

Proposed closed loop approach

Closed-Loop Transfer Function G(f)

Lau and Perrott, DAC, June 2003

- Indirectly design G(f) using bode plots of A(f) - Directly design G(f) by examining impact of its specifications on phase noise (and settling time) - Solve for A(f) that will achieve desired G(f) Implemented in PLL Design Assistant Software http://www.cppsim.com

M.H. Perrott

32

Evaluate Phase Noise with 500 kHz PLL Bandwidth

ƒ

Key PLL parameters:

- G(f): 500 kHz BW, Type II, 2 order rolloff - TDC noise: -94.7 dBc/Hz - DCO noise: -153 dBc/Hz at 20 MHz offset (3.6 GHz carrier) nd

M.H. Perrott

33

Calculated Phase Noise Spectrum with 500 kHz BW Output Phase Noise of Synthesizer

-60

Detector Noise VCO Noise Total Noise

-70

GSM Mask (Referenced to 3.6 GHz carrier)

-80

L(f) (dBc/Hz)

-90

Overall PLL Phase Noise TDC Noise

-100 -110 -120 -130

DCO Noise

-140 -150 -160 3 10

10

4

10

5

10

6

10

7

Frequency Offset (Hz)

TDC noise too high for GSM mask with 500 kHz PLL bandwidth M.H. Perrott

34

Change PLL Bandwidth to 100 kHz

ƒ

Key PLL parameters:

- G(f): 100 kHz BW, Type = 2, 2 order rolloff - TDC noise: -94.7 dBc/Hz - DCO noise: -153 dBc/Hz at 20 MHz offset (3.6 GHz carrier) nd

M.H. Perrott

35

Calculated Phase Noise Spectrum with 100 kHz BW Output Phase Noise of Synthesizer

-60

Detector Noise VCO Noise Total Noise

-70 -80

Overall PLL Phase Noise

-90

L(f) (dBc/Hz)

GSM Mask (Referenced to 3.6 GHz carrier)

TDC Noise

-100 -110

DCO Noise -120 -130 -140 -150 -160 3 10

4

10

5

10

6

10

7

10

Frequency Offset (Hz)

GSM mask is met with 100 kHz PLL bandwidth M.H. Perrott

36

Loop Filter Design using PLL Design Assistant

ƒ

PLL Design Assistant allows fast loop filter design

- See Section 4 of Supplemental Slides

ƒ Assumption: Type = 2, 2nd order rolloff

- Where:

ƒ M.H. Perrott

PLL Design Assistant provides the values of K, wp = 2πfp, wz = 2πfz 37

Example Digital Loop Filter Calculation

ƒ

Assumptions

- Ref freq (1/T) = 50 MHz, Out freq = 3.6 GHz (so N = 72) - Δt = 20 ps, K = 12 kHz/unit cap - 100 kHz bandwidth, Type = 2 , 2 order rolloff del

v

nd

M.H. Perrott

38

Verify Calculations Using C++ Behavioral Modeling 1

1

D Q R

CppSim Module Description

R D Q

Name Inputs, Outputs Parameters Code

PFD

Charge Pump

ƒ

ƒ

- Hierarchical

description of system topology

ƒ

Loop Filter

Divider Σ−Δ Modulator

Schematic

CppSim Module Description Name Inputs, Outputs Parameters Code

Code blocks

- Specification of module behavior using templated C++ code

Behavioral environment allows efficient architectural investigation and validation of calculations

- Fast simulation speed is essential for design investigation

M.H. Perrott

39

CppSim – A Fast C++ Behavioral Simulator

http://www.cppsim.com M.H. Perrott

40

How Do We Improve TDC Performance? Two Key Issues: • TDC resolution • Mismatch

Motivation TDC-referred Noise S tq(e j2πfT)

DCO-referred Noise S Φn(f)

-20 dB/dec

f tq[k]

f Φn(t)

2πN G(f)

fo

ƒ

fo

PLL bandwidth dramatically influences relative impact of TDC and VCO noise Want high PLL bandwidth?

1-G(f)

Need low TDC Noise

Φout(t) Low PLL Bandwidth

High PLL Bandwidth

DCO Noise

dBc/Hz

dBc/Hz

TDC Noise

fo M.H. Perrott

TDC Noise

f

DCO Noise

fo

f 42

Improve Resolution with Vernier Delay Technique div(t)

Delay

Delay

Delay

Delay

div(t) D Q

D Q

D Q

Reg

Reg

Reg

e[k]

ref(t)

1 1 1 0 0

e[k]

1 1 1 0 0

e[k]

ref(t) Delay

div(t)

Vernier div(t)

ref(t)

M.H. Perrott

Delay

Delay

Delay

D Q

D Q

D Q

Reg

Reg

Reg

Delay2

Delay2

Delay2

ref(t)

Effective resolution: Delay-Delay2

e[k] Delay2

43

Issues with Vernier Approach

ƒ ƒ

Mismatch issues are more severe than the single delay chain TDC

- Reduced delay is formed as difference of two delays

Large measurement range requires large area

- Initial PLL frequency acquisition may require a large range Delay

div(t)

Vernier div(t)

ref(t)

M.H. Perrott

Delay

Delay

1 1 1 0 0

Delay

D Q

D Q

D Q

Reg

Reg

Reg

Delay2

Delay2

Delay2

e[k]

ref(t)

Effective resolution: Delay-Delay2

e[k] Delay2

44

Two-Step TDC Architecture Allows Area Reduction Single Delay Chain

Vernier Delay

div(t)

Delay

Delay

Delay

Delay

Delay Mux

D Q

D Q

D Q

Reg

Reg

Reg

ref(t)

D Q

D Q

D Q

Reg

Reg

Reg

Delay2

Delay2

Delay2

Logic

Ramakrishnan, Balsara VLSID ‘06

ƒ ƒ

Single delay chain provides coarse resolution (Folded) Vernier provides fine resolution

M.H. Perrott

Coarse e[k]

Fine e[k] Delay - Delay2

Delay

45

Two-Step TDC Using Time Amplification Single Delay Chain

div(t)

Delay

Delay

Single Delay Chain Time Amplifier Delay

Delay

Delay

Delay

Mux D Q

D Q

D Q

D Q

D Q

D Q

Reg

Reg

Reg

Reg

Reg

Reg

ref(t) Logic

Simplified view of: Lee, Abidi VLSI 2007

ƒ ƒ

Single delay chain provides coarse and fine resolution Time amplification is used to improve resolution

M.H. Perrott

Coarse e[k]

Fine e[k]

Delay

Delay

Amplification of Time

46

Leveraging Metastability to Create a Time Amplifier in(t) ref(t) in(t)

ref(t)

Time Amplifier out(t)

Δtin

D Q

out(t)

Latch

Δtin

ref(t)

ref(t)

in(t)

in(t)

out(t)

out(t) Δtout

Δtout

Simplified view of: Abas, et al., Electronic Letters, Nov 2002 (note that actual implementation uses SR latch)

ƒ

Metastability leads to progressively slower output transitions as setup time on latch is encroached upon

M.H. Perrott

- Time difference at input is amplified at output

47

Interpolating time-to-digital converter Tq

Start

Delay

Delay

Delay

1

Start

1 1 1

Stop

Tstop

Registers

Out

1 1 0

Out

Henzler et al., ISSCC 2008

ƒ ƒ

Stop Tin

Interpolate between edges to achieve fine resolution Cyclic approach can also be used for large range

M.H. Perrott

48

An Oscillator-Based TDC Ring Oscillator

Vdd

Phase Error[1]

Phase Error[2]

3

3

div(t) ref(t) Osc(t)

Reset ref(t)

Counter Logic

div(t)

Count[k] Register e[k]

ƒ ƒ

Count[k]

e[k]

Output e[k] corresponds to the number of oscillator edges that occur during the measurement time window Advantages

- Extremely large range can be achieved with compact area - Quantization noise is scrambled across measurements

M.H. Perrott

49

A Closer Look at Quantization Noise Scrambling Phase Error[1] Ring Oscillator

Vdd

Phase Error[2]

div(t) ref(t) Osc(t)

Reset ref(t)

Counter Logic

div(t)

Count[k] Register e[k]

ƒ ƒ

Count[k] q[1]

Quant. Error[k] -q[0] e[k]

q[3] -q[2]

3

3

Quantization error occurs at beginning and end of each measurement interval As a rough approximation, assume error is uncorrelated between measurements

- Averaging of measurements improves effective resolution

M.H. Perrott

50

Deterministic quantizer error vs. scrambled error

ƒ ƒ ƒ

Deterministic TDC do not provide inherent scrambling For oversampling benefit, TDC error must be scrambled! Some systems provide input scrambling (ΔΣ fractional-N PLL), while some others do not (integer-N PLL)

M.H. Perrott

51

Proposed GRO TDC Structure

A Gated Ring Oscillator (GRO) TDC Phase Error[1] Ring Oscillator

Phase Error[2]

div(t)

Enable ref(t) Osc(t) Reset ref(t)

Counter Logic

div(t)

Count[k] Register e[k]

Count[k] q[1]

Quant. Error[k] -q[0] e[k]

q[2] -q[1]

3

4

ƒ

Enable ring oscillator only during measurement intervals

ƒ

Quantization error becomes first order noise shaped!

- Hold the state of the oscillator between measurements - e[k] = Phase Error[k] + q[k] – q[k-1] - Averaging dramatically improves resolution!

M.H. Perrott

53

Improve Resolution By Using All Oscillator Phases Phase Error[1] Ring Oscillator

Phase Error[2]

div(t)

Enable ref(t)

Osc. Phases(t)

Reset ref(t)

Counters Logic

div(t)

Count[k] Register

Count[k]

e[k]

Helal, Straayer, Wei, Perrott VLSI 2007

Quant. Error[k] e[k]

q[1]

q[2] -q[1]

-q[0]

11

10

ƒ Raw resolution is set by inverter delay ƒ Effective resolution is dramatically improved by averaging M.H. Perrott

54

GRO TDC Also Shapes Delay Mismatch Enable

Measurement 1

Enable

Measurement 2

Enable

Measurement 3

Enable

Measurement 4

ƒ

Barrel shifting occurs through delay elements across different measurements

- Mismatch between delay elements is first order shaped!

M.H. Perrott

55

Simple gated ring oscillator inverter-based core Enabled Ring Oscillator

Disabled Ring Oscillator

(a)

(b)

Delay Element

Enable

Gate the oscillator by switching the inverter cores to the power supply

Enable

Vo n-1 Vo n

Vo 5

Vo 3

M.H. Perrott

M3

Vo i-1

Vo 1

Vo 4 Vo 2

M4

Vo i M2

Enable

M1

56

GRO Prototype enable 15 Stage Gated Ring Oscillator En Dis

S Q R

enable(t) enable

Straayer, Perrott

ƒ

M.H. Perrott

Logic

error[k]

GRO implemented as a custom 0.13 μm CMOS IC

57

Measured GRO Results Confirm Noise Shaping enable 15 Stage Gated Ring Oscillator Variable Delay

enable(t)

S Q R

enable 40

30

Input variable delay signal

Amplitude (dB)

20

Harmonics due to nonlinearity of variable delay

Logic

error[k]

10

0

-10

Noise shaped quant. noise

-20

-30 0.01

M.H. Perrott

0.1

1

Frequency (MHz)

10

100

58

Measured deadzone behavior of inverter-based GRO

ƒ ƒ ƒ ƒ

Deadzones were caused by errors in gating the oscillator GRO “injection locked” to an integer ratio of FS Behavior occurred for almost all integer boundaries, and some fractional values as well Noise shaping benefit was limited by this gating error

M.H. Perrott

59

Next Generation GRO: Multi-path oscillator concept Single Input Single Output

ƒ ƒ ƒ

Multiple Inputs Single Output

Use multiple inputs for each delay element instead of one Allow each stage to optimally begin its transition based on information from the entire GRO phase state Key design issue is to ensure primary mode of oscillation

M.H. Perrott

60

Multi-path inverter core Lee, Kim, Lee JSSC 1997

Mohan, et. al., CICC 2005

M.H. Perrott

61

Proposed multi-path gated ring oscillator

Hsu, Straayer, Perrott ISSCC 2008

ƒ ƒ ƒ

Oscillation frequency near 2GHz with 47 stages… Reduces effective delay per stage by a factor of 5-6! Represents a factor of 2-3 improvement compared to previous multi-path oscillators

M.H. Perrott

62

A simple measurement approach… N-Stage Gated Ring Oscillator Enable

Reset Start

Counters Logic

Stop

Count[k] Register e[k]

ƒ ƒ

Helal, Straayer, Perrott VLSI 2007

2 counters per stage * 47 stages = 94 counters each at 2GHz Power consumption for these counters is unreasonable Need a more efficient way to measure the multi-path GRO

M.H. Perrott

63

Count Edges by Sampling Phase

ƒ

Calculate phase from:

ƒ

1 counter and N registers Æ much more efficient

- A single counter for coarse phase information (keeps track of phase wrapping) - GRO phase state for fine count information

M.H. Perrott

64

Proposed Multi-Path Measurement Structure

ƒ ƒ

Multi-path structure leads to ambiguity in edge position Partition into 7 cells to avoid such ambiguity ƒ Requires 7 counters rather than 1, but power still OK

M.H. Perrott

65

Prototype 0.13μm CMOS multi-path GRO-TDC Start Timing Generation

Stop

Enable

CLK

47-stage Gated Ring Oscillator Z1-47 State Register

Start Stop Enable CLK

1 2 3 4 5 6 7 Measurement Cells

Adder

Out

Straayer et al., VLSI 2008

ƒ

Two implemented versions:

ƒ

2-21mW power consumption depending on input duty cycle

- 8-bit, 500Msps - 11-bit, 100Msps version

M.H. Perrott

66

Measured noise-shaping of multi-path GRO 65,536 pt. FFT

-50

ƒ ƒ ƒ ƒ

279.2

Input of 1.2pspp

-60 -70 -80 -90

-100

TDC Output after 1MHz LPF

(Hanning window + 20x averaging)

Filtered TDC Output

Power Spectral Density (dB ps2/Hz)

-40

Ideal variance of 50-Msps quantizer with 1ps steps

Noise of 80fsrms in 1MHz BW

104

105

106

107

279.0

278.8

1.2ps 278.6

0

40

80

120

Frequency (Hz)

Time (µ µs)

(a)

(b)

160

200

Data collected at 50Msps More than 20dB of noise-shaping benefit 80fsrms integrated error from 2kHz-1MHz Floor primarily limited by 1/f noise (up to 0.5-1MHz)

M.H. Perrott

67

Measured deadzone behavior for multi-path GRO

ƒ

Only deadzones for outputs that are multiples of 2N

ƒ

Size of deadzone is reduced by 10x

- 94, 188, 282, etc. - No deadzones for other even or odd integers, fractional output

M.H. Perrott

68

The Issue of Quantization Noise Due to Divider Dithering

The Nature of the Quantization Noise Problem Ref

Loop Filter

PFD

Out

Div N/N+1

1-bit Frequency M-bit ΔΣ Selection Modulator Quantization Noise Spectrum

Output Spectrum Noise

Frequency Selection

ƒ M.H. Perrott

Fout ΔΣ

PLL dynamics

Increasing PLL bandwidth increases impact of ΔΣ fractional-N noise

- Cancellation offers a way out!

70

Previous Analog Quantization Noise Cancellation

ƒ ƒ

Phase error due to ΔΣ is predicted by accumulating ΔΣ quantization error Gain matching between PFD and D/A must be precise

Matching in analog domain limits performance M.H. Perrott

71

Proposed All-digital Quantization Noise Cancellation

Hsu, Straayer, Perrott ISSCC 2008

ƒ ƒ

Scale factor determined by simple digital correlation Analog non-idealities such as DC offset are completely eliminated

M.H. Perrott

72

Details of Proposed Quantization Noise Cancellation

ƒ

Correlator out is accumulated and filtered to achieve scale factor

- Settling time chosen to be around 10 us

ƒ

See analog version of this technique in Swaminathan et.al., ISSCC 2007 M.H. Perrott

73

Proposed Digital Wide BW Synthesizer

ƒ ƒ ƒ M.H. Perrott

Gated-ring-oscillator (GRO) TDC achieves low in-band noise All-digital quantization noise cancellation achieves low out-of-band noise Design goals:

- 3.6-GHz carrier, 500-kHz bandwidth -