UWB Real-Time Testbed with Waveform-Based Precoding - CiteSeerX

UWB Real-Time Testbed with Waveform-Based Precoding Nan Guo, John Q. Zhang, Peng Zhang, Zhen Hu, Yu Song and Robert C. Qiu Department of Electrical and Computer Engineering Center for Manufacturing Research Tennessee Technological University Abstract—This paper reports recent progress in ultrawideband (UWB) radio testbed design and development. Experimental radio testbeds are ideal means to verify theoretically ideas, test feasibility, and reduce the uncertainty between theoretical expectation and practical implementation. The testbed under development has been designed as a general experimental platform to explore the advanced radio technologies, such as UWB based communications as well as ranging, physical layer security, optimum transmit waveforms, and cognitive radio. Our preliminary testbed includes a transmitter and a receiver, with a single UWB antenna at each side. It can be expanded to include multiple transmitters and receivers, multiple antennas at one or both sides, and a feedback link paired with the forward link. Programmability and flexibility are top concerns in the system design, and these two design goals are reflected throughout the three building blocks, i.e., baseband, mixed-signal and RF frontend. Two major contributions of the paper are: 1) providing the art of design and implementation with theoretical guideline; 2) demonstration of a set of end-to-end radio testbed for a wide range of research exploration—To our best knowledge, it is the first testbed with UWB time reversal function. Index Terms—ultra-wideband (UWB), time reversal, testbed.

I. I NTRODUCTION There is a trend to integrate cognitive radio with cognitive radar, together with anti-jamming capabilities. The advent of multi-GHz arbitrary waveform generators and the need for cognitive radio make this integration attractive. The multiGHz waveform provides super anti-jamming capabilities. The goal of this project is to investigate a novel paradigm of integrating the three ingredients; the multi-GHz waveform is jointly considered with the dynamic spectrum access. The primary challenge is caused by the wideband (multi-GHz) nature of the problem at hand. In principle, most of the processing at the receiver can be moved to the transmitter-where energy consumption and computation are sufficient for many advanced algorithms. This framework is called waveform-oriented pre-coding. It is different from traditional pre-equalization (or precoding), mainly because the modulation waveforms for the latter are fixed. The former counterpart, however, changes its modulation waveforms depending on the propagation environment. This is interesting since multi-GHz sampling is recently made feasible. The cost is, however, high. The ADC and DAC do not follow the Moores law, so this trend will not change in relatively long term. The wideband (multi-GHz) nature of the problem leads to time reversal [1][2][3][4][5][6][7], to exploit rich multipath. Waveform-based pre-coding such as time reversal needs to obtain up-to-date channel information at the transmitter, and the channel reciprocity is used to sound and estimate the

channel. As shown in [5], the uplink and downlink channels in the same frequency band have the same channel impulse response (CIR), which means the estimate based on uplink (downlink) channel sounding can be used in downlink (uplink). This channel reciprocity is especially meaningful when the system operates in time division duplex (TDD) manner. In addition, frequent channel sounding and estimation are not required in some scenarios like fixed or quasi-fixed wireless communications. Majority of low-complexity UWB systems reported in the literature aim at low data rate and do not deal with inter-symbol-interference (ISI) [8][9][10][11][12][13][14][15] [4][6][7]. Recently we have developed a radio testbed able to generate programmable waveforms with over-500-MHz bandwidth at the transmitter, aiming at simple receivers and high data rates in non-line-of-sight (NLOS) environments. Laboratorial radio testbeds are ideal means to verify theoretical ideas, test feasibility, and narrow uncertainty margins between theoretical expectation and practical implementation. The testbed is actually a general experimental platform to explore the most advanced radio technologies, such as UWB based communications as well as ranging, physical layer security, optimum transmit waveforms, and cognitive radio. Two major contributions of the paper are: 1) providing the art of design and implementation with theoretical guideline; 2) demonstration of an end-to-end radio testbed for a wide range of research explorations. To our best knowledge, it is the first radio testbed with UWB time reversal function. This paper is organized as follows. System level design issues are addressed in the next section. Provided in section III are details in implementation aspect. Test and experiment results are reported in section IV, followed by concluding remarks in section V. II. S YSTEMS D ESIGN C ONSIDERATIONS A. Overall Design Pulse based signaling and transmitter-side processing have been adopted as system design guideline. Although direct pulse (carrier less) transmission can largely reduce complexity of transmitter RF front-end, it is not a good choice for multipurpose radio testbed mainly because of its inflexibility. As a matter of fact, an RF modulated pulse is not only easy to generate, but also more flexible: the center frequency is determined by a local oscillator and the spectral shape is governed by the baseband pulse. Conceptual testbed architecture is shown in Figure 1 where all baseband and control functions are implemented using FPGAs. Following an FIR filter (embedded in the FPGA), the digital-to-analog converter

C. Transmit Waveforms Power Amplifier Baseline Transmitter

Programmable FIR Filter

DAC

Modulator

Coefficients Local Oscillator Baseband (Xilinx Virtex-5 FPGA)

Mixed Signal

RF

Transmitter

LNA Processing

Decision

ADC Detector Synchronization

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Mixed Signal

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Receiver

Fig. 1.

Overall testbed architecture.

(DAC) outputs desired analog waveforms. The simple-receiver philosophy is reflected in this testbed with on/off keying (OOK) or binary pulse position modulation (2-PPM) and diode based non-coherent detector at the receiver. Demodulation is done in digital domain, so that algorithms and parameters can be adjusted easily. Of course, the analog-to-digital converter (ADC) is power hungry and it may be replaced by some substitute circuits in commercialized products in the future. B. Calibration Phase This testbed has programmable transmit waveform function. To generate desired waveforms, the waveform generator at the transmitter has to be calibrated prior to regular data transmission. In addition, the receiver needs to set a proper amplification gain and decision thresholds priorly. Tasks in the calibration phase include channel sounding, channel estimation, FIR filter coefficient optimization, determining the amplification gain, and choosing the thresholds. In reality, the channel information can be obtained at either the transmitter or the receiver [5], but in either cases a feedback channel and some handshaking procedures are necessary. Considering limited sampling rate and resolution, there exist a best set of filter coefficients under some criterion. Our recent analytical work on this optimization will be reported separately. Intensive work has been done on channel sounding and estimation, and many proposed methods can be considered. Also, automatic gain control (AGC) and threshold optimization are traditional issues well understood by designers. Therefore, it is meaningful to focus on most advanced issues and not to implement these functions in the current version of the testbed. Instead, we sound the channel using lab instruments, estimate the channel and optimize the coefficients in an off-line manner. The amplification gain and thresholds are set manually.

A symbol waveform can include multiple pulses to reduce peak power while keeping enough symbol energy (in this design a symbol contains one data bit). Scrambling coding is necessary to remove DC component and reduce the spectral spikes in the modulated signal. In typical indoor environments, delay spread is in the order of tens of nanoseconds, and interpulse-interference (IPI) is inevitable as the pulse repetition rate reaches the level of tens of MHz. A waveform generator is placed at the transmitter to focus the received signal in time and reduce the ISI impact. OOK and 2-PPM are two modulation schemes that are suitable for non-coherent detection. For higher data rates, a 2-PPM symbol duration has to be double of an OOK symbol duration to avoid IPI. Finding a proper threshold for OOK demodulation at unknow level of background noise is challenging, but threshold selection is not necessary for the 2-PPM scheme if using differential energy detection. Time reversal waveforms have been used to test the system and verify the performance. In a time reversal system, the transmit chip waveform is the time-reversed version of the CIR, which is environment dependent [3][5]. The waveform generator in the transmitter has to be programmable to match the instant CIR. Studies have shown that the received signal concentrates a large percentage of the total energy in a short period of time, enabling the use of some simple receiver that have little toleration to IPI and ISI [4][6][7]. D. Energy Collection Signal energy at the detector’s output is accumulated by integration. The integration window size is a key parameter that affects performance. A smart way is to weight the incoming baseband signal before integration at the cost of increased complexity [13][14][15]. Instead of using fancy integrators, we rely on the waveform generator at the transmitter to focus signal energy and set the integration window size to a fixed value that is much smaller than a typical delay spread in an NLOS environment. The integration window size used in this testbed is 16.25 ns. E. Frame Structure After calibration phase data can be transmitted. For simplicity, burst mode communication is considered in this design. In each burst, a fixed-length frame is transmitted without any handshaking between the transmitter and the receiver. The frame starts with a synchronization header followed by a packet of payload data. Tracking is not necessary if the frame length is relatively shorter than the coherent time, but fast initial timing acquisition is highly desired for efficient transmission. Illustrated in Figure 2 is a typical frame structure used in the testbed. The chip duration is 40 ns and each bit is represented by four chips. With this specific frame arrangement the packet size in time is 163.84 μs and the raw data throughput is 93.75%.

32 chips of “0”

Guard interval

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source

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board_clk 128 chips of “1”

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Fig. 2.

control bits

Frame structure.

F. Synchronization Synchronization is achieved based on received baseband signal. A 3-stage synchronization method has been designed and that is of lower complexity than traditional direct correlation based methods. Here are functions of the three stages: stage 1 for signal-arrival detection (or coarse synchronization), stage 2 for chip synchronization, and stage 3 for frame synchronization. The main advantages of this 3-stage approach include: (1) the stage 1 provides coarse timing quickly and reduces search space; and (2) hard decision is made after stage 2, so that the stage 3 deals with mono-bit sequence, resulting in less computation and lower complexity. To shorted the overall synchronization time further, parallel chip level processing is employed at the cost of more FPGA resources occupation. Using the frame structure shown in Figure 2, the synchronization takes about 10 μs. Note that the simple detector poses additional challenge to synchronization: what is the best decision threshold? what is the optimal frame synchronization code in such a non-Gaussian noise case? and how to optimally design each stage to achieve the best overall synchronization performance? TABLE I. A Link Budget Example. Bit rate 6.25 Mb/s Minimum required SNR per bit Eb /N0,min = 16 dB Center frequency 4 GHz Transmitter antenna gain 3.5 dBi Receiver antenna gain 3.5 dBi Distance between the two antennas 15 meters Receiver noise figure 6 dB Implementation loss 4 dB Transmitted power (input to antenna) -16.45 dBm (0.0227 mW) Bandwidth (approximately) 800 MHz EIRP spectral density -41.98 dBm/MHz Path loss at 1 m 44.48 dB Path loss at 3 m 54.03 dB Total path loss 68.00 dB Received power -77.45 dBm Link margin 2.59 dB Proposed minimal receiver sensitivity -80.04 dBm

G. Link Budget Estimation The link budget estimation shown in Table I is based on the following two conditions: 1) free space propagation and 2) OOK modulation with equi-probable “1” and “0” bit transmission. The transmitted power used here is estimated considering the actual components used in the transmitter. Spectrum measurement shows that the estimated transmitted power spectral density (PSD) is closed to the measured result.

Fig. 3. The functional diagram of transmitter baseband/control subsystem.

The actual transmission range depends on the jpropagation environment. Path loss is much larger in a no-direct-path environment and the large delay spread would introduce ISI. Extra path loss and/or ISI can shortens transmission range significantly. III. I MPLEMENTATION A SPECTS Module-based implementation methodology is adopted to expedite the overall development. Major parts in the testbed include Xilinx Virtex series FPGAs, a programmable DAC, an ADC, and RF frnt-ends. The waveform generator, a key element in the testbed, is a combination of a programmable FIR filter and the DAC , where the FIR filter is embedded in the FPGA. A. Baseband and System Control The baseband and system control functions are implemented using Xilinx Virtex series FPGAs. The functional diagrams of the baseband/control subsystems are shown in Figure 3 and Figure 4. The transmitter baseband subsystem can be divided into two modules: a baseline transmitter module and an FIR filter module with coefficient loading function. The baseline transmitter performs regular transmitter baseband functions: data interface, modulation, spreading and scrambling. The output of the baseline transmitter module is a chip level digital stream at chip rate 25 Mcps. This chip stream is then fed into the FIR filter. In the receiver baseband/control subsystem there are three working states defined as follows. • State 00: idle state, the receiver monitors if a frame has arrived; • State 01: fine synchronization state, the receiver acquires chip timing and frame timing; • State 10: data transmission state, the receiver demodulates the received data. The state transition diagram is given in Figure 5, and these state transitions are executed by the finite state machine (FSM) implemented in the receiver-side FPGA. All system control tasks are taken cared of by the FPGAs. Configuring some devices such as DAC and local oscillator (LO) is part of system control. The serial peripheral interface (SPI) bus is a simple and flexible interface standard that allows one master device to communicate with one or multiple slave devices, and it can support data rates up to tens of Mbps. In

Begin

ADC data ADC clock

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state(1:0)

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data_out

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Configure DAC

Fig. 4.

The functional diagram of receiver baseband/control subsys-

tem. Fig. 6.

System control flow chart for the transmitter.

State 10 Data Trans. Quadture 400 MHz - 4 GHz.

Data Transmission Completion

Symbol Synchronization

PA

Antenna 3.1-10 GHZ 3.5dBi gain at 4.0 GHz

Modulator 2 - 8GHz 35dB gain

State 00 Idle

Fig. 5.

Signal arrival Synchronization failure

State 01 Fine Sync.

State transition diagram.

the transmitter, the LO is connected to the FPGA via an SPI bus with the FPGA serving as the SPI master and the LO as the SPI slave. The system control flow chart in the transmitter side is presented in Figure 6. B. Mixed Signal Devices and Their Interfaces On the market there are not many DAC and ADC products supporting Gsps sampling rates. Top concerns in selecting them include multiplexing or demultiplexing features, reconfigurability and dual-channel. Although the high speed digital interface standard, low voltage differential signal (LVDS), has been used in the transmitter, the connection between the FPGA and the DAC is actually a bottleneck that limits the speed. It has been found that if a connecting path consists of PCB traces, connectors and cables, reaching a sampling rate beyond 500 Msps becomes extremely difficult. For the design of the high-speed interface between ADC (or DAC) and FPGA, signal integrity has become a critical issue. Many signal integrity problems are electromagnetic phenomena in nature. There are two concerns for signal integrity: the timing and the quality of the signals. Signal timing mainly depends on the delay caused by the physical

Local Oscillator

Fig. 7.

4.0 GHz Center Freq SPI control

The diagram of transmitter RF front-ends.

length and the material of each segment along the connecting path. Signal waveform distortions can be caused by reflection due to impedance mismatching, cross talk, and power/ground noise. An ADC-FPGA interface with double-end termination has been carefully designed to support a sampling rate of 800 Msps in the receiver. C. RF Front-Ends We mainly rely on off-the-shelf products for RF front-ends in the transmitter. Major components and modules include local oscillator (LO), modulator, amplifiers and antennas. The RF front-ends in the transmitter are illustrated in Figure 7. At the receiver, a diode-based detector is employed, making the receiver RF front-end relatively simple. The received RF signal first goes through the bandpass filter, and then is processed by the detector. Finally the baseband signal from the detector is sampled by the ADC at 800 Msps. Reconfigurability and wide frequency range are preferred for the LO. Z-comm and other manufacturers offer such LOs. A quadrature type of modulator (or up-converter) is needed to handle complex signals. Baseband bandwidth and input LO frequency range of a modulator are particularly important to

shift registers: a_0 ~ a_39

a_9

a_19

a_29

LUT Port A data

Fig. 8.

shift registers: b_0 ~ b_39

a_39

b_9 input chip vector scrambling code vector

b_19

b_29

b_39

input chips scrambling code

Port B data

The implementation of the FIR filter in Virtex-5 FPGA.

UWB signal generation. The power amplifier has to be of wide bandwidth and there are many choices. A variable attenuator may be used with the power amplifier in order not to break the FCC emission power ruling. For the frequency band of interest, there have been some UWB antenna products on the market and many proposed designs. Generally speaking, a small-size omni-directional antenna with voltage standing wave ratio (VSWR) ≤ 2 is a reasonable choice. Typically these antennas have a few dBi gain at 4 GHz. One common issue in RF implementation is carrier leakage rejection. Although the modulator has very good carrier isolation (say, -37 dBm), there are some other paths that the carrier can pass to the output port. Also, unbalanced bias between the two differential input ends of a modulator contributes carrier leakage. Conventional RF decoupling techniques can reduce carrier leakage. In addition, a narrow band notch filer at the carrier frequency may be employed to suppress the output carrier leakage. D. Waveform Generator Design with Practical Considerations As mentioned above, the waveform generator is a combination of the programmable FIR filter and the DAC. Figure 8 shows the implementation of the FIR filter in Virtex-5 FPGA. This design takes advantage of sparseness of the chip stream and uses a look-up table (LUT) to realize multiplication. The structure shown here has a pair of filters corresponding to the two cores in the DAC. The coefficients are stored in two separate shift registers. Although the implementation of the FIR filter is architecturally fixed, different waveform templates can be downloaded into the shift registers, which provides the waveform generator with programmability. The ultimate goal regarding the waveform generator is to generate arbitrary analog waveforms, such as time reversed CIR, chirp signal, optimal waveforms in some criteria, and so on. However, sampling rate, digital resolution (number of bits) and all kinds of hardware resources are practically limited. These limitations have to be taken into account in designing a feasible waveform generator. The sampling rate limit is determined by the maximum FPGA processing speed, the bandwidth of the connecting path between the FPGA and the DAC, and the maximum sampling rate supported by the DAC. In order to relax sampling rate requirement, the DAC’s multiplexing feature is utilized to combine two data streams in

Fig. 9.

Room 400, layout.

a time interleaving manner, resulting in an output at doubled sampling rate. In this case, the two individual FIR filters have to be configured such that each of the two generates one-half of the whole sequence at one-half of the actual sampling rate. IV. E XPERIMENT AND S YSTEM T EST A. Environment and System Setup The testbed was tested in an NLOS office environment. The office layout and antenna positions are illustrated in Figure 9. As shown the office has three compartments. There are computers, electronic equipment, wood/metal shelves, desks and chairs inside. Two identical omni-directional antennas were used to transmit and receive signals. The transmit antenna was located in compartment A, while the receive antenna was located in compartment B; and, the line-of-sight between them was blocked by a bookshelf. The straight-line distance of these two antennas was 5 m (16.4 ft), and both antennas were mounted at the same height 1.4 m (4.6 ft). Such an environmental setup ensures a multipath channel with large delay spread. At the transmitter side, the time reversal template was prepared from a rectangle-windowed channel transfer function measured using a vector network analyzer (VNA). As shown in Figure 10, the frequency sweeps from 3.5 GHz to 4.5 GHz with 1 MHz resolution, covering the frequency band of the transmitted signal. Denoted by h(t), the passband CIR for the frequency band of interest, the baseband equivalent CIR would be h (t) = h(t)e−jωc t , where ωc is the center frequency. Based on the measurements, the magnitude of the windowed baseband CIR is depicted in Figure 11. The passband CIR is an inverse Fourier transform (IFT) of the windowed (passband) channel transfer function. Finally, the baseband CIR h (t) in the time delay line model can be estimated using a deconvolution algorithm like CLEAN. Here, the mathematical manipulation and technical details about how to obtain h (t) from frequency-domain measurement are omitted.

−65 −70

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−75 −80 −85 −90 −95 −100 −105 3.5

4 Frequency (Hz)

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x 10

Fig. 10. Rectangle-windowed transfer function of the channel, measured by a VNA. Frequency sweeps from 3.5 GHz to 4.5 GHz with 1 MHz resolution.

Fig. 12.

Baseband time reversal waveform with scrambling.

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h (−t) would be an ideal baseband time reversal template, but it cannot be accurately generated due to the practical limitations. What has been tested is a ternary-quantized, realnumber baseband template with sampling rate 500 Msps. This template was optimized under maximum correlation criterion to approximate the original template h (−t). Figure 12 is a piece of baseband signal corresponding to four scrambled chips, captured at the waveform generator’s output by a Tektronix TDS 7104 digital phosphor oscilloscope (DPO). Since the approximated baseband time reversal template contains four 2-ns pulses, each chip is comprised of four 2-ns pulses as well. Figure 13 is the spectrum of the modulated waveform captured at the transmitter by a Rohde & Schwarz FSEM20 Spectrum Analyzer, where the center frequency is 4 GHz and the 10 dB bandwidth is about 800 MHz. At the receiver, side the DPO was used to monitor the detector’s output and the demodulated bit stream. one could tell if the system was running properly simply by observing the demodulated bit stream.

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Fig. 13.

3.2

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Spectrum of time reversal waveform after modulation.

B. Experimental Results In this test, a given pseudo-random (PN) sequence was transmitted periodically at bit rate 6.25 Mbps. Figure 14 shows the system test observations. The top trace is the transmitted baseband waveform, the middle trace is the detector output, and the bottom trace is the demodulated bit stream. It can been seen that the top trace is a zoom-out version of Figure 12. Although there are some interferences observed on both the middle and the bottom trace, distinguishable peaks can be seen on the middle trace and the PN sequence can be read clearly from the bottom trace. A close-up of the middle trace is shown in Figure 15. The top trace is the baseband transmitted waveform, the middle trace is the received waveform at the detector’s output, and the bottom trace is a data clock running at 6.25 MHz, the same as the data rate. Time focusing property can be observed from the middle trace. At the transmitter side, four pulses are transmitted separately in each chip period; while at the receiver side, there is only one strong peak in each chip period, because

Fig. 15. Fig. 14.

Time focusing property of time reversal.

System test result.

four separated pulses arrived at the same time after traveling through different paths and add up constructively. Although the mainlobe is dominant, some sidelobes are noticeable, suggesting that either the waveform generator needs to be refined, or other signal processing techniques should be combined. During this indoor trial, no bit errors were observed for time reversal setting; and, without use of time reversal waveform, the system simply did not work because of severe ISI. V. C ONCLUSIONS This paper reports our recent research and development work in radio testbed aspect. The design considerations have been presented along with the system architecture. The implementation issues have been reported in detail. A UWB time reversal radio in an indoor environment have been successfully demonstrated, and the first-hand experimental results have been shown. Experiences and knowledge have been gained with this radio testbed. In the near future, this current version of the testbed will be further improved in many aspects (higher waveform resolution, variable data rate, larger transmission range, etc.), and more research tasks will be carried out on this platform. It is expected that the proposed techniques can be applied to many areas such as in-vehicle and under-deck communications. The goal of this project is to explore the waveform-based pre-coding. This testbed is evolving to have functions of cognitive radio and secure radio. ACKNOWLEDGMENT This work was supported by the Office of Naval Research through a grant (N00014-07-1-0529), and National Science Foundation through a grant (ECS-0622125). R EFERENCES [1] M. Fink, “Time-reversal of Ultrasonic Fields—Part I: Basic Principles,” IEEE Trans. Ultrason. Ferroelec. Freq. Control, vol. 39, no. 5, pp. 555– 566, 1992.

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