Vector quantized signal dependant Delta-Sigma modulator based ...

IEICE Electronics Express, Vol.6, No.17, 1259–1265

Vector quantized signal dependant Delta-Sigma modulator based high performance three-phase switching converter K. Diwakara) , C. Senthilpari, Ajay Kumar Singh, and Lim Way Soong Faculty of Engineering and Technology, Multimedia University, Jalan Ayer Keroh Lama, 75450, Melaka, Malaysia a) [email protected]

Abstract: The conventional second-order Delta-Sigma modulator (DSM) based switching converter (SC) cannot be used for full range (−1 to +1) of input signal. The DSM becomes unstable when the normalized input signal is about 0.4. The output of the second integrator saturates the operational amplifier which is used as comparator in the single-bit quantizer. The three- phase switching converter, based on DSM with hexagonal quantizer, improves the signal to noise ratio as well as the spectral response without improving the range of the input signal. This paper proposes three-phase signal dependant DSM based switching converter with vector quantizer. The proposed three-phase SC increases the input signal to full scale and maintains its stability. The SNR and spectral response are better than the conventional DSM based three-phase switching converter with hexagonal quantizer. The overall maximum percentage of difference in phase voltages is 0.4%. Keywords: vector quantizer, signal dependant DSM, switching converter, signal to noise ratio Classification: Electron devices, circuits, and systems References [1] R. Schreier and G. C. Temes, Understanding Delta-Sigma Data Converters, IEEE Press, 2005. [2] G. Luckjiff and I. Dobson, “Hexagonal ΣΔ Modulators in Power Electronics,” IEEE Trans. Power Electron., vol. 20, no. 5, pp. 1075–1082, Sept. 2005. [3] G. Luckiff, I. Dobson, and D. Divan, “Hexagonal sigma-delta modulation,” IEEE Trans. Circuits Syst., vol. 50, no. 8, pp. 991–1005, Aug. 2003.

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IEICE 2009

DOI: 10.1587/elex.6.1259 Received July 22, 2009 Accepted August 10, 2009 Published September 10, 2009

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Introduction

Delta-Sigma Modulators (DSMs) are over sampled analog-to digital converters that achieve the performance of high resolution quantizer by using low resolution quantizer and linear filter in a feed back loop. The modulator can trade resolution in time for resolution in amplitude and as well it employs simple and relatively low tolerance analog components. The quantizer output toggles about the input signal so that the average quantizer output is approximately equal to the average of the input. In both communications and power electronics, the aim is to design the DSM such that the input signal is passed through the system with minimal distortion from quantization noise for full range of amplitude and frequency of input signal [1, 2]. In the conventional discrete Delta-Sigma modulator [1], the sampling of input signal and DSM operation is performed by the same clock signal. The second-order DSM has better signal to noise ratio (SNR) compared to firstorder DSM. In general higher order modulators have better SNR but can process only low range of input signal and have less stability. The conventional DSM is used in numerous applications in industrial electronics. One such application in power electronics is conventional DSM based switching converter (SC), which is used to control the speed of DC motor [2]. The range of input signal of the switching converter with conventional DSM, reduces as the over sampling ratio (OSR) increases, due to poor SNR and unstable condition. Conventional DSM with hexagonal quantization results in significant improvement in spectral performance, SNR and is used to control three-phase dc motor with three-phase switching converter [2, 3]. But the range of input signal cannot be extended to full scale. This paper proposes a three-phase SC based on second order DSM with input signal dependant operating period and vector quantizer. The SC is stable for full range of analog input signal. The upper bounds on the integrator outputs never increase abruptly. The SNR and spectral response are better than the conventional DSM based three-phase SC with hexagonal quantizer [2, 3].

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IEICE 2009

DOI: 10.1587/elex.6.1259 Received July 22, 2009 Accepted August 10, 2009 Published September 10, 2009

Block diagram of proposed three-phase SC

2.1 Proposed vector quantizer In scalar single-bit quantizer, the quantizer input xq is quantized to +1 when xq is any positive value or zero. The quantizer input is quantized to −1 when xq is negative. The idea of scalar quantization is extended to vector quantization. The proposed vector quantizer is shown in Fig. 1 (a) The circle of radius (xq )max is divided into six equal sectors. The vector falling in any sector is represented by the representative vector in each sector. Each representative vector bisects the corresponding sector and its magnitude is 1. The three-phase switching circuit is shown in Fig. 1 (b). The switching circuit has six switching states corresponding to the six output vectors in Fig. 1 (a). The output of the switching circuit (a,b,c) drives the balanced

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Fig. 1. (a)- Proposed vector quantizer.

Fig. 1. (b)- Three-phase switching circuit.

three-phase load like three-phase dc motor. In the conventional DSM based single-phase or three-phase SC the sampling of input signal and DSM operation is performed by the same clock signal [2, 3]. Figure. 2 (a) shows conventional DSM based single-phase SC in which Q1 and Q2 are acting as switches. The block diagram of the proposed, three-phase signal dependant DSM based SC with vector quantizer is shown in Fig. 2 (b).

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IEICE 2009

DOI: 10.1587/elex.6.1259 Received July 22, 2009 Accepted August 10, 2009 Published September 10, 2009

In the proposed three-phase SC, the sampling of input signal and DSM operation is performed by different clock signals. The DSM circuit is operated by clock with period TC . The Sample and Hold (S/H) circuit samples the

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input signal, y at a sampling period TU (update period). TU and TC are selected such that TU  TC . The time at which the states of different blocks are updated, is labeled on each block or on set of blocks (shown by thick dotted lines) in Fig. 2 (a) and in Fig. 2 (b). The input x, of the secondorder DSM is a constant dc signal (x = 1). The magnitude |y| of the analog input signal y is used to control the operating period of DSM. All modulator signals are augmented from scalar quantities to vectors and so all components process the vector signals. The average values of outputs of first integrator, second integrator, and quantizer during ith update period are denoted as x1 , x2 and z respectively. The output of single-bit quantizer is +1 or −1 or 0 when DSM is functioning. During a positive transition of update signal, the SR flip-flop is set. When SR flip-flop is set (phase Φon ), the switches s1 to s7 are closed (shown by thin dotted lines) and DSM starts functioning. The DSM output consists of a sequence of pulses of magnitude +1, −1 and 0. The resolution of DSM output, Δz is given by, Δz =

TC |ymax | TU

(1)

The resolution, Δz is integrated when SR flip-flop is set. The integral value of Δz, (Δz)cum is compared with |y|. When (Δz)cum > |y|, the SR flip-flop is reset (phase Φoff ). The switches s1 to s7 are opened, the DSM stops functioning and output is zero for the remaining sampling period since the quantizer output is clamped to analog ground through a switch. All the integrators, denoted as I1 , I2 , and I3 are reset to zero and cumulative addition of Δz also stops. The resolution Δzis selected such that in any sampling period (Δz)cum is less than |ymax |. When y is negative, quantizer output is inverted (not shown in figure) to get correct sign for the output. During next positive transition of update cycle, the DSM operating cycle is repeated. There are six outputs from the vector quantizer and the values of outputs depend on which sector the quantizer input falls. The average value of bit stream at the output a,b,c of 3Φ switching circuit, during each sampling period, is proportional to the sampled value of the input signal y. Each output lead by 120◦ in the phase sequence a-b-c. Therefore, the speed of three-phase dc motor will be proportional to the amplitude of analog input signal y, in both directions. The amplitude of analog input signal (y) controls only the operating period of DSM and hence the state variables and stability do not depend upon the amplitude of y. The normalized value of y can range from −1 to +1 (full scale range). As far as the DSM is concerned the input is a constant dc signal (x = 1). Therefore, the maximum bounds on the state variables are constant for complete range of y and the SNR never falls for higher range of y.

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IEICE 2009

DOI: 10.1587/elex.6.1259 Received July 22, 2009 Accepted August 10, 2009 Published September 10, 2009

2.2 Relation between inputs and output in each phase For each update period TU , which is a constant, the DSM circuit operating time, TO is in the range 0 ≤ TO < TU where TO is a variable and

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is proportional to |y|. The average value of output signal in phase-a, during TO (za ) within each sampling period is proportional to normalized input (1/n). Therefore, N p TC k (2) za = = n TO where NP is the net number of pulses (number of positive pulses – number of negative pulses) at the output of phase-a, k is constant of proportionality and n is the feedback gain. The operating period of DSM circuit is proportional to |y|. Therefore, (3) TO = TU |y| The average value of DSM output in phase-a during TU (za ) is given by, za =

N p TC TU

(4)

Using equations (2), (3) and (4), za can be written as, za =

k |y| n

(5)

When y is negative, the quantizer output is inverted. Therefore za can be written as, k (6) za = y n

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IEICE 2009

DOI: 10.1587/elex.6.1259 Received July 22, 2009 Accepted August 10, 2009 Published September 10, 2009

Simulation

The MATLAB/Simulink software is used to simulate the proposed DSM with n = 1.1, fU = 2.048 kHz and fC = 10 MHz. The sampled analog input signal of peak amplitude 1 V and frequency 13 Hz. is used for the simulation. Fig. 3 (a) shows three-phase (a-b-c) output of the quantizer. The outputs lead by 120◦ in the phase sequence a-b-c. The overall maximum percentage of difference in phase voltages is 0.4%. Comparison of SNR of Ref. [2] and proposed SC (phase-a) with variation of input amplitude of sinusoidal signal is shown at the top of Fig. 3 (b). The SNR curve of proposed SC can be explained using noise shaping behavior of DSM for dc signal (DSM input is unity dc signal). The increased attenuation of noise transfer function for dc signal reduces the quantization noise in the signal band. Therefore, if the DSM is operated with dc input and low clock period for sufficient time (update period) the average value of the digital output will be good approximation of dc input signal. The merit of operating on dc signal dominates from −50 dB to −13 dB of input signal and so SNR of proposed SC is better than that reported in Ref. [2] in this range. In the proposed circuit, the operating time of DSM is proportional to the amplitude of sampled analog input signal. When the magnitude of sampled analog input signal decreases the DSM circuit operates for shorter time and so the quantization noise level increases and SNR decreases. The effect of controlling the operating time of DSM, proportional to sampled analog input signal, dominates from −13 dB to −2 dB of input signal and so the SNR of proposed SC is lesser than Ref. [2] in the range. As the input increases from −2 dB 1263

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(0.63) to 0 dB (1), the SNR of Ref. [2] falls down because the second integrator output increases rapidly which overload the quantizer. In the proposed SC for input ranging from 0.63 to 1 (37% of full scale), the SNR never falls down but slowly increases and reaches 64.3 dB when the input is 1. The PSD of output signal of proposed DSM is shown at the bottom of Fig. 3 (b) and from which the noise shaping characteristics of the proposed DSM is clear. The signal level is 20 dB and near the vicinity of signal frequency the noise level is −30 dB. Figure 3 (c) shows the variation of noise signal (y-z) with time and the overall absolute maximum value is 1 mV (0.1% or −30 dB).

Fig. 3. (a)- Three- phase voltages of the Proposed threephase SC. (x-axis: Time in sec.; y-axis: Voltage in volts for (a), (c), (e) and radians for (b), (d), (f))

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Fig. 3. (b)- Comparison of SNR (OSR=32) and PSD (y=1) of proposed three-phase SC.

IEICE 2009

DOI: 10.1587/elex.6.1259 Received July 22, 2009 Accepted August 10, 2009 Published September 10, 2009

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Fig. 3. (c)- Variation of noise signal of proposed threephase SC. (x-axis: Time in sec.; y-axis: Voltage in volts)

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Conclusion

In the proposed three-phase SC, the maximum bounds on the state variables are constant for complete range of input signal. The state variables never become arbitrarily large to make the system unstable. The normalized input signal can range from −1 to +1. The SNR does not fall for higher range of input signals. The overall maximum percentage of difference in phase voltages is 0.4%. In the output spectrum near the signal frequency the noise level is well below the signal level. Hence, the proposed three-phase SC is well suited for applications in power electronics.

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IEICE 2009

DOI: 10.1587/elex.6.1259 Received July 22, 2009 Accepted August 10, 2009 Published September 10, 2009

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