VHDL : case study

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P. Bakowski. 3. General specifications. The general structure of the frequency meter has three inputs: clk_cap signal that carries the measured frequency ...
VHDL : case study Frequency Meter P. Bakowski

[email protected]

General specifications The general structure of the frequency meter has three inputs:

P. Bakowski

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General specifications The general structure of the frequency meter has three inputs: clk_cap signal that carries the measured frequency

P. Bakowski

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General specifications The general structure of the frequency meter has three inputs: clk_cap signal that carries the measured frequency clk_seq signal that imposes the operational sequence of the meter

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General specifications The general structure of the frequency meter has three inputs: clk_cap signal that carries the measured frequency and clk_seq signal that imposes the operational sequence of the meter go signal that activates the sequencer

active P. Bakowski

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General specifications The general structure of the frequency meter has three inputs: clk_cap signal that carries the measured frequency and clk_seq signal that imposes the operational sequence of the meter go signal An two output signals to two 7-segment displays driven by the output decoder of the frequency meter.

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General specifications units

go ua_g clk_seq

a g b

f e d c

a g b

clk_cap da_g

f e d c tens

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General specifications units

go ua_g clk_seq

sequencer

a g b

f e d c

a g b

clk_cap da_g

f e d c tens

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General specifications units

go ua_g clk_seq

sequencer count

clk_cap

a g b

f e d c

a g b

counter da_g

f e d c tens

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General specifications units

clk_seq

sequencer count

clk_cap

counter

disp

display latch

go

a g b

ua_g

f e d c

a g b

da_g

f e d c tens

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go

Sequencer clk_seq library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all;

sequencer

disp

count

entity sequencer is port(clk_seq,go: in std_logic; count,disp: out std_logic; end sequencer;

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Sequencer – abstract states architecture fsm of sequencer is begin process(clk_seq) type tetat is (stop,ecount,edisp); variable vetat: tetat:= stop; begin case vetat is when stop => count