vhdl implementation of test access port controller

Manpreet Kaur et al. / International Journal of Engineering Science and Technology (IJEST)

VHDL IMPLEMENTATION OF TEST ACCESS PORT CONTROLLER MANPREET KAUR Academics and consultancy and services division Center for development of advanced computing (C-DAC) Mohali, India Mobile no. +91-8146997247 e-mail: [email protected]

BALWINDER SINGH Academics and consultancy and services division Center for development of advanced computing Mohali, India Mobile no. +91-9888000646 e-mail: [email protected]. Abstract : In this paper, an implementation of IEEE 1149.7 standard is used for designing Test Access Port (TAP) Controller and testing of interconnects is done using boundary scan. By c-JTAG the pin count gets reduced which increases the performance and simplifies the connection between devices. TAP Controller is a synchronous Moore type finite state machine that is changed when the TMS and TCK signals of the test access port gets change. This controls the sequence operation of the circuitry conveyed by JTAG and c-JTAG. JTAG mainly used four pins with TAP and fifth pin is for optional use in Boundary scan. But c-JTAG uses only two pins with TAP. In this approach TDI and TDO gets multiplexed by using class T4 and T5 of c-JTAG. Various instructions are used for testing interconnects using IEEE 1149.7 standard (std). Keywords: VHDL, FSM, IEEE 1149.1(JTAG) std, IEEE 1149.7(c-JTAG) std, BSDL. 1.

INTRODUCTION

In the 1980s, the Joint Test Action Group (JTAG) was formed to grow the test access to chips on boards due to the adaption of surface-mount assembly. In 1990, they released the IEEE Standard 1149.1 as Standard Test Access Port and Boundary-Scan Architecture. IEEE 1149.1 standard is needed to solve the problems of board test, as specified by the provision for boundary scan. The standard realized is needed for accessing the components on boards and in systems that would suit a wide range of uses. The IEEE 1149.1 TAP (Test Access Port) controller is one of the widely used circuits in commercial IC chips. And it is used as the foundation of IEEE 1149.7 TAP i.e. also known as c-JTAG (compact-JTAG). 1.1. IEEE 1149.7 Standard IEEE 1149.7 is a standard for a test access port and boundary scan architecture offers reduced pins and enhanced functionality [11]. Whereas the conventional 1149.1 TAP (TAP.1) requires at least four signals with a fifth signal, for test reset that is optional, the reduced-pin 1149.7 TAP (TAP.7) requires only two signals with the possibility for encoding the optional test reset function. Further, with the functionality enhancement, it is expected that, in many cases, extended signaling is used as applications debug on no more than two pins. Even while delivering these benefits, 1149.7 have taken main attention to preserve the investment that the industry has made in 1149.1 for chips and on boards. Particularly, 1149.7 adapt the architecture of the 1149.1 boundaryscan architecture to fully support board test and in-system configuration [7]. Further, 1149.7 do not replace 1149.1, but rather adapts it and extends it. 1149.1 chips can be adapted easily to provide a TAP.7 as shown in figure 1. TAP.7 can coexist with TAP.1s on boards and even on the same board-level TAP connections.

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c-JTAG

TCK

TMS

1149.1 IC

TCK

1149.7 IC

1149.1 IC

TDI TMS

TDO

Basic 1149.1 IC with four signals

Modified 1149.7 IC with two signals

Figure1: Adaption of 1149.1 to 1149.7

1.2. Challenges: One unique feature of 1149.7 is the reduced pin count interface for the test access port (TAP) interface; it uses a two-wire interface, as compare to the 1149.1 four or five-wire TAP interface. Recent years have seen an implementation of multi-core system on chip (SOC), system in package (SIP) and package on package (POP) devices [7]. All these technologies pose new challenges when it comes to manufacturing test due to limited test points and higher speed. This is causing existing manufacturing test systems to lose test coverage, even with the implementation of IEEE 1149.1. 1.3. IEEE 1149.7 Key Objectives The key objectives for IEEE 1149.7 standard are divided into three categories: system architecture, applications debug, and infrastructure. They are described follows:  System architecture derive from the appropriate accommodation of multiple-on-chip embedded TAP Controllers (EMTAPC), the reduction of pins, adaption of star topology, independence from debug technology, and for power management. Where intellectual property (IP) blocks may each contain EMTAPCs, multiples of these may be accommodated on a complex system-on-chip (SOC). While reduced pin count has inherent value with respect to miniaturization, as well as in combination with the star topology, fewer pins better supports system-in-package (SIP).  For applications debug, the TAP.7 provides advanced capability that reduces or eliminates the signalling by using the two wires. Extensions provided include connections, increased throughput by scan optimization, higher operating frequency, and transport of BDX and/ or CDX.  Finally, the infrastructure, has two further objectives; firstly, honour 1149.1 by preserving the test infrastructure that has been built up around it and on which the industry depends; and secondly, maintain a level of compliance such that existing intellectual property in chips, on boards, and in debug and test systems (DTS) can be adapted at low cost. 2. IEEE 1149.7 Architecture IEEE 1149.7 Architecture includes three capabilities shown in figure 2, they are named as, complaint capability, extended capability and advance capability. Behaviour of these capabilities is follows:  Behaviour of complaint capability is IEEE 1149.1 compliance with multiple test access ports within the system test logic.  Behaviour of extended capability is TAP.7 controller commands and infrastructure.  Behaviour of advanced capability is serialization of two pin operation. Within this specification, the system test logic refers to chip test logic. A chip functional logic is not included in the STL (system test logic). It provides an IEEE 1149.1 interface for the T0 TAP.7. The RSU is a reset unit that provides reset operation and TAP.7 Controller selection services. The EPU is a extended protocol unit that provides an IEEE 1149.1 interface for the T1–T3 classes. The APU is a advanced protocol unit that provides in T4–T5 classes TAP.7 interface that is either narrow or wide, with the wide interface provides an IEEE 1149.1 interface. The scan paths associated with the TAP.7 architecture reference

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using the entity in which they reside, for example a TAP.7 Controller Scan Path, an STL Scan Path, etc. With this architecture, the Test Reset signal is optional with all Classes. These signals should be connected separately to the debug and system unless they are continuously driven by a driver within the system.

Advanced Capability

Complaint Capability

Extended Capability

TCKC,TMSC

RSU

APU

EPU

STL

TCKC,TMSC TDIC,TDOC TCK,TMS, TDIC,TDOC

RSU

EPU

EPU

TCK,TMS, TDIC,TDOC

RSU

STL

STL

TCK,TMS, TDI,TDO

RSU

STL

TAP.7 Controller

System Test Logic

Figure 2: IEEE 1149.7 Architecture

2.1. Capabilities of Classes Capability class is implemented; a given TAP.7 must implement all of the mandatory features of its own class (T0 to T5). The classes are generally considered in two groups: class T0-T3 consider in extended 4-pin operation and class T4-T5 consider in advanced 2-pin operation.  Class T0 maintains compliance to 1149.1 while also providing support for multiple TAPs on a single chip.  Class T1 adds support for the 1149.7 command, test resets, and power control.  Class T2 adds the capability to bypass a chip’s system test logic, resulting in a 1-bit path for Instruction Register (IR) and Data Register (DR) scans.  Class T3 adds support for connecting TAP.7 controllers in a 4-wire star topology.  Class T4 adds support for advanced scans and 2-pin operation (all signalling done using only TMS and TCK pins), which means TDO and TDI can be removed or used for other functions.  Class T5 considers, support for up to two data channels for non-scan data transfers, which can be used for application specific debug and instrumentation purposes. 3.

Proposed TAP Controller

TAP Controller has important role in all IC chips that are complaint with 1149.1 boundary scan standard and it is complaints with 1149.7 boundary scan standard. Although the main purpose of boundary scan is testing of IC chips. Figure 3 shows the TMS and TCK (and the optional TRST) go to a 16-state finite-state machine controller, which produces the various control signals. These signals include dedicated signals to the Instruction register (Clock-IR, Shift-IR, and Update-IR) and generic signals to all data registers (Clock-DR, Shift-DR, Update-DR). The data register that actually responds is the one enabled by the conditional control signals generated at the parallel outputs of the Instruction register, according to the particular instruction. The other signals, Reset, Select and Enable are distributed as follows:  Reset is distributed to the Instruction register and to the Data Register.  Select is distributed to the output multiplexer.  Enable is distributed to the output driver.

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TMS

TCK

Clock 16 states FSM of TAP Controller (Moore Machine)

Shift Update Reset Select Clock Shift

TRST

Update Enable Figure 3: FSM Block of TAP

3.1. TAP Controller State Diagram Figure 4 shows the 16-state FSM for TAP controller. The value on the state transition arcs is the value of TMS. A state transition occurs on the positive edge of TCK and the controller output values change on the negative edge of TCK. The TAP controller initializes the Test-Logic-Reset state. While TMS remains a 1, the state remains unchanged. In the Test-Logic-Reset state and the active register is determined by the contents of the Instruction register. The selected register is either the Identification register, if present, else the Bypass registers. Pulling TMS low causes a transition to the Run-Test/Idle state. Test logic reset

Run Test / Idle

Select DR

Capture DR

Shift DR

Select IR

Capture IR

Shift IR

Exit 1 DR

Exit 1 IR

Pause DR

Pause IR

Exit 2 DR

Exit 2 IR

Update DR

Update IR

Figure 4: TAP Controller state diagram

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Normally, want to move to the Select IR-Scan state ready to load and execute a new instruction. An additional 11 sequence on TMS will achieve this. From here, we can move through the various Capture-IR, Shift-IR, and Update-IR states as required. The last operation is the Update-IR operation and the instruction loaded into the shift section of the Instruction register is transferred to the Instruction register to become the new current instruction. This causes the Instruction register to be deselected as the register connected between TDI and TDO and the Data register identified by the new current instruction to be selected as the Data register between TDI and TDO. For example Bypass instruction used, the Bypass register becomes the selected data register. From now one, can manipulate the data register with the generic signals; Capture-DR, Shift-DR, and UpdateDR control signals. 3.2. Boundary Scan Testing Boundary Scan Testing (BST) is the method of controlling and observing the boundary scan pins of the JTAG compliant device. BST can be used to test connectivity between devices by scan chaining. Several scan chains can exist on a PCB to form multiple scan chains that can be possible with the class of 1149.7 standard. An advantage of BST is that, it can be implemented without physical test probes; all that is needed is a 2-wire interface using 1149.7 standard and an appropriate test platform. The main drawback to BST is that it can only evaluate digital signals; it cannot measure input or output voltage levels or currents. Instructions used for interconnect testing are EXTEST, BYPASS, SAMPLE and PRELOAD, INTEST; they are following described: 3.2.1. EXTEST Instruction Boundary scan’s EXTEST mode is used to test the structural faults like shorts and opens in device interconnects; and stuck-at pin faults shown in figure 5. If boards were composed entirely of boundary scan parts, testing using the EXTEST mode would provide a complete pin-level structural check, with fault coverage. The EXTEST instruction select the boundary scan register when executed to interconnect testing. The code for EXTEST used to be defined to be the all-0s code according to the standard used.

IC1

1

0

0

1

0

0

1

0

Short wire

IC2

Open wire

Figure 5: Interconnects between two ICs

EXTEST puts the device in test mode that is, the boundary scan cells on the input side of the device have permission to write logic values into the device, and the boundary-scan cells on the output side of the device have permission to write logic values onto the output pins of the device. This means that there should be no risk of the device being placed into its boundary scan test mode of operation by means of the accidental loading and execution of the EXTEST instruction. If this happened, either this device or other devices connected to this device might be placed into a state. A stuck-at-0 short to Ground on a TDI input pin could load an all-0s code into the Instruction register causing the device to be placed in a mode when executed. 3.2.2. BYPASS Instruction The Bypass instruction must be assigned an all-1s code and when executed, causes the Bypass register to be placed between the TDI and TDO pins. By definition, the initialized state of the Instruction register should contain the code for the Bypass instruction unless the optional Identification register has been implemented, in which case, the code for the IDCODE instruction should be present in the instruction register. 3.2.3. SAMPLE and PRELOAD Instruction The Sample and Preload instruction, selects the Boundary-Scan register when executed. The instruction sets up the boundary-scan cells either to sample (capture) values or to preload known values into the boundary-scan

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cells prior to some following operation. The codes for the Sample and Preload instructions are not defined. The codes may either be the same or they may be different. Both instructions leave the device in functional mode, not test mode. This means that any values preloaded or sampled into the boundary scan cells are not passed through into the device or to the device output pins, unlike EXTEST. Thus the device is still under the control of the functional mode signals. This is an important role between Preload and Sample, compared to EXTEST. 3.2.4. INTEST Instruction The IEEE 1149.1 Standard defines a number of optional instructions, INTEST instruction is one of them i.e. instructions that do not need to be implemented but which have a defined operation if they are implemented. INTEST instruction that selects the boundary-scan register to test the internal interfaces between the devices. 3.3. Test Language A set of description files that are required to support test applications, 1149.1 introduced the Boundary-Scan Description Language (BSDL), after referred to as BSDL.1. Likewise, 1149.7 recognize the need for additional description elements and so have offered its own BSDL.7 derivatives. As for BSDL.1, the BSDL.7 model of a component is effectively an electronic data sheet for parameters of the test logic that may vary from one component to another. As 1149.7 have added some new parameters that may vary from chip to chip, these need to be accommodated in the BSDL.7. Otherwise BSDL.7 derives entirely from the BSDL.1. COMPONENT_CONFORMANCE_ADAPTER COMPONENT_CONFORMANCE_STL TAP_CLASS TAP_SCAN_CLOCK_COMPACT TAP_SCAN_MODE_COMPACT TAP_SCAN_IN_COMPACT TAP_SCAN_OUT_COMPACT TAP_SCAN_RESET 4.

Simulation Results

The design is implemented using Moore state machine and simulated using Xilinx simulator. Synthesis Report of all blocks of IEEE standard shown in Table 1. Table 1: Synthesis Report of Blocks of IEEE standard

Utilized Blocks of IEEE standard No. of slices

No. of FlipFlops

No. of four input LUTs

No. of bonded IOBs

No. of GCLKs

163

252

266

16

2

Instruction Register

11

17

20

27

2

Data Register

31

42

20

23

3

EMTAPC

18

30

40

14

2

Bit scan Detection

22

15

30

24

1

Available

3784

7168

173

8

Blocks TAP Controller

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4.1. Proposed TAP Controller TAP Controller is implemented using Moore FSM. IEEE 1149.7 known as compact-JTAG (c-JTAG) offers more functionality using fewer pins, while maintaining full compatibility with IEEE 1149.1 (JTAG) boundary scan to provide an enhanced test and debug standard. TAP Controller FSM has nine outputs they are named as: Reset, Select, Enable, Clock IR, Shift IR, Update IR, Clock DR Shift DR, Update DR. Classes used from T0 to T5 with the scan formats according to the classes. Top view of TAP Controller is shown in figure 6 and Simulation Result of TAP Controller is shown in figure 7.

Figure 6: Top View of TAP Controller

Figure 7: Simulation Result of TAP Controller

4.2. Instruction Register The instruction register contains at least two bits because boundary scan employs two data registers: the bypass and boundary scan registers. If the data register is chosen, the instruction register must select which of the data registers will be used for the boundary scan. Simulation Result of Instruction Register is shown in figure 8.

Figure 8: Simulation Result of Instruction Register

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4.3. Data Register The data register, which consists of at-least a bypass register and boundary scan register that determines how the test data will be input into a device and how to report the outcome of the test. Add a multiplexer controlled by the TAP finite state machine to choose either the internal register or the regular boundary scan register. The result bit stream is then sent to the TDO output. Simulation Result of Data Register is shown in figure 9.

Figure 9: Simulation Result of Data Register

4.4. EMTAPC Isolate, Exclude and Normal State 1149.7 classes T0-T1 are using here for Isolate, Exclude and Normal mode for EMTAPC. Simulation Result of EMTAPC is shown in figure 10.

Figure 10: Simulation Result of EMTAPC

4.5. Bit Scan Detection of Fault using scan format Bit Scan detection is used for the fault detection, whether the stuck-at-0 or stuck-at-1 using scan formats of 1149.7 standard. Simulation Result of Bit Scan Detection of Fault using scan format is shown in figure 11.

Figure 11: Simulation Result of Bit Scan Detection of Fault using scan format

5. Conclusion IEEE 1149.7 considers a test and debug interface that is a superset of the IEEE 1149.1 (JTAG) TAP. IEEE 1149.7(c-JTAG) is used for reducing pin count and for enhanced functionality, 1149.7 offers an access mechanism that is well suited to interfacing multiple cores on SOC or to interface multiple die in SIP or multiple packages. Because of the enhanced functionality and the reduced pin capability maintain compatibility, designing and testing of boards, ICs etc. are very easy to implement and optimize. With c-JTAG, effort of testing and designing the TAP controller is reduced as compared to the IEEE 1149.1 standard. Finally, it is expected that, even though 1149.7 is a new standard, it will have a leg up with regards to adaption by industry as its foundation of 1149.1.

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References [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18]

A. W. Ley, “New 1149.7 enhances 1149.1 test access port, maintains compatibility for boundary scan”, 2009. Azumi Kobayashi, Yasuharu Kobayashi and Keiichi Horie, “External Memory BIST for System-in-Package”, IEEE-2005. B. Hailpern, P. Santhanam, "Software debugging, testing, and verification," IBM Systems Journal, 2002. C. Mac Namee, D. Heffernan, "Emerging on-chip debugging techniques for real time embedded systems," IEEE Computing & Control Engg, Dec.2000. Dave Stang, and R. Dandapani, “An implementation of IEEE 1149.1-To avoid violation and other practical In Compliance”, IEEE2002. I. Huang, C. Kao and H. Chen, "A retargetable embedded in circuit emulation module for microprocessors," IEEE Design & Test of Computers, Aug. 2002. IEEE 1149.7 - Texas Instruments Embedded Processors Wiki, Texas Instruments, 2009. John Andrews, “An Embedded JTAG, System Test Architecture”, 1993. L. and M. Ricchetti, “Tapping into P1500 Domains”, Testing Embedded Core-Based Systems, 2001. Manual, “IEEE Standard 1149.1-2001, IEEE Standard Test Access Port and Boundary-Scan Architecture”, 2001. Manual, “IEEE P1149.7 Standard for Reduced pin count and Enhanced functionality Test Access Port and Boundary Scan Architecture”, IEEE-2009. N. Stollon, “Embedded Instrumentation Integration Using IEEE Nexus 5001 and 1149.7”, Design and Reuse, 2009. Peter M. Campbell and Mankaun Vai, “Implementation of IEEE 1149.1 Standard in VHDL”, 1990. S. Lau, “Reinventing JTAG for SOC debugging,” Embedded Systems Design, 2008. S. Lau, “IEEE 1149.7: Expanding and improving JTAG,” Embedded Computing Design, 2009. Subhasish Mitra and Samy Makar Transmeta ,“Design for testability and testing of IEEE 1149.1 TAP controller”,IEEE-2002. Steven F. Oakland, “Combining IEEE Standard 1149.1 with Reduced Pin Count Component Test”, 1991. The Next Generation in Test and Debug Solution- c-JTAG - IEEE 1149.7.

Balwinder Singh has obtained his Bachelor of Technology degree from National Institute of Technology, Jalandhar and Master of Technology degree from University Centre for Inst. & Microelectronics (UCIM), Punjab University, Chandigarh in 2002 and 2004 respectively. He is currently serving as Senior Engineer in Centre for Development of Advanced Computing (CDAC), Mohali and is a part of the teaching faculty and also pursuing Phd from GNDU Amritsar. He has 6+ years of teaching experience to both undergraduate and postgraduate students. Singh has published three books and many papers in the International & National Journal and Conferences. His current interest includes Genetic algorithms, Low Power techniques, VLSI Design & Testing, and System on Chip. Manpreet Kaur received the B.Tech (Electronics and Communication Engineering) degree from the Shaheed Udham Singh Collage of Engineering and Technology, Tangori (Mohali) affiliated to Punjab Technical University, Jalandhar in 2010, and presently she is doing M.Tech. (VLSI design) degree from Centre for Development of Advanced Computing (C-DAC), Mohali and working on her thesis work. Her area of interest is Embedded Systems, VLSI Design and Testing, Digital Designs, etc.

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