International Journal of Electronics and Computer Science Engineering Available Online at www.ijecse.org
302
ISSN: 2277-1956
VHDL Implementation of Efficient Multimode Block Interleaver for WiMAX Deepak Bhardwaj 1, S P Singh 2, V K Pandey 3 1, 2 3 Electronics & Communication Engineering Department of Electronics & Communication Engg, Noida Institute of Engineering and Technology, Greater Noida, U P, India.
[email protected] Abstract-Wireless communication is one of the most vibrant research areas in the communication field today. WLAN and WiMAX are emerging standards for wireless broadband communication system. OFDM is multiplexing technique used in above standards as it reduces inter symbol interference and multipath fading over wireless channel. Standards mentioned above can be implemented efficiently in FPGA. Interleaver plays a vital role in improving the performance of FEC codes in terms of Bit Error Rate over wireless channel. The complete Interleaver has been divided into two sub modules; address generator and interleaved memory. The proposed work presents that a modification in the FSM of address generator for WiMAX Interleaver provides a considerable improvement in terms of logic cells and slice flip flops used. Moreover using this modified address generator an efficient multimode WiMAX Interleaver has been implemented using VHDL. The simulation results and circuit parameters are also presented. Keywords: OFDM; FEC; FPGA; WLAN; WiMAX; VHDL; 1. INTRODUCTION The world is passionately accepting the new wireless communication methods and services. The global demand for multimedia data services has grown at a remarkable pace which has led to the expansion of system capacity in terms of the number of subscribers supported, higher data rate and ubiquitous coverage with high mobility. Broadband wireless access (BWA) systems have evolved as the solution for the persistent demand of these multimedia services [1]. It provides enhancement in multimedia data services and quality of service (QoS). It support simultaneous voice, data and multimedia services to a large group of subscribers without the need for digital subscriber line (DSL) or cable modem. WLAN and WiMAX are emerging standards for wireless broadband communication system. Orthogonal frequency division multiplexing (OFDM) is a multiplexing technique used in above standards. OFDM has grown dramatically in the field of wireless communication because of its robustness against multipath delay spread. This is achieved by using a long symbol period which minimizes the ISI. In OFDM the high rate data stream (bandwidth W) is decomposed into N lower rate data streams and then they are transmitted simultaneously over a large number of subcarriers [2]. A sufficiently high value of N makes the individual bandwidth (W/N) of subcarriers narrower than the coherence bandwidth of the channel. The individual subcarriers experience flat fading only and this can be compensated using a trivial frequency domain single-tap equalizer [3]. The choice of individual subcarrier is such that they are orthogonal to each other. The overlapping of subcarriers is allowed because the orthogonality ensures the separation of subcarriers at the receiver end. This approach results in a better spectral efficiency than that of FDMA systems where no spectral overlap of carriers is allowed. WiMAX is an emerging industry consortium standard for wireless broadband networking. It is based on wireless metropolitan area networking (WMAN) standards. It offers a rich set of features with a lot of flexibility in terms of deployment options and potential service offerings. The WiMAX physical layer (PHY) is based on orthogonal frequency division multiplexing which offers good resistance to multipath and allows WiMAX to operate in Non Line of Site (NLOS) conditions whereas Wireless Local Area Network (WLAN) interconnects two or more communicating devices using some wireless distribution method and usually providing a connection through an
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303 VHDL Implementation of Efficient Multimode Block Interleaver for WiMAX
access point (AP) to the wider internet [4]. WLANs can potentially be a promising tool in different user environments namely home, corporate and public environment etc. WLANs are used to connect wireless users to a fixed LAN in corporate environments. A major WLAN application will be in public sectors where WLAN can be used to connect a user to the backbone network. Airports, hotels, high-rising offices, city centers will be target area for such public WLAN usage [5]. It is becoming more and more evident that WLANs will play a greater role in future. A popular vision of future generations of telecommunications systems suggests that it will be an amalgamation of high data-rate wireless wide area networks and newly standardized WLANs. However systems of the near future will require WLANs with data rate of greater than 100 Mbps. Standards mentioned above can be implemented efficiently in FPGA. A product such as WiMAX implemented on FPGA can easily be upgraded by making necessary changes in the Hardware Description Language (HDL) code. In addition, the TAT of FPGA based circuit is much shorter compared to Application Specific Integrated Circuit (ASIC). Design flexibility is another important advantage of FPGA based implementations. The main function of a communication system is to transmit information from source to destination with sufficient reliability. The error correction codes (ECC) play very important role in modern digital communication systems. Interleaving is a technique that can be used in digital communications systems to enhance the error correcting capabilities of block codes. Interleaving is an important and powerful technique to combat burst of errors for FEC coded signal. This technique is traditionally used to reduce bit error rate (BER) of digital transmission over a burst channel. The Interleaver subsystem rearranges the encoded symbols over multiple code blocks. This effectively spreads out long burst noise sequences so they appear to the decoder as independent random symbol errors which are manageable burst errors. The rest of the paper is organized as follows: Section 2 provides overview of FPGA resources and devices. Section 3 presents the basic detail of interleaving. Hardware modeling for WiMAX Interleaver is described at length in Section 4. Section 5 discusses the implementation and Simulation results, concluding remarks are given in Section 6. 2. FPGA RESOURCES AND DEVICES High processing speed, design flexibility and fast design Turnaround Time (TAT) is the important requirements of BWA to meet the challenges poised to it. These requirements make the designers to choose reconfigurable hardware platform like Field Programmable Gate Array (FPGA). FPGA is an emerging technology to implement wireless standards like WLAN and WiMAX. Professional media equipment designers have traditionally relied on digital signal processing (DSP) devices to provide processing power for audio and video subsystems. For better audio and video streaming performance at lower costs, FPGA are used rather than dozens of DSP device [6]. FPGAs essentially create a universal hardware platform, useful for a number of media applications requiring real time audio and video processing. The FPGAs offer high flexibility which means that many functions can be placed on the most efficient location in the logic flow of the device rather than in peripheral hardware. A product implemented on FPGA can easily be upgraded by making necessary changes in the Hardware Description Language (HDL) code and thus becomes obsolescence free. A FPGA is a semiconductor device that is made up of reprogrammable logic components. These logic components, which are made up of a combination of look-up tables (LUT) and flip-flops (FF) can be programmed to perform simple logic functions operations, as well as more complex combinatorial functions. In recent years, vendors started to include specialty resources in the FPGA fabric such as multipliers, specialty logic units, and block RAM [7]. Moreover, these specialty resources improve the performance for specific operations only, and may not be utilized in much application so different families of FPGAs with similar gate counts can have significantly different capabilities. Block RAM (BRAM) greatly increases FPGA processing power by allowing fast data storage Xilinx has offered two main FPGA families: the high-performance Virtex series and the high-volume Spartan series, with a cheaper easy path option for ramping to volume production. The company also provides two CPLD lines, the Cool Runner and the 9500 series [8]. The Virtex-II Pro, Virtex-4, Virtex-5, and Virtex-6 FPGA family’s targets high performance applications that require higher clock rates, extensive math operations or significant use of single cycle timed loops.
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3. INTERLEAVING Interleaving is a technique that can be used in digital communications systems to enhance the error correcting capabilities of block codes. The Interleaver subsystem rearranges the encoded symbols over multiple code blocks. This effectively spreads out long burst noise sequences so they appear to the decoder as independent random symbol errors which are manageable burst errors [9]. Interleaving can be classified as either periodic or pseudo-random. The periodic Interleaver orders the data in a repeating sequence of bytes. The two main classes of periodic interleaving are: block interleaving and convolution interleaving. The block Interleaver accepts symbols in blocks and performs identical permutations over each block of data. One way to accomplished this involves taking the input data and writing the symbols by rows into a matrix with i rows and n columns and then reading the data out of the matrix by columns [10]. This is referred to as a (n,i) block Interleaver and in convolution Interleaver the code word symbol from the encoder is fed into the array of shift registers, one code symbol to each row. With each new code word symbol the commutator switches to a new register and the new code symbol is shifted out to the channel [11]. In OFDM based wireless standards like WLAN and WiMAX block Interleaver is used. All FEC coded data bits are interleaved by a block Interleaver, with a block size corresponding to the number of coded bits per the allocated sub channels per OFDM symbol, Ncbps. The Interleaver is defined by a two-step permutation. The first ensures that adjacent coded bits are mapped onto nonadjacent subcarriers [2]. The second permutation ensures that adjacent coded bits are mapped alternately onto less or more significant bits of the constellation, thus avoiding long runs of lowly reliable bits, d represents number of columns of the block Interleaver which is typically chosen to be 16. mk is the output after first level of permutation and k varies from 0 to Ncbps -1. S is a parameter defined as s= max {1, Ncpc/2}, where Ncpc is the number of coded bits per subcarrier.
N cbps m k = d
(k % d
)+
k d
d × mk m j k = s × k + mk + N cbps − % s s N cbps Where % and
(1)
(2)
signify modulo and floor functions respectively. 4. HARDWARE FOR INTERLEAVER
4.1-Interleaving in WiMAX The hardware model of OFDM based WiMAX interleaver consists of two sections: address generator and interleaver memory as shown in Fig. 1 [12, 13]. The address generator is basically the simultaneous implementation of (1) and (2) which is used to generate the write address and read address for the interleaver memory. Block Interleaver uses two memory blocks out of which one memory block is to write and the other is used to read, based on the value of select (sel) signal [14].
Figure 1 Top level view of interleaver
The address generator circuit will generate addresses by evaluating the above equations with relevant Ncbps for different Interleaver Depths (IDs) to incorporate various code rates and modulation schemes as shown in Table 1 for IEEE 802.16e.
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305 VHDL Implementation of Efficient Multimode Block Interleaver for WiMAX
Table 1 Permitted Interleaver depth in IEEE 802.16e for all code rates and modulation schemes [15].
Modulation Scheme
QPSK (S=1)
Code rate
½
16-QAM (S=2)
3/4
1/2
64-QAM (S=3)
3/4
1/2
2/3
¾
Interleaver depth, Ncbps in bits
96 144 192 288 288 384 432 192 288 384 576 576 288 432 576 384 576 480 576 The write addresses for QPSK modulation scheme with Ncbps=96 are shown in Table 2. To restrict the length of paper, complete addresses for other modulation schemes are not shown. Only first 32-permutation sample addresses for different code rates and modulation schemes are shown in Table 2 to Table 17. Table 2 Write addresses for QPSK modulation scheme (Ncbps=96). 0 48 1 49 2 50 3 51 4 52 5 53
6 54 7 55 8 56 9 57 10 58 11 59
12 60 13 61 14 62 15 63 16 64 17 65
18 66 19 67 20 68 21 69 22 70 23 71
24 72 25 73 26 74 27 75 28 76 29 77
30 78 31 79 32 80 33 81 34 82 35 83
36 84 37 85 38 86 39 87 40 88 41 89
42 90 43 91 44 92 45 93 46 94 47 95
Table 3 First 32 write addresses generated for QPSK modulation with Ncbps=144 (ID = 001 and increment value=9)
0 72 1 73
9 81 10 82
18 90 19 91
27 99 28 100
36 108 37 109
45 117 46 118
54 126 55 127
63 135 64 136
Table 4 First 32 write addresses generated for QPSK modulation with Ncbps=192 (ID = 010 and increment value=12)
0 96 1 97
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12 108 13 109
24 120 25 121
36 132 37 133
48 144 49 145
60 156 61 157
72 168 73 169
84 180 85 181
IJECSE, Volume1, Number 2 Deepak Bhardwaj et al.
Table 5 First 32 write addresses generated for QPSK modulation with Ncbps=288 (ID = 011 and increment value=18)
0 144 1 145
18 162 19 163
36 180 37 181
54 198 55 199
72 216 73 217
90 234 91 235
108 252 109 253
126 270 127 271
Table 6 First 32 write addresses generated for QPSK modulation with Ncbps=384 (ID = 100 and increment value=24)
0 192 1 193
24 216 25 217
48 240 49 241
72 264 73 265
96 288 97 289
120 312 121 313
144 336 145 337
168 360 169 361
Table 7 First 32 write addresses generated for QPSK modulation with Ncbps=432 (ID = 101 and increment value=27)
0 216 1 217
27 243 28 244
54 270 55 271
81 297 82 298
108 324 109 325
135 351 136 352
162 378 163 379
189 405 190 406
Table 8 First 32 write addresses generated for QPSK modulation with Ncbps=480 (ID = 110 and increment value=30)
0 240 1 241
30 270 31 271
60 300 61 301
90 330 91 331
120 360 121 361
150 390 151 391
180 420 181 421
210 450 211 451
Table 9 First 32 write addresses generated for QPSK modulation with Ncbps=576 (ID = 111 and increment value=36)
0 288 1 289
36 324 37 325
72 360 73 361
108 396 109 397
144 432 145 433
180 468 181 469
216 504 217 505
252 540 253 541
Table 10 First 32 write addresses generated for 16-QAM modulation with Ncbps=192 (ID= X00 and increment value= 13, 11)
0 96 1 97
13 109 12 108
24 120 25 121
37 133 36 132
48 144 49 145
61 157 60 156
72 168 73 169
85 181 84 180
Table 11 First 32 write addresses generated for 16-QAM modulation with Ncbps=288 (ID= X01 and increment value= 19, 17)
0 144 1 145
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19 163 18 162
36 180 37 181
55 199 54 198
72 216 73 217
91 235 90 234
108 252 109 253
127 271 126 270
307 VHDL Implementation of Efficient Multimode Block Interleaver for WiMAX
Table 12 First 32 write addresses generated for 16-QAM modulation with Ncbps=384 (ID= X10 and increment value= 25, 23)
0 192 1 193
25 217 24 216
48 240 49 241
73 265 72 264
96 288 97 289
121 313 120 312
144 336 145 337
169 361 168 360
Table 13 First 32 write addresses generated for 16-QAM modulation with Ncbps=576 (ID= X11 and increment value= 37, 35)
0 288 1 289
37 325 36 324
72 360 73 361
109 397 108 396
144 432 145 433
181 469 180 468
216 504 217 505
253 541 252 540
Table 14 First 32 write addresses generated for 64-QAM modulation with Ncbps=288 (ID= X00 and increment value= 20, 17, 17)
0 145 1 146
20 162 18 163
37 182 38 180
54 199 55 200
74 216 72 217
91 236 92 234
108 257 109 254
128 270 126 271
Table 15 First 32 write addresses generated for 64-QAM modulation with Ncbps=384 (ID= X01 and increment value= 26, 23, 23)
0 193 1 194
26 216 24 217
49 242 50 240
72 265 73 266
98 288 96 289
121 314 122 312
144 337 145 338
170 360 168 361
Table 16 First 32 write addresses generated for 64-QAM modulation with Ncbps=432 (ID= X10 and increment value= 29, 26, 26)
0 217 1 218
29 243 27 244
55 272 56 270
81 298 82 299
110 324 108 325
136 353 137 351
162 379 163 380
191 405 189 406
Table 17 First 32 write addresses generated for 64-QAM modulation with Ncbps=576 (ID= X11 and increment value= 38, 35, 35)
0 38 73 108 146 289 324 362 397 432 1 36 74 109 144 290 325 360 398 433 4.2-Novel Address Generator with Improved Preset Block
181 470 182 468
216 505 217 506
254 540 252 541
The address generator circuit is used to generate (1) write addresses (2) read addresses (3) sel signals. The complete circuit is shown in Fig. 2. The circuit consists of stages of multiplexers which implement equal or unequal increments for various modulation schemes as shown in Table 18. As given in [15] the design concept contains three levels of multiplexer (MUX). The first level of MUXs implements the unequal increments required in 16-QAM and 64-QAM. The four interleaver depths of 16-QAM as shown in Table 3.18 are implemented by the first four MUXs from the top in level 1. The select inputs of these four
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MUXs are tied together and are driven by a T-flip-flop named QAM16_SEL. Similarly the last four MUXs implement interleaver depths for 64-QAM modulation. The select inputs are driven by a MOD-3 counter named QAM64_SEL. Table 18 Permitted modulation schemes with incremented values [15].
Modulation
MOD_TYPE
QPSK
00
Interleaver Depth
ID
Increment Values
Whether equally spaced
96 000 6 YES 144 001 9 YES 192 010 12 YES 288 011 18 YES 384 100 24 YES 432 101 27 YES 480 110 30 YES 576 111 36 YES 16-QAM 01 192 X00 13,11 NO 288 X01 19,17 NO 384 X10 25,23 NO 576 X11 37,35 NO 64-QAM 1X 288 X00 20,17,17 NO 384 X01 26,233,23 NO 432 X10 29,26,26 NO 576 X11 38,35,35 NO The second level MUXs basically pick up one inputs based on the values of ID. The topmost MUX in level 2 implements the eight interleaver depths for QPSK modulation scheme available by concatenation of sub-channels. The second and third MUXs in level 2 are used for 16-QAM and 64-QAM respectively. The outputs from level 2 MUXs are routed to the next section by level 3 MUX based on MOD_TYP value. The 7-bit output from the level 3 MUX acts as one input to the 10-bit adder circuit after zero padding. The other input of the adder comes from accumulator which holds the previous address. After addition a new address is written in the accumulator. The preset logic is a FSM whose principal function is to generate the correct beginning addresses for all subsequent iterations. Unlike [15], our novel design includes two more signals generated by preset logic which are start signal and select signal. Start signal is used to provide a pulse signal to QAM16_SEL and QAM64_SEL, when the addresses reach to the terminal value of the iteration (e.g. 90 in table 3.2).This is used to provide the correct functionality of the interleaver. Moreover unlike [14] a select signal generated from preset logic is used as input for the generation of read addresses and sel signals. The select signal simply provides a pulse signal at the end of the one complete Ncbps (e.g. 95 in table 3.2). Using this select signal the circuitry used in read addresses and sel signal generator become simpler. A careful examination of Table 3.18 and address generated for different modulation schemes with different code rate shows that a small modification in the FSM of the preset logic can lead to considerable improvement in terms of resource utilised. From Table 18. Some interleaver depths (Ncbps=288,384,432,576) will generate the same terminal address for both QPSK and 64QAM modulation schemes. From Fig. 3 when FSM enters into the first state (SF) with CLR=1, based on the value in MOD_TYP it makes transition to one of the three possible next states (SMT0, SMT1 or SMT2). Each state in this level represents one of the possible modulation schemes.
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309 VHDL Implementation of Efficient Multimode Block Interleaver for WiMAX
Figure 2 Address Generators for WiMAX Interleaver
The FSM thereafter makes transition to one of the next level states (SID0 to SID7 from SMT0, SID0 to SID3 from SMT1 or SMT2) based on the value in ID. If MOD_TYPE is 64-QAM and ID is X00 (Ncbps=288) then this state is directly transferred to the ID-3 state of QPSK modulation as shown in Fig. 3. This will generate the same pattern of addresses. If no changes take place in the values of ID and MOD_TYP, the FSM will follow the same route of transition and the same set of interleaver addresses will continually be generated. If at any stage a change in ID and MOD_TYP is needed then the circuit will follow a different path. The circuit responds to CLR followed by ID and MOD_TYP inputs at any stage of the FSM. With CLR=1 it comes back to SF state irrespective of its current position and there after transits to desired states in response of new values in ID and MOD_TYP. Similarly the ID states X01, X10 and X11 (Ncbps=384,432,576) for 64-QAM modulation scheme will be directly transferred to the 100,101and 111 respective ID states for QPSK modulation schemes and will follow the same route as for Ncbps=288.
Figure3 Modified FSM
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4.3-Interleaved Memory Operation The proposed interleaver memory architecture is as shown in “Fig.2”. It comprises of two memory modules RAM-I and RAM-II [14]. When one memory block RAM-I is being used to write over, the other one is used to read from. After completing one FEC block, the memory modules exchange their operations i.e. now RAM-II is used to write over and RAM-I is used to read from. The multiplexers are used to provide correct read and write addresses while inverter is used to provide correct write and read enable signals.
Figure 4 Interleaved memory
5. IMPLEMENTATION AND SIMULATION RESULTS 5.1-WiMAX Address Generator The VHDL model of the address generator for OFDM based WiMAX is prepared using Xilinx Integrated Software Environment (ISE) and is implemented on Xilinx spartan-3 (Device: XC3S400) FPGA platform. The results are obtained using Model Sim Xilinx edition II 5.7g. The Comparative analysis of address generator for [15] and this work are shown in Table 19. Our approach shows a 36.2% improvement in terms of logic cells and 22% improvement in terms of slice flip flops. The simulations results of the address generated for different modulation schemes with different code rates are shown in Fig. 5 to Fig. 7. Table 19 Result for WiMAX Address Generator
FPGA Resources
Number of Slices
Number of Slice FF
Number of bonded IOBs
Number of GCLKs
Ref [15]
226
48
17
2
This work
144
37
17
2
Percentage improvement
36.2%
22.9%
NIL
NIL
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311 VHDL Implementation of Efficient Multimode Block Interleaver for WiMAX
Figure 5 Simulation waveform for QPSK modulation scheme (Ncbps=96).
Figure 6 Simulation waveform for 16-QAM modulation scheme (Ncbps=192)
Figure 7 Simulation waveform for 64-QAM modulation scheme (Ncbps=288)
5.2-WiMAX Interleaver The VHDL model of the complete interleaver for OFDM based WiMAX (IEEE 802.16e) is prepared using Xilinx Integrated Software Environment (ISE) and is implemented on Xilinx spartan-3 (Device: XC3S400) FPGA platform. The results are obtained using ModelSim Xilinx edition II 5.7g. The obtained results are shown in Table 20. To verify
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the simulation results first 16 bits of data input are held high. The effect of this is shown as consecutive 1’s are separated by a definite increment according to the modulation scheme and code rate applied To restrict the length of paper, simulation results for other modulation schemes are not shown. Table 20 Results for WiMAX Interleaver
FPGA Resources
This Work
Number Of Slices Number Of Slice Flip Flops Number Of 4 Input LUTs Number Of Bonded IOBs Number Of BRAMs Number Of GCLKs Frequency
167 50 293 9 2 2 154.5 MHZ
. Figure 8 Simulation waveform for QPSK modulation scheme (Ncbps=96).
6. Conclusion The complete interleaver has been divided into two sub modules; address generator and interleaved memory. A modification in the FSM of address generator for WiMAX standard has reduced the number of slices by 82 and number of slice flip flops by 11 which show a 36.2% and 22.9% improvement respectively as compared to available literature. Also, using this modified address generator an efficient multimode block interleaver for WiMAX has been implemented with all permitted code rates and different modulation schemes. The circuit parameters and simulation results obtained using ModelSim XE II software are also presented. References [1] [2] [3] [4] [5] [6] [7]
W. Konhauser, “Broadband wireless access solutions –progressive challenges and potential value of next generation mobile networks”, Wireless Personal Communications, vol 37, May 2006, pp.243--259. U. S. Jha and R. Prasad, “OFDM Towards Fixed and Mobile Broadband Wireless Access,” Artech House Publisher, London, 2007. A. Sghaier, S. Ariebi, and B. Dony, “A pipelined implementation of OFDM transmission on reconfigurable platforms”, CCECE08 Conference, Dec, 2007, pp. 801-804. IEEE std. 802.11a-1999, ‘‘Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications: High Speed Physical Layer in the 5 GHz Band,’’ July 1999. IEEE std. 802.11g-2003, “Wireless LAN Medium Access Control (MAC) and Physical Layer (PHY) specifications, Amendment 4: Further Higher Data Rate Extension in the 2.4 GHz Band” July 2003. S. Brown & J. Rose, “FPGA and CPLD Architectures: A Tutorial”, IEEE Design & Test of Computers, Summer 1996, pp. 42-57. Xilinx, “Spartan-3 FPGA Family: Complete Data Sheet,” available at www.xilinx.com
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[8] [9] [10] [11] [12] [13] [14] [15]
Xilinx, “virtex FPGA Family: Complete Data Sheet,” available at www.xilinx.com. E. Tell, and D. Liu, “A hardware architecture for a multimode block interleaver”, ICCSC, Moscow, Russia, June 2004. S A Hanna, “Convolutional interleaving for digital radio communication”. B. K. Upadhyaya and S. K. Sanyal, “VHDL Modeling of Convolutional Interleaver-Deinterleaver for efficient FPGA implementation, “International Journal of Recent Trends in Engineering, Academy Publisher, Finland, Vol 2, No. 6, November, pp. 66-68, 2009. “Air interface for fixed broad band wireless access systems” IEEE standard 802.16-2004, 2004 “Air interface for fixed and mobile broad band wireless access systems” IEEE standard 802.16e, 2005 B. K. Upadhyaya and S. K. Sanyal, “Design of a novel FSM based reconfigurable multimode interleaver for WLAN application” 2011 IEEE. B. K. Upadhyaya, I. S. Misra and S. K. Sanyal, “Novel design of address generator for WiMAX multimode interleaver using FPGA based finite state machine,” ICCIT 2010, AUST, Dhaka, Dec., 2010.
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