What is VHDL?

Introduction to VHDL

Agenda • Introduce VHDL • Basic VHDL constructs • Implementing circuit functions – – – –

Logic, Muxes Clocked Circuits Counters Shifters Counters, State Machines

• FPGA design and implementation issues – FPGA resource utilization – Implementation constraints

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Section 1 Introduction • What a is s VHDL? • VHDL Design Flow • Basic VHDL constructs – Entity/ Architecture – Logical operators

• Using Tools to synthesize VHDL

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Introducing VHDL • VHDL was as des designed g ed u under de the e VHSIC SCp program og a by the Department of Defense • VHDL acronym stands for Very High Speed Integrated Circuit (VHSIC) Hardware Description Language

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What is VHDL? • VHDL iss a language a guage used to o desc describe be sys systems e s • It can be used to design and simulate digital circuits • VHDL was adopted by IEEE in 1987 as a standard – IEEE 1076-1987 – -Most Common version VHDL 93 – Most recent version VHDL 2008

• STD_LOGIC Libraries are covered by IEEE 1164 • Simulation enhancements covered in VITAL

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Why VHDL? • • • • • •

Capab e o Capable of more o e co complex p e des designs g s than a sc schematics e a cs Not bound to a vendor Supports design abstraction It is a standard Supports design reuse The DOD requires it

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Synthesis vs. Simulation

Simulatable

VHDL Synthesizable

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VHDL Design Flow Specify Design Write VHDL Code Simulate VHDL Synthesize Design I l Implement t design d i Verify Timing Feed Back to any p stream point. p up

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Building Blocks • The e Entity y / Architecture c ec u e pa pair – – – – –

The basis of all VHDL designs Entities can have more then one Architecture Architectures can have only one entity Entities define the interface (i.e. I/Os) for the design Architectures define the function of the design

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The Entity Details

entity entity_name is generic (generic_list); (generic list); port (port_list); end entityy_name;;

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The Entity Details

D

Q

clk DFLOP

=

entity DFLOP is Port ( D : in std_logic; g ; clk : in std_logic; Q : out std_logic ); end DFLOP;

(Port_names : MODE type); MODE types: in, out, inout or buffer

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The Architecture Details

architecture architecture_name of entity_name is declaration section b i begin concurrent statements end architecture_name; architecture name; • Declaration section – Signals, constants and components local to the architecture can be declared here

• Concurrent C t statements t t t – Where the circuit is defined

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Logical Operators

• VHDL predefines the logic operators – NOT Æ

HIGHER PRECEDENCE

– AND – NAND – OR – NOR – XOR

There is no implied precedence for these operators. If there are two or more different operators in an equation, the order of precedence is from left to right

– XNOR

Note: XNOR supported in standard 1076-1993

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Comments • -- ((Double oub e minus us ssign) g ) is s the e co comment e mark a • All text after the -- on the same line is taken as a comment • Comments only work on a single line • There is no block comment in VHDL 93 ((Availible in 2008 /* */

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Example Entity/Architecture -- Example of two input AND gate library IEEE; use IEEE.std_logic_1164.all; entity and2vhdl is port ( In_a : in std_logic; g ; In_b : in std_logic; Out_c : out std_logic ); end and2vhdl; architecture Behavioral of and2vhdl is begin Out_c