Pentium IV, CPUs have greatly improved in terms of performance. Accordingly, their power consumption has increased dramatically [1][2]. To reduce the power ...
An Output Impedance-Based Design of Voltage Regulator Output Capacitors for High Slew-Rate Load Current Transients Jia Wei and Fred C. Lee Center for Power Electronics Systems The Bradley Department of Electrical and Computer Engineering Virginia Polytechnic Institute and State University Blacksburg, VA 24061 USA
This work was supported primarily by Artesyn, Delta Electronics, Hipro Electronics, Hitachi, Infineon, Intel, Intersil, National Semiconductor, Power-One, TDK and Texas Instruments. Also, this work made use of ERC shared facilities supported by the National Science Foundation under Award Number EEC-9731677. Any opinions, findings and conclusions or recommendations expressed in this material are those of the author(s), and do not necessarily reflect those of the National Science Foundation.
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I. INTRODUCTION Microprocessors in today’s computers continue to increase in speed and power. From the Intel 80X86 series to today’s Pentium IV, CPUs have greatly improved in terms of performance. Accordingly, their power consumption has increased dramatically [1][2]. To reduce the power loss, an evolution began when the high-performance Pentium processor was driven by a non-standard, less-than-5V power supply, instead of drawing its power from the 5V plane on the system board. In order to provide the power to the processor as quickly as possible, the voltage regulator (VR), a dedicated DC-DC converter, is placed in close proximity to power the processor. In the beginning, VRs drew power from the 5V output of the silver box. As the power delivered through the VR increased so dramatically, it became no longer efficient to use the 5V bus. Then, for desktop and workstation applications, the VR input voltage moved to the 12V output of the silver box. This trend began when Pentium II processors emerged. Today’s Pentium IV processors use 12V-input VRs. The VR evolution has been driven by the fast development of microprocessors. Fig. 1 shows the Intel roadmap for voltage and current of the 32-bit CPU load for VRs [1]. Fig. 1(a) shows that future microprocessors will run at very low voltages (sub-1V) with very tight voltage tolerances. Meanwhile Fig. 1(b) indicates a high current consumption, and fast dynamics of about 400 A/us. To meet the stringent transient response
Vcc (V)
Keywords: output capacitor; high slew-rate; impdeance; voltage regulator (VR)
requirement, and also to reduce the passive component size, it is predicted that the VR switching frequency will move into the MHz range in the next few years. This situation presents great challenges. Today’s VRs use the multiphase interleaving synchronous buck topology [3][4][5][6][7]. The switching frequency is normally in the 300~500KHz range. OSCON capacitors and ceramic capacitors are both used at the output of the VR to handle the high slew-rate load current transient response. There has been some valuable work done by other researchers [8]~[18] on the design of the output capacitors. This paper discusses the design of the VR output capacitor based on output impedance. The relationship between the number of OSCON capacitors and the number of ceramic capacitors is presented, as is the impact on the choice of the switching frequency. The all-ceramic solution is compared with the OSCON-ceramic combination. It is shown that at high switching frequencies, the all-ceramic solution is better. Simulation and experimental results verify the theoretic prediction.
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Abstract — This paper presents an output impedance-based approach for designing the voltage regulator (VR) output capacitors at high-slew-rate load current transient. Different types of capacitors are analyzed. Various options for VR output capacitors are discussed and compared. The technology and market trend indicates that the all-ceramic solution is likely to be the most cost-effective approach.
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(b) Fig. 1. Intel 32-bit CPU core voltage (a) and current (b) roadmaps.
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II.
THE OSCON-CERAMIC MIXTURE SOLUTION
Fig. 2 shows an example of the VR output voltage-current load line from the Intel VR10 specs [2]. The horizontal axis is the VR output current, and the vertical axis is the VR output voltage. The adaptive voltage positioning (AVP) concept requires the voltage to drop as the current increases. The solid line is the nominal load line, and the dotted lines are the tolerance band. The slope of the load line is called Rdroop. When there is a load current step change ∆Io, the corresponding VR output voltage change is ∆Vo=∆Io×Rdroop. The acceptable ∆Vo during a transient response is decreasing as microprocessors become more powerful; therefore, the specified Rdroop is also decreasing. This poses great challenges for VR design. The example in Fig. 2 shows an Rdroop of 1.214 mΩ. From the standpoint of impedance, the required output voltage droop function of the VR indicates that the VR is a voltage source with output impedance equal to Rdroop. This goal is achieved by using output capacitors and closed-loop control. There are two popular types of capacitors used at the VR output: One is the OSCON capacitor and the other is the ceramic capacitor. An OSCON capacitor is essentially an electrolytic capacitor. It features large capacitance and relatively low values of equivalent series resistor (ESR) and equivalent series inductance (ESL). A ceramic capacitor has even lower ESR and ESL than an OSCON capacitor, but also has lower capacitance. Fig. 3(a) shows the equivalent circuit of a real capacitor. It consists of three components: a pure capacitor C, the ESR and the ESL. The asymptotic impedance curve of the capacitor is shown in Fig. 3(b). There are two zeros on the curve. Roughly speaking, the ESR and the C form the first zero, namely fz1; the ESR and the ESL form the second one, namely fz2. The mathematic expressions are
1 , and 2π ⋅ ESR ⋅ C ESR f z2 = 2π ⋅ ESL
f z1 =
(1)
Z
ESL ESR ESR
C
12V
(2)
Core Voltage
Zo(s)
Rdroop
(a)
Zc
Zo-close
Nominal M ax. M in. 10
20
30
40
fc
Zo-open 50
60
f
Fig. 4(a) shows a multiphase buck VR with OSCON output capacitors. As shown in Fig. 4(b), the dotted line marked as ZC is the output capacitor impedance. The dashed line marked as Zo-open is the open-loop output impedance of the converter. In the low-frequency range, the choke inductor ESR dominates Zo-open; then, there is the LC resonance between the choke inductor and the output capacitor; after the LC resonance, Zo-open follows ZC. The shape of Zo-open is not the desired constant; to get constant output impedance, closed-loop control is needed. A closed-loop control has a bandwidth of fc. Within fc, the control loop reshapes Zo-open to the closed-loop output impedance, marked as Zo-close, shown as the solid line in Fig. 4(b). Beyond fc, the control loop cannot be effective; therefore Zo-close follows Zo-open. Since today’s VRs normally operate at 300~500 KHz, it’s very easy to achieve fc>20KHz; however, it’s very difficult to achieve fc>500KHz. As long as the control loop design tries to make Zo-close=Rdroop, Zo-close can be kept constant up to 500 KHz. However, Zo-close will eventually increase in the high-frequency range due to the ESL effect of OSCON capacitors.
Z
0
f z2
(a) (b) Fig. 3. The frequency characteristics of a capacitor: (a) the equivalent circuit, and (b) the asymptotic curve of capacitor impedance.
The capacitor impedance is dominated by different parameters in different frequency ranges. Below fz1 the capacitance C dominates; between fz1 and fz2 the ESR dominates, and beyond fz2 the ESL dominates. Using an OSCON capacitor as an example, C=820µF, ESR=12mΩ, and ESL=4nH; some simple calculation gives that fz1=16KHz and fz2=477KHz. 1.3 1.28 1.26 1.24 1.22 1.2 1.18 1.16 1.14 1.12 1.1
f z1
0
70
80
Output Current
Fig. 2. A load line example from the Intel VR10 specs.
90
0
20K
500K
f
(b) Fig. 4. VR output impedance: (a) a multiphase buck VR without OSCON output capacitors, and (b) the asymptotic curves of impedance.
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ESROSCON (3) R droop where ESROSCON is the ESR of a single OSCON capacitor. Fig. 2 shows Rdroop=1.214mΩ; also considering ESROSCON=12mΩ, formula (3) gives nOSCON≈11. Fig. 5 shows the time domain switching model simulation of the transient response. The load current step change is from 70 A to 0 A @ 70 A/µs. Based on the load line specs shown in Fig. 2, the value of Vo is not allowed for spike into the forbidden region (where Vo>1.3V). But it is clearly shown that the Vo spike goes into the forbidden region. In addition, the steady -state voltage ripple is very large. This Vo waveform is unacceptable. The bad Vo waveform exists because Zo-close cannot be kept at Rdroop in the high frequency range due to the ESL effect of the OSCON capacitors. The solution is to parallel ceramic capacitors with OSCON capacitors. Ceramic capacitors have better high-frequency characteristics than OSCON capacitors. An example of ceramic capacitor parameters are as follows: C=100µF and ESR=1mΩ. Some simple calculations based on formula (1) yield that fz1=1.6MHz. Also, the ESL of ceramic capacitors has negligible impact, and is therefore neglected. The characteristics of OSCON capacitors are shown in Fig. 6(a). The impedance is given by n OSCON =
ESROSCON s ⋅ ESLOSCON 1 + + (4) s ⋅ nOSCON ⋅ COSCON nOSCON nOSCON The characteristics of ceramic capacitors are shown in Fig. 4.13 (b). The impedance is given by Z OSCON (s) =
Z cer ( s ) =
1 s ⋅ ncer ⋅ C cer
+
ESRcer ncer
polemix
1 1 ⋅ + n ncer ⋅ Ccer OSCON ⋅ C OSCON
1.40 1.35
Forbidden Region !!!
1.30 1.25 1.20 1.15 1.10 10
20
Io step: 0~70A, 70A/us 30 40 50 t(us) 60
Fig. 5. Simulated Vo transient response when using all OSCON capacitors. Z
ESL OS CON n OS C ON Z OSCON
E SROS CON n OS C ON
ESR O SCON n OSCON
n OS CON COS C ON 0
(5)
When the OSCON and ceramic capacitors are in parallel, the impedance of the mixture is a parallel of ZOSCON(s) and Zcer(s), given by 1 Z mix ( s) = 1 1 (6) + Z OSCON ( s ) Z cer ( s) The solid curve in Fig. 6(c) shows the combined characteristics of the two types of capacitors. There is a pole marked as polemix on the curve where ZOSCON(s) and Zcer(s) intersect. Because the two types of capacitors are in parallel, the lower-impedance one dominates. Therefore, below polemix, Zmix(s) follows ZOSCON(s), while beyond polemix, Zmix(s) follows Zcer(s). The expression of polemix is given by: 1 1 = ⋅ 2π ESROSCON ESRcer + ncer nOSCON
ESROSCON>> ESRcer and COSCON>> Ccer, which are true in practical cases, it can be approximated that 1 n 1 polemix ≈ ⋅ OSCON ⋅ (8) 2π ESROSCON ncer ⋅ Ccer Formula (8) shows that the ESR of the OSCON capacitors and the C of the ceramic capacitors determine the location of polemix. Fig. 7 shows a simulated Zmix(s). The parameters are nOSCON=11, ESROSCON=12mΩ, COSCON=820µF, ncer=3, ESRcer=1mΩ, and Ccer=100µF. Formula (8) predicts an approximate polemix≈490KHz. This prediction matches the curve in Fig. 7. A higher number of ceramic capacitors means a lower polemix. In Fig. 8, fz1 and fz2 are the two zeros of the OSCON
Vo(V)
In Fig. 4(b) Zo-close is constant up to 500 KHz. The equivalent ESR of the group of OSCON capacitors in parallel determines the Zo-close value. Because the goal is to achieve Zo-close=Rdroop, the number of OSCON capacitors needed is thus given by
(7)
From formula (7), it is observed that 1/polemix is just the RC time constant of the loop formed by the two types of capacitors shown in Fig. 6(c). By making the assumption that
20K
500K
f
(a) Z
ESR cer n cer
Zcer
n cer C cer ESR cer n cer 0
1.6M
f
20K 500K 1.6M polemix
f
(b) Z
E SLOS C ON nOS C ON E SROS C ON nOS C ON n OS C ON × C OS C ON
Z cer
E SR cer n cer n cer C cer
ZOSCON ESROS CON n OS CON ESR cer n cer
0
(c) Fig. 6. New capacitor characteristics achieved by mixing two types of capacitors: (a) OSCON capacitor characteristic; (b) ceramic capacitor characteristic; and (c) the characteristics by mixing OSCON and ceramic capacitors.
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Z
0
Zm ix
Gain (dB)
- 20 - 40 R droop
-60
Zo-close
(b)
-80
fc
90
Phase (°)
fz1
0 Z
60 30
R droop
10
100
1K
10K 100K
1M
(c)
10M
f(Hz) fc
Z
Z m ix
Zo-close
(a)
fc f z1
fz2
1.6M
f
f z1
0
f z2
1.6M
f
Fig. 8. The Zo-close(s) created by different amounts of ceramic capacitance: (a) too little ceramic capacitance; (b) the right amount of ceramic capacitance; and (c) too much ceramic capacitance. 1.40 1.35
Forbidden Region !!!
1.30
Vo(V)
capacitor, and fc is the control bandwidth. The dashed line marked as Zmix represents the characteristics created by mixing OSCON and ceramic capacitors. The solid line Zo-close is the achieved closed-loop output impedance. Fig. 8(a) shows the case when the ceramic capacitance is so low that polemix>fz2. Zo-close will increase after fz2, following the OSCON ESL effect, until the point at which the ceramic capacitor characteristic Zcer occurs. After that, because Zcerfc_A, the all-ceramic solution requires less of a footprint area. It can be easily derived that A ESLOSCON 2π ⋅ C cer ⋅ OSCON ⋅ ESROSCON + A ESR OSCON ⋅ C cer cer
(16)
Because of the higher control bandwidth and fewer ceramic capacitors needed for all-ceramic solution, there exists a bandwidth f$_A that makes Costcerf$_A. This means when fc>f$_A, the all-ceramic solution is cheaper. It can be easily derived that
and the total footprint area of the all-ceramic solution is 1 S cer = ⋅ Acer (13) 2π ⋅ Rdroop ⋅ f c ⋅ Ccer
fc _ A =
(15)
1 2π ⋅ Rdroop ⋅ f c
(c)
Fig. 14. Options for VR output capacitors: (a) OSCONs plus ceramics; (b) a non-viable solution; and (c) the all-ceramic solution.
V.
EXPERIMENTAL RESULTS
A transient response test is performed to verify the theoretical prediction. The design spec is the VR10 load line shown in Fig. 2. The switching frequency of the multiphase buck VR is 1 MHz. Fig. 15 shows the test waveforms. Fig. 15(d) shows the load current, which steps down from 60 A to 0 A with 60A/µs
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slew rate. Figs. 15(a)~(c) are the VR output voltage waveforms, and they correspond to the cases shown in Fig. 14(a)~(c). The dashed lines above which the graphs say “forbidden region” are where Vo=1.3V. Vo is 1.275 V at a load of 0 A, and is 1.19 V at a load of 60 A. Case Fig. 15(a) uses 11 OSCON capacitors plus 300µF ceramic capacitors, and has a good Vo waveform; Fig. 15(b) uses four OSCON capacitors plus 300µF ceramic capacitors, and the Vo spike goes into the forbidden region as predicted; Fig. 15(c) uses 800µF ceramic capacitors, and also has a good Vo waveform.
Forbidden Region
Vo
(a)
Forbidden Region
Vo
(b)
Forbidden Region
Vo ∆Io =60 A
(c)
[1] Intel Technology Symposium 2001 report. [2] Intel Corp., “Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD) 10.0 Design Guidelines,” April 2003. [3] M. Zhang, M. Jovanovic and F. C. Lee, “Design Considerations for Low-Voltage On-Board DC/DC Modules for Next Generations of Data Processing Circuits,” IEEE Transactions on Power Electronics, volume: 11, issue: 2, March 1996, pp. 328 –337. [4] X. Zhou, P. L. Wong, P. Xu, F. C. Lee and A. Q. Huang, “ Investigation of Candidate VRM Topologies for Future Microprocessors,” IEEE Transactions on Power Electronics, volume: 15, issue: 6, Nov. 2000, pp. 1172 -1182. [5] X. Zhou, P. Xu and F. C. Lee, “A High Power Density, High Frequency and Fast Transient Voltage Regulator Module with a Novel Current Sharing Technique,” in Proc. IEEE Appl. Power Electron. Conf. (APEC), 1999, pp. 289-294. [6] Y. Panvo and M. Jovanovic, “Design Consideration for 12-V/1.5-V, 50-A Voltage Regulator Modules,” in Proc. IEEE Appl. Power Electron. Conf. (APEC), 2000, pp. 776-783. [7] P. Xu, X. Zhou, P. Wong, K. Yao and F. C. Lee, “Design and Performance Evaluation of Multi-Channel Interleaving Quasi-Square-Ware Buck Voltage Regulator Module,” HFPC’00. [8] R. Miftakhutdinov, “Analysis and Optimization of Synchronous Buck Converter at High Slew-Rate Load Current Transients,” proceedings of IEEE PESC’00, pp. 714-720. [9] R. Miftakhutdinov, “Analysis of Synchronous Buck Converter with Hysteretic Controller at High Slew-Rate Load Current Transients,” proceedings of HFPC99, pp. 55-69.
(d)
Fig. 15. Experimental test results of the transient response: (a) OSCONs plus ceramics; (b) the non-viable solution; (c) the all-ceramic solution, and (d) the load current step change.
VI.
REFERENCES
CONCLUSION
Future CPUs require tighter voltage regulation; therefore a smaller Rdroop is specified. To obtain a quality transient response, the VR output impedance is expected to be equal to the required Rdroop. In achieving the VR output impedance equal to Rdroop, OSCON capacitors are used along with ceramic capacitors. The number of OSCON capacitors must make the equivalent ESR equal to Rdroop and the ceramic capacitors are used to attenuate the ESL effect of the OSCON capacitors. In this solution, there is little to gain by pushing an increase in the switching frequency of the VR. Another solution is to use only ceramic capacitors. In this case, pushing the switching frequency to increase can reduce the number of ceramic capacitors needed, provided the control bandwidth is increased proportionally to the increase of the switching frequency. The two options for VR output capacitors are compared. The all-ceramic solution is better in terms of footprint area and cost when the switching frequency is beyond a certain value, and therefore provides an opportunity to deliver a more cost-effective VR solution to future processors.
[10] R. Miftakhutdinov, “Optimal Design of Interleaved Synchronous Buck Converter at High Slew-Rate Load Current Transients.” proceedings of IEEE PESC’01, pp. 1714-1718. [11] A. Rozman and K. Fellhoelter, “Circuit Considerations for Fast, Sensitive, Low Voltage Loads in a Distributed Power System,” proceedings of IEEE APEC’95, pp. 34-42. [12] D. Briggs, R. Martinez, R. Miftakhutdinov and D. Skelton, “A Fast, Efficient Synchronous-Buck Controller for Microprocessor Power Supplies,” proceedings of HFPC98. [13] P. Wong, F.C. Lee, Z. Zhou and J. Chen, “VRM Transient sSudy and Output Filter Design for Future Processors,” proceedings of IECON '98, pp. 410-415. [14] A. Waizman and C.Y. Chung, “Resonant Free Power Network Design Using Extended Adaptive Voltage Positioning (EAVP) Methodology,” IEEE Trans. Advanced Packaging, vol. 24, Aug. 2001, pp. 236-244. [15] R. Redl and N.O. Sokal, “Near-Optimum Dynamic Regulation of DC-DC Converters Using Feed-Forward of Output Current and Input Voltage with Current-Mode Control”, IEEE Trans. Power Electro, vol. 1, July 1986. pp. 181-192. [16] G. K. Schoneman and D.M. Mitchell, “Output Impedance Considerations for Switching Regulators with Current Injected control,” proceedings of IEEE PESC, 1987, pp. 324-335. [17] R.Redl, B.P. Erisman and Z. Zansky, “Optimizing the Load Transient Response of the Buck Converter,” proceedings of IEEE APEC’98, pp. 170-176. [18] K. Yao, Y. Meng, P. Xu and F.C. Lee, “Design Considerations for VRM Transient Response Based on the Output Impedance,” proceedings of IEEE APEC’02. [19] J. Wei, and F. C. Lee, “A Novel Soft-Switched High-Frequency High-Efficiency High-Current 12V Voltage Regulator Phase-Shift Buck Converter”, in Proc. IEEE Appl. Power Electron. Conf. (APEC), 2003, pp. 724-730. [20] C. Blake, R. Monteiro and A. Sawle, “Optimizing Gate Drive Voltage to Achieve over 85% Efficiency in a 4-Phase, 100A Voltage Regulator Module (VRM)”, proceedings of Intel Technology Symposium 2002.
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