Calculation of Output Voltage Ripple and Design ... - IEEE Xplore

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 61, NO. 3, MARCH 2014

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Calculation of Output Voltage Ripple and Design Considerations of SEPIC Converter Ebrahim Babaei, Member, IEEE, and Mir Esmaeel Seyed Mahmoodieh, Student Member, IEEE

Abstract—In this paper, a design method is proposed for finding the equivalent inductance and capacitance of the single-ended primary-inductor converter (SEPIC). The relations of the output voltage ripple (OVR) of the SEPIC converter are obtained in complete inductor supply mode–continuous conduction mode (CISMCCM), incomplete inductor supply mode-CCM (IISM-CCM), and IISM-discontinuous conduction mode (IISM-DCM). The maximum of OVR (MOVR) is investigated for a specified range of the input voltage and load resistance. This value of the MOVR is obtained for the minimum values of input voltage and load resistance. In this paper, the minimum values of the equivalent inductance and capacitance are calculated in obtaining the minimum value of the MOVR. One of the other performed studies in this paper is calculation of the switch peak current in CCM and DCM. In addition, the converter is designed based on the minimum values of the MOVR and stress of the switching current. Experimental and simulation results are used to prove the validity of the presented theoretical subjects. Index Terms—Complete inductor supply mode (CISM), continuous conduction mode (CCM), discontinuous conduction mode (DCM), incomplete inductor supply mode (IISM), output voltage ripple (OVR), single-ended primary-inductor converter (SEPIC), stress of switching current.

I. I NTRODUCTION

N

OWADAYS, the dc/dc converters are widely used in different applications. In some special applications such as military, aerospace, cranes, and precision instrumentation [1], the output voltage ripple (OVR) has to be maintained in an acceptable level to achieve superior performance [2], [3]. In addition to the aforementioned applications, the dc/dc converters are applied to tie the renewable energy to the utility [4], [5] and the speed control of adjustable motors [6]. Therefore, the quality of the output voltage has a special importance in these kinds of applications. In [6], the author has studied the speed control of a dc series motor by using a buck–boost converter by presenting a new control method. Also, the ripple of the input voltage and current of the motor was decreased by designing a proper PI controller. In [7], the authors have decreased the OVR of a buck converter by combining a resonant controller in parallel connection with a PID controller. The major disadvan-

Manuscript received April 30, 2012; revised October 25, 2012 and March 28, 2013; accepted April 4, 2013. Date of publication July 29, 2013; date of current version August 23, 2013. The authors are with the Faculty of Electrical and Computer Engineering, University of Tabriz, Tabriz 51664, Iran (e-mail: [email protected]; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2013.2262748

tages of the presented methods in [6] and [7] are the complexity of the system and its control method. In [8], the authors have investigated the OVR of a buck converter by classifying continuous conduction mode (CCM) and discontinuous conduction mode (DCM) by the critical inductance. In [9], a chaotic control method has been presented for decreasing the OVR and electromagnetic interference (EMI) of a buck converter. In [10], a new modified boost topology has been presented with some significant new features, such as reduced component current stress and continuous output current. The major disadvantage of this converter is the limited range of the voltage conversion ratio (M ). The allowable range of M for the presented method is 1 < M < 1.6. In [11], a different arrangement of a boost converter with an extra LC filter is presented to decrease the OVR. The major disadvantages of [11] are increasing the cost and complexity of the converter. Until now, the studies which have been done about the single-ended primary-inductor converter (SEPIC) are more about the control method, in order to decrease the switching losses by using soft switching [12], [13]. In [14], studies about the OVR in a SEPIC converter have been done. In [14], the authors have presented a modified topology of a SEPIC converter in order to decrease the OVR in CCM and DCM. The major disadvantage of this method is the high stress of switching voltage compared with the conventional SEPIC converter. Because of this disadvantage, the presented method in [14] is just applied in low voltages and high currents. The use of more power supply elements (inductor and capacitor) in [14] causes the increase of EMI. One of the other disadvantages of this method is the complexity of the converter and its control method. By developing CCM and DCM to complete inductor supply mode (CISM) and incomplete inductor supply mode (IISM) [3], the operational modes of the SEPIC converter are divided into three groups: CISM-CCM, IISM-CCM, and IISM-DCM. In this paper, the OVR of the converter is investigated by considering the stress of switching current and size of elements in all three operational modes. In dc/dc converters, the value of the OVR is determined by the values of the inductances and capacitances. In addition, the value of the switch peak current (SPC) is determined by the values of the inductances. In addition to the values of the inductances and capacitances, the values of the input voltage and load resistance can affect the values of the OVR and SPC. In this paper, the aim is to calculate the values of inductances and capacitances in such a way that the values of maximum of OVR (MOVR) and SPC are minimized. In this paper, first the different operational modes of the SEPIC converter are introduced. Then, the critical inductances between these operational

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The following is valid if the SEPIC converter operates in CCM: D=

Vo . Vo + Vi

(4)

Considering (1) and (2), and (4), the values of LCe and LKe can be explained as follows, respectively: Fig. 1. Power circuit of the SEPIC converter.

modes are calculated. After this, the relations of the OVR, MOVR, and stress of switching current are obtained as functions of different quantities of the converter. In addition, a design method is given for calculating the minimum values of inductances and capacitances to guarantee the minimum values of the MOVR and SPC. It is important to note that the presented method can be applied for different kinds of dc/dc converters. Finally, the experimental and simulation results are presented to reconfirm the validity of the proposed theoretical subjects. II. O PERATIONAL M ODES AND C ALCULATION OF E QUIVALENT C RITICAL I NDUCTANCES The topology of the SEPIC converter is shown in Fig. 1. The operational modes in a SEPIC converter are generally classified in CCM and DCM. The borderline between these two operational modes is specified by the equivalent critical inductance LCe . Considering the load current (Io ) and the sum of the minimum currents of L1 (ILV 1 ) and L2 (ILV 2 ), CCM is divided into two operational modes, namely, CISM and IISM. The borderline of these two operational modes is determined by critical inductance LKe . The DCM just contains an interval of IISM. Therefore, the SEPIC converter contains three operational modes. The waveforms of different quantities of the converter in different operational modes are shown in Fig. 2. In CISM-CCM operational, the sum of the minimum currents of the inductors (ILV 1 + ILV 2 ) is more than Io , and also, the equivalent inductance Le = L1 L2 is more than LKe . In IISMCCM operational, LCe < Le < LKe and ILV 1 + ILV 2 < Io are valid. In IISM-DCM operational, ILV 1 + ILV 2 = 0 and Le < LCe are valid. Considering Fig. 2, it is illustrated that the equivalent critical inductances between CCM and DCM (LCe ) and between CISM and IISM (LKe ) are obtained by considering ILV 1 + ILV 2 = 0 and ILV 1 + ILV 2 = Io , respectively LCe

RL (1 − D)2 = 2f

(1)

LKe

RL (1 − D)2 . = 2f D

(2)

In (1) and (2), f is the switching frequency, and D is the duty cycle of the converter which is defined as follows: D=

Ton . T

Considering 0 < D < 1, (1) and (2), LKe > LCe is valid.

(3)

LCe =

Vi2 RL 2f (Vi + Vo )2

(5)

LKe =

Vi2 RL . 2f Vo (Vo + Vi )

(6)

III. OVR C ALCULATION The OVR is one of the effective parameters in designing a dc/dc converter. In dc/dc converters, the circuit elements should be designed in such a way that the OVR has the minimum value. In this section, the analysis of the OVR is carried out in all operational modes, and the effect of each of the electrical parameters on OVR is investigated. A. Calculating OVR in CISM-CCM According to Fig. 2(a), the OVR in this operational mode is obtained by integrating iC2 during Ton as follows: VP P = VCP 2 − VCV 2

1 =− C2

Ton iC2 (t)dt

(7)

0

where VCP 2 and VCV 2 are the maximum and minimum values of the output voltage, respectively. In time interval Ton , iC2 is equal to iC2 (Ton ) = −Io .

(8)

Assuming a high value for capacitor C2 , the value of Io can be considered constant. Applying (3) and (8) in (7), we have -CCM = VPCISM P

DT Io . C2

(9)

Applying (4) in (9), considering T = 1/f and Vo = RL Io , the value of the OVR in this operational mode is -CCM = VPCISM P

Vo2 . RL C2 f (Vi + Vo )

(10)

Considering (10), it is illustrated which OVR in the CISMCCM is independent of the values of L1 and L2 . Meanwhile, the value of the OVR in this operational mode has a reverse relation with the values of input voltage and load resistance. In other words -CCM ∂VPCISM P LKe,min If LCe,max > LKe,min , the converter will have five operational regions. If Le < LCe,min , the converter operates in IISMDCM (region 1). The minimum value of VP P 1,max is obtained for Le = LCe,min . Therefore, by applying (40) in (35), the following is valid: (2Vo + Vi,min )2 Vo . 4f RL,min C2 (Vo + Vi,min )2

(64)

In CCM, according to (57) and (64), for Le > LKe,min , the value of the MOVR is minimum, and it is independent of Le . In other words, by increasing the value of Le , the value of the MOVR remains constant, and it is minimum. In DCM, for Le = LCe,min , the value of the MOVR is minimum.

One of the other effective parameters in designing a dc/dc converter is the stress of the switching current. The converter should be designed in such a way that it contains the minimum stress of the switching current. Considering Fig. 1, when switch S is on, the current passing through the switch is equal to iS (t) = iL1 + iL2 (t).

(65)

According to Fig. 2, SPC in CCM and DCM is at t1 , and it is equal to ISP = ILP 1 + ILP 2

(66)

(58)

If LCe,min < Le < LKe,min , one section of the operational region of the converter will be in IISM-DCM, and the other section will be in IISM-CCM. The maximum and minimum values of VP P 2,max are obtained for Le = LCe,min and Le = LKe,min , respectively. Considering (22), (35), (40), and (42), the following equations are obtained: -DCM = max VPIISM P 2,max

(2Vo + Vi,min )2 Vo 4f RL,min C2 (Vo + Vi,min )2

(59)

-CCM = min VPIISM P 2,max

Vo2 . RL,min C2 f (Vi,min + Vo )2

(60)

If LKe,min < Le < LCe,max , one section of the operational region of the converter will be in IISM-CCM, and the other section will be in CISM-CCM. The maximum and minimum values of VP P 3,max are as follows: -CCM = max VPIISM P 3,max

Vo2 RL,min C2 f (Vi,min + Vo )

-CCM = min VPCISM P 3,max

Vo2 . (62) RL,min C2 f (Vi,min + Vo )

(61)

For LCe,max < Le < LKe,max (region 4) and Le > LKe,max (region 5), the converter will operate in CISM-CCM, so -CCM = V CISM-CCM = VPCISM P 4,max P P 5,max

= VP P 4,max = VP P 5,max .

V. C ALCULATION OF S TRESS OF S WITCHING C URRENT

VP P 1,max > VP P 2,max > VP P 3,max > VP P 4,max

-DCM = min VPIISM P 1,max

VP P 1,max > VP P 2,max > VP P 3,max

(56)

Considering (48), (52), and (54)–(56) leads to

= VP P 5,max .

Considering (58)–(63) leads to

Vo2 . RL,min C2 f (Vi,min + Vo ) (63)

where ISP is the SPC. CCM ) Considering (4), (21), and Vo = RL Io , SPC in CCM (ISP is obtained as follows: CCM = ISP

Vo (Vi + Vo ) Vo Vi . + RL Vi 2f Le (Vi + Vo )

(67)

Equation (67) shows that SPC has a reverse relation with the values of Le and RL . Considering the specific values of Vi and RL , if Le > LCe , the converter operates in CCM, so the maximum value of SPC is obtained for Le = LCe , and by applying (5) in (67), the maximum value of SPC is obtained as follows: CCM ISP,max =

2Vo (Vi + Vo ) . RL Vi

(68)

With a similar analysis, SPC in DCM is equal to the sum of (31) and (32), so by considering (34), SPC in DCM is obtained as follows: 2 DCM . (69) ISP = Vo R L f Le Considering (69), SPC in DCM has a reverse relation with Le and RL . For specific values of Vi and RL , if Le < LCe , the converter operates in DCM, so the minimum value of SPC is obtained for Le = LCe . Hence, by applying (5) in (69), the minimum value of SPC can be calculated as DCM ISP,min =

2Vo (Vi + Vo ) . RL Vi

(70)

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addition, the stress value of the switching current will be high, so the following should be valid: Le < LCe,min =

2 Vi,min RL,min . 2f (Vi,min + Vo )2

(73)

Considering (72) and (73) leads to LCe,min < Le < LKe,max .

Fig. 5.

Variations of SPC in different operational modes versus Le .

Comparing (68) and (70) leads to DCM CCM ISP,min = ISP,max .

(71)

Considering (71), SPC in DCM is more than that in CCM. Fig. 5 shows the variations of SPC versus the equivalent inductance for specific values of Vi and RL and for a constant switching frequency. As it is observed in Fig. 5, SPC is maximum in DCM, and it is low to some extent in CCM. In both DCM and CCM, the value of SPC has a reverse relation with the value of Le .

The OVR and stress of switching current are two effective parameters in designing a dc/dc converter. The value of the OVR is determined by the values of L1 , L2 , C2 , and the switching frequency. The stress value of the switching current is also determined by the values of L1 , L2 , and the switching frequency. By increasing the switching frequency, the OVR and stress of the switching current can be decreased. However, in practice, there is limitation in applying high frequency. The other method for decreasing OVR and the stress of the switching current is increasing the equivalent inductance. As it is expressed in Section IV, the worst operational condition (MOVR) is for the minimum values of input voltage and load resistance (Vi,min and RL,min ). Considering which stress value of the switching current has a reverse relation with the value of RL , in the worst operational condition, the stress value of the switching current is high. The proposed method in this section is a desired method for achieving the minimum value of the MOVR considering the minimum stress of the switching current. As it is expressed in Section III, OVR is minimum in CISMCCM and is independent of Le . If Le > LKe,max , for all possible values of Vi and RL , the converter will operate in CISM-CCM. Considering (43), using a high value for Le , the size of the elements of the converter increases, so selecting a high value for Le is not proposed. Hence Le < LKe,max

2 Vi,max RL,max . = 2f Vo (Vo + Vi,max )

According to (57) and (64), it is observed that, for Le > LKe,min , the value of the MOVR is independent of Le . It means that, by increasing the equivalent inductances, the MOVR does not vary. Also, the stress of the switching current of the converter is low because it operates in CCM. Therefore, the minimum value of the equivalent inductance in order to ensure facing with minimum MOVR in the worst operational conditions (MOVR) is LKe,min as follows: Le,min = LKe,min =

(72)

If Le < LCe,min , the converter will operate in IISM-DCM (for all values of Vi and RL ), but as expressed in Section III, the OVR will be high, and it increases by decreasing Le . In

2 Vi,min RL,min . 2f Vo (Vo + Vi,min )

(75)

According to (63), MOVR is equal to VP P,max =

Vo2 . RL,min C2 f (Vi,min + Vo )

(76)

Considering (76), the minimum value of C2 is as follows: C2,min =

VI. D ESIGN C ONSIDERATIONS

(74)

Vo2 . RL,min VP P,max f (Vi,min + Vo )

(77)

By considering the equivalent series resistance (ESR) effect of the output capacitor, the minimum value of the output capacitor in (77) varies as follows: C2,min =

Vo2

(78)

(Vo + Vi,min )(VP P,max − λ)RL,min f

where λ of the aforementioned relation is equal to 2RESR Vo2 . RL,min Vi,min

λ=

(79)

RESR in the aforementioned relation is the resistance value of ESR. In designing the elements of the converter, calculating the value of C1 is needed in addition to the values of L1 , L2 , and C2 . The value of the voltage ripple of capacitor C1 is obtained by integrating iC1 in time interval Toﬀ as VP P,C1 =

Vo2 . RL f C1 (Vi + Vo )

(80)

As shown in (80), the value of the voltage ripple of capacitor C1 has a reverse relation with the values of Vi and RL , so the MOVR of capacitor C1 can be expressed as follows: VP P,C1,max =

Vo2 . RL,min f C1 (Vi,min + Vo )

(81)

Considering (81), the minimum value of capacitor C1 is equal to C1,min =

Vo2 RL,min f VP P,C1,max (Vi,min + Vo )

.

(82)

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VII. E FFICIENCY OF S EPIC C ONVERTER One of the other significant parameters of designing a converter is its efficiency. Considering which one of the objects of this paper is designing converter inductance to achieve the minimum MOVR and for Le > LKe,min , the value of the MOVR is minimum and independent of the inductance value, so in this section, the effect of inductance increase on converter efficiency is investigated. The efficiency of the SEPIC converter is equal to η=

P out Pout + Ploss

(83) Fig. 6.

where Ploss is the total loss of the converter as follows: Ploss = PS + PD + PL + PC1 + PC2

(84)

where PS , PD , PLe , PC1 , and PC2 are the losses of the switch and diode, the ESR of the inductances, and the ESR of capacitors C1 and C2 , respectively. According to Fig. 1, the switch loss is equal to 2 PS = PrS + 0.5PSW = rS IS,rms + 0.5f Co (Vo + Vi )2 (85)

where PrS , PSW , rS , IS,rms , and Co are the switch conduction loss, the switching loss, the ON-state resistance of the switch, the rms value of the switch current, and the capacitor capacity of the switch output, respectively. By calculating each of the parameters of the aforementioned relation, the switch loss is expressed as follows: D(1 − D)2 Vo2 DIo2 f Co Vo2 + . (86) + PS = rS 12L2e f 2 (1 − D)2 2D2 The diode loss is equal to PD = VD Io + rD

Vo2 (1 − D)3 Io2 + 12L2e f 2 1−D

(87)

where VD is the ON-state voltage drop of the diode and rD is the diode conduction resistance. The loss of equivalent inductance is obtained by 2 V (1 − D)2 Io2 + PL = rL(IL1 + IL2 )2rms = rL o (88) 12L2e f 2 (1 − D)2 where rL is the ESR of the inductances. The ESR losses of capacitors C1 and C2 are expressed as follows, respectively: 2 PC1 = rC1 IC1,rms 2 Vo (1 − D)3 Vo2 D(1 − D)2 DIo = rC1 + + (89) 12L1 f 2 12L2 f 2 1−D 2 V (1 − D)3 DIo2 2 = rC2 o + PC2 = rC2 IC1,rms (90) 12L2e f 2 1−D

where rC1 and rC2 are the ESR losses of capacitors C1 and C2 , respectively. Calculating the converter loss using (86)–(90), the converter efficiency can be calculated using (83). Equations (86)–(90)

Effect of inductance on the converter efficiency.

show that the converter loss decreases by increasing the value of the inductance. In other words, the converter efficiency increases. Therefore, by considering Le > LKe,min , in addition to obtaining the minimum of the MOVR which is independent of inductance, the converter efficiency also increases. Fig. 6 shows the converter efficiency versus the equivalent inductance for different ESR values of the inductances. In this figure, the converter efficiency is calculated for Vi = 80 V, Vo = 150 V, f = 15 kHz, RL = 50 Ω, VD = 0.7 V, Co = 100 PF, rS = 50 mΩ, and rC1 = rC2 = rD = 20 mΩ. According to the figure, it is observed that, by increasing the inductance value, the converter efficiency also increases. VIII. T HEORETICAL A NALYSIS AND E XPERIMENTAL AND S IMULATION R ESULTS In order to prove the theoretical subjects presented in the previous sections, the SEPIC converter which is shown in Fig. 1 is simulated in a computer. In addition, for reverification of the theoretical analysis, experimental and simulation (using PSCAD/EMTDC software) results have been presented. For better detection, the experimental and simulation results are presented for steady state. The transistor (switch S) and diode (D) of the prototype are MJ13005 and MUR460, respectively. The C1 and C2 capacitors are composed of series and parallel connections of some 40 μF/250 V electrolytic, 1 μF/250 V polyester, and 100 nF/400 V ceramic. The L1 and L2 inductors are composed of series and parallel connections of some 500-μH air-gapped ferrite-type core using multilayer wires (Litz wire) for winding. The 89C52 microcontroller by ATMEL Company has been used to generate the switching pattern. Tektronix TDS 2024B four channel digital storage oscilloscope is used for measurements in the laboratory. The major parameters of the converter are shown in Table I. According to (40)–(43), (77), (82), and Table I, the values of the inductances and capacitances are expressed as shown in Table II. Fig. 7(a) shows the variation of the OVR versus Le for different values of Vi and RL in buck mode. As shown in this figure, the values of the OVR in IISM-DCM and IISM-CCM decrease by increasing the value of Le . In CISM-CCM, the value of the OVR is independent of the value of Le . Also, it is observed that, for low equivalent inductances, the converter is in IISM-DCM. Considering Fig. 7(a), the value of the OVR in IISM-DCM is independent of Vi . Also, in this operational mode, the OVR value has a reverse relation with the value of

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TABLE I PARAMETERS OF C ONVERTER

TABLE II VALUES OF I NDUCTANCES AND C APACITANCES

RL . Fig. 7(a) shows that the values of the OVR in IISM-CCM and CISM-CCM have a reverse relation with the values of Vi and RL . It is observed that the maximum value of the OVR occurs for Vi,min and RL,min . Fig. 7(b) shows the variation of the OVR versus Vi for RL,min = 50 Ω and different values of Le in buck mode. As shown in this figure, for Le = 0.4 mH < LCe,min , the converter in the whole operational region is in IISM-DCM. Therefore, the value of the OVR is independent of the value of Vi . For high values of Le , the converter operates in IISM-CCM and CISM-CCM. By increasing the values of Le and Vi , the value of the OVR decreases. Considering which MOVR is obtained for Vi,min and RL,min , for Le > LKe,min = 1.27 mH, the value of the MOVR is independent of the value of Le and has its minimum value (VP P,max = 1.2 V). Therefore, this subject proves the validity of the presented subjects in Section IV. Fig. 7(c) shows the variations of the OVR versus RL for Vi,min = 80 V and different values of Le . As shown in this figure, the value of the OVR decreases as the value of RL increases. Also, it is observed that the value of the OVR decreases by increasing the value of Le . As shown in this figure, for this condition, the MOVR does not change, and its value is equal to 1.2 V. In other words, for Le > LKe,min = 1.27 mH, the MOVR is independent of the value of Le . This subject proves the validity of the presented subjects in Section IV. Fig. 8 shows the variation of SPC versus Le for RL,min and RL,max . This figure shows that the SPC decreases by increasing the value of Le . In DCM, SPC is high, and it is low in CCM. In addition, the SPC decreases in both DCM and CCM as the value of RL increases. Hence, for specific values of RL,min and Le , SPC has the most value of itself. This subject proves the validity of (71).

Fig. 7. Variation of the OVR. (a) Versus the equivalent inductance for different values of Vi and RL . (b) Versus Vi for different values of Le . (c) Versus RL for different values of Le .

Fig. 8. SPC versus equivalent critical inductance for RL,min and RL,max .

As shown in Figs. 7 and 8, the experimental and simulation results have good agreement with the results of theoretical analysis, and they reconfirm the theoretical analysis. Figs. 9 and 10 show the experimental results of the SEPIC converter in boost mode for Vi,min = 80 V and RL,min = 50 Ω (MOVR condition). As shown in Fig. 9, by selecting

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R EFERENCES

Fig. 9. Experimental results of the SEPIC converter in boost mode at the worst operational conditions (RL,min , Vi,min ) for Le = 0.67 mH. (a) Current of capacitor C2 . (b) OVR.

Fig. 10. Experimental results of the SEPIC converter in boost mode at the worst operational conditions (RL,min , Vi,min ) for Le = 1.2 mH. (a) Current of capacitor C2 . (b) OVR.

L1 = 2 mH and L2 = 1 mH because Le = 0.67 mH > LKe,min = 0.31 mH, M OV R = 3 V (%2 Vo ). According to Fig. 10, for L1 = 2 mH and L2 = 3 mH, by increasing Le to 1.2 mH, the value of the MOVR does not change, and it is equal to 3 V. Hence, it can be concluded that, for Le > LKe,min , the MOVR is independent of the value of Le . Expressing this subject proves the validity of the subjects presented in Section IV. It should be noted that, in Figs. 9(b) and 10(b), the OVR is just presented and the dc component of the output voltage is eliminated. IX. C ONCLUSION The operational modes of the SEPIC converter are divided into CISM-CCM, IISM-CCM, and IISM-DCM. In CCM, with constant values of load, capacitor capacity, and switching frequency, the OVR is not always independent of the inductance value. In CISM-CCM, its value is minimum and also independent of the equivalent inductance. In IISM-CCM and IISM-DCM, the OVR is more and increases by decreasing the equivalent inductance value. In CCM, the stress of the switching current is less than its value in DCM and has a reverse relation with the values of Le and RL . In Le,min = LKe,min condition, not only a minimum value of the MOVR is obtained, but also a low value for the stress of the switching current is produced. In Vi = Vi,min and RL = RL,min conditions, the minimum value of the equivalent critical inductance between CISM and IISM is obtained, and in these conditions, the minimum value of the MOVR is generated. It is important to note that, for Le ≥ LKe,min , the value of the MOVR is independent of the value of the equivalent inductance. In addition, by increasing the inductance value, the converter efficiency also increases.

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Ebrahim Babaei (M’10) was born in Ahar, Iran, in 1970. He received the B.S. and M.S. degrees in electrical engineering (first class honors) from the Department of Engineering, University of Tabriz, Tabriz, Iran, in 1992 and 2001, respectively, and the Ph.D. degree in electrical engineering from the Department of Electrical and Computer Engineering, University of Tabriz, in 2007. In 2004, he joined the Faculty of Electrical and Computer Engineering, University of Tabriz, where he was an Assistant Professor from 2007 to 2011 and where he has been an Associate Professor since 2011. He is the author of more than 210 journal and conference papers. His current research interests include the analysis and control of power electronic converters, matrix converters, multilevel converters, FACTS devices, power system transients, and power system dynamics.

Mir Esmaeel Seyed Mahmoodieh (S’13) was born in Tabriz, Iran, in 1984. He received the B.S. degree in power engineering from the Department of Engineering, Islamic Azad University of Ardabil, Ardabil, Iran, in 2008 and the M.S. degree from the Department of Engineering, Islamic Azad University of Ahar, Ahar, Iran, in 2011. He is currently working toward the Ph.D. degree in power engineering at Bu-Ali Sina University, Hamedan, Iran. His major fields of interest include the analysis, control, and modeling of power electronic converters.