A CMOS Image Sensor using Variable Reference Time Domain Encoding M. K. Law and A. Bermak Department of Electrical and Computer Engineering The Hong Kong University of Science and Technology Clear Water Bay, Kowloon, Hong Kong SAR Email:
[email protected],
[email protected]
Abstract— In this paper, a Variable Reference Time Domain Encoding CMOS image sensor is presented. The time domain encoding vision sensor is known to suffer from slow conversion time, especially at low level of illumination. This is due to limited photocurrent generated to discharge the photodiode junction voltage to the reference voltage. A variable referencing scheme is proposed so that the reference voltage will be modulated and bounded by a specified deadline. The pixel consists of a photodiode, an analogue comparator, an 8-bit SRAM, a SR latch, and occupies an area of 32µm × 35µm, with a fill-factor of 12.6% using a 0.35µm CMOS process. Simulation results show that signal conversion can be achieved by using pre-defined threshold 1 voltages. By using four levels of reference voltage and 10 of the original conversion time required by the original time domain encoding, over 70% reduction in total integration time can be achieved.
I. I NTRODUCTION The last decade has witnessed a very rapid emergence of CMOS imaging technology as the technology of choice for portable digital imaging products. Standard CMOS fabrication process has enabled the concept of a camera-on-chip as a result of reduced manufacturing costs, compactness, and low power operation [1]. With the reduction in supply voltage in advanced CMOS processes, traditional voltage mode operation is becoming one of the major limitations in CMOS imager design. Time domain encoding [2]–[4] can provide viable solution as the operation is based on spiking rather than voltage encoding. However, time domain encoding still suffers from the disadvantage of slow conversion time. This paper presents a variable referencing scheme that can effectively reduce the conversion time, while maintaining the high dynamic range featured in time domain encoding. The reference voltage is modulated upon reaching pre-defined deadlines so that the corresponding signal can be converted more readily. The approach is adaptive to different illumination intensities. This paper is organised as follows. Section II first introduces the original time domain encoding algorithm, then describes the proposed variable reference time domain algorithm with operation principle explained. Section III shows the image sensor architecture that implements the algorithm using four reference voltage levels with the corresponding simulation results. Section IV outlines the conclusion.
II. A LGORITHM A. Original Time Domain Encoding The time domain encoding technique as shown in Fig. 1 and reported in [2]–[4], utilizes the linear discharge behavior of the photodiode in determining the light intensity. This is done by measuring the time required for the photodiode junction voltage Vn to reach a pre-defined reference voltage Vref . By assuming constant junction capacitance, the integration time T can be expressed as a function of the photocurrent Ipd : T =
α (Vdd − Vref ) × Cpd ≃ Ipd + Idc Ipd
(1)
where Vdd is the supply voltage, Cpd , Idc are the photodiode junction capacitance and dark current.
Fig. 1.
Pixel schematic
Equation (1) shows that there is an inverse relationship between the conversion time and the amount of photocurrent. A control circuit is designed to quantize the photocurrents into digital values using a timer which decrements the data provided to the SRAM. The primary clock tpri is defined as the time required to resolve the maximum photocurrent Imax and the next photocurrent Imax − ∆I, as: tpri = (
2b
1 (Vdd − Vref ) × Cpd 1 − b ) −2 2 −1 ∆I
(2)
where ∆I and b are the photocurrent quantization difference and number of bits in the memory, respectively.
This relationship, as shown graphically in Fig. 3, can be expressed as: tconv(n) × ∆Vref (n) ∆Vr(n+1) = tblank + tsum(n+1) =
Fig. 2. Relationship between photocurrent and integration time. Note that the conversion time, which distinguishes one photocurrent level to another, increases as photocurrent level decreases.
The blanking period tblank is defined as the time required to elapse before the maximum detectable photocurrent reaches the threshold, defined by: tblank =
(Vdd − Vref ) × Cpd (2b − 1) × ∆I
(3)
From equation (2) and (3), we can write: tblank = (2b − 2) × tpri
(4)
The conversion time, tconv , is a measure of the time required to quantize successive photocurrent levels, and is governed by the following equation: tconv(n) = (
tconv(n) × ∆Vref (n) tint(n+1)
(7)
where Vr(n+1) is the residual voltage at count (n + 1), ∆Vref (n) is the difference in reference voltage at count n, and tconv(n) and tint(n+1) are the conversion time from count n to (n + 1) and the total integration time for count (n + 1), respectively. Notice the fact that: tsum(n+1) = tsum(n) + tconv(n) =
n X
tconv(i)
(8)
i=1
By using equation (4), (6) and (8), the first term of equation (7) can be reduced to function of n for fixed b, and is independent of the primary clock tpri . It can then be concluded that the residual voltage at conversion count n is given solely by the value n and the term ∆Vref (n) . Therefore, at a particular time corresponding to the conversion count n, the value of ∆Vr(n+1) can be exactly determined for known value of ∆Vref (n) . A precise step increase in reference voltage can then be determined. This algorithm is adapative as the integration time can be established independently of the maximum photocurrent, which depends on the primary clock, tpri .
1 1 (Vdd − Vref ) × Cpd − ) (5) 2b − (n + 1) 2b − n ∆I
where tconv(n) is the conversion time from count n to (n + 1). From equation (2) and (5), we can write: tconv(n) = tpri ×
(2b
(2b − 1)(2b − 2) − (n + 1))(2b − n)
(6)
Note that tblank and tconv can be expressed as a multiple of the primary clock tpri . In this case, the dynamic range can then be adaptively adjusted by varying the primary clock, which represents the difference between successive photocurrent levels ∆I, to achieve high dynamic range. However, due to the inversely proportional property in equation (1), a considerable amount of time is required to convert the signals at low photocurrent levels, as shown in Fig. 2. B. Variable Reference Time Domain Encoding The proposed variable reference time domain encoding technique is presented to speed-up the sensing process, with the concern of simple and robust hardware implementation. Let Iph(n) and Iph(n+1) be two consecutive photocurrents, with n denoting the nth level of photocurrent. By the time when Iph(n) reaches the threshold voltage, the Iph(n+1) photocurrent would not have reached the threshold and there is a residue voltage that is required to be discharged before Iph(n+1) also reaches the threshold, denoted by ∆Vr(n+1) .
Fig. 3.
Fig. 4.
Relationship between residual voltage and conversion count
Quantization error due to excessive increase in reference voltage
By applying different levels of reference voltage at different conversion counts, a significant reduction in integration time can be achieved. Notice that the increase in reference voltage cannot be larger than the corresponding residual voltage. Otherwise, quantization error will occur, which can be illustrated by Fig. 4. In fact, it should be strictly less than ∆Vr(n+1) in 1 of the order to eliminate quantization errors. A fraction of 10 original conversion time required by the original time domain encoding is selected for performing simulations.
Fig. 5. Relationship between the original time domain encoding and optimal variable reference time domain encoding. Note that the fixed number of reference voltages should be modulated at the latest conversion count to achieve optimal integration time.
C. Optimal integration time In order to reduce the complexity of the control circuit and the bandgap reference, we perform simulations with four levels of reference voltage. The optimal integration time can then be determined with this constraint. Fig. 5 shows the results of modulating the reference voltage at two different conversion counts m and n with m < n. As the photocurrent generated decreases when conversion count increases, the residual voltage that corresponds to conversion count m is therefore less than that of conversion count n. This is clearly evidenced from equation (4), (6) and (8), as we can write: tint(n+1) = tblank + tsum(n+1) = tpri (2b − 2) +
n X
III. I MAGE S ENSOR D ESIGN AND S IMULATION R ESULTS To verify the proposed algorithm performance, an image sensor has been designed using standard CMOS 0.35µm technology. The image sensor is composed of a 128x128 sensor array, a control circuit, a bandgap reference, row buffers, row and column decoders and sense amplifiers.
tconv(i)
i=1
= tpri (2b − 2)(1 +
n X i=1
=
(2b
(2b − 1) ) − (i + 1))(2b − i)
tpri (2b − 2)(2b − 1) 2b − (n + 1)
(9)
From equation (6), (7) and (9), we obtain: ∆Vr(n+1) =
∆Vref (n) , n ∈ {1, 2b − 2} 2b − n
(10)
It can be seen from equation (10) that ∆Vr(n) increases as n increases. Notice that, as illustrated in Fig. 5, the total integration time is solely determined by the least photocurrent level. This implies that the larger the reference voltage for determining the least photocurrent level, the faster the total integration time. In other words, the reduction in integration time will be increased if we modulate the reference voltage at a later stage. Therefore, in order to obtain the optimal integration time, the reference voltage modulation should be performed at the latest possible conversion count in a consecutive manner. In particular, for 2b photocurrent quantization levels with decreasing conversion counts, the three extra reference voltage levels, excluding the one at the beginning corresponding to conversion count (2b − 1), should be modulated at conversion count 3, 2 and 1.
Fig. 6.
Bandgap reference schematic
The bandgap reference circuit as shown in Fig. 6 is implemented using the basic bandgap architecture with an output amplifier to provide a reference higher than the bandgap voltage. A resistive output chain is implemented to provide four levels of reference voltages. The output voltage accuracy is achieved by precise resistor matching during layout. The settling time requirement can be easily met as the conversion time at low illumination levels are quite long (in the order to milli-second). The reference voltages are modulated by the control circuit as shown in Fig. 7. It will generate different control signals to modulate the reference voltage upon reaching pre-defined deadlines. It also provides the conversion count signals in gray code to individual pixels after buffering. The reference voltage is switched at the bandgap reference instead of at each pixel in order to eliminate the problems of extra circuitry and excessive switching at the pixel level. Each pixel is composed of a photodiode, an analogue comparator, a SRlatch, an 8-bit SRAM and buffers. The layout of the pixel is shown in Fig. 8, occupying a silicon area of 32µm × 35µm, with a fill-factor of 12.6%.
Lookup Table
Blank Counter
Digital Comparator
Gray Counter Variable Clock
Clock
Binary Counter
Fig. 7.
Fig. 8.
Control Signals
Reset
Simplified control circuit schematic
Pixel layout of 32µm × 35µm using 0.35µm CMOS technology
Performance of the proposed variable reference algorithm was examined using standard 0.35µm CMOS technology. A 4-level reference voltage scheme was implemented and simulated. Reference voltage modulation was performed at the lowest conversion count to achieve the optimal integration time. The result, including the integration cycle and the memory read cycle, is shown in Fig. 9(a). As can be seen from the figure, the threshold voltage is modulated upon reaching the pre-determined conversion count and the corresponding pixel is reset asynchronously after reaching the threshold. The memory read cycle reads out the complemented gray code stored in the corresponding on-pixel SRAM, as shown in Fig. 9(b). The result shows that by modulating the reference voltage 1 at the latest conversion count and using 10 of the conversion time required by the original time domain encoding, over 70% of total integration time can be reduced. IV. C ONCLUSION The approach of Variable Reference Time Domain Encoding for CMOS image sensor design is presented, in which SNR is traded for reduced integration time. Simulation results confirm 1 of that over 70% reduction in integration time by using 10 the original value can be achieved by performing a four level threshold voltage modulation. Futher reduction is possible by using more levels of reference voltage, but will result
Fig. 9. Simulation result showing (a) integration cycle and memory read cycle (b) pixel memory complemented gray code content.
in increased circuit implementation complexity. This concept of variable reference time domain encoding was validated through full post layout simulation using 0.35µm CMOS technology. V. ACKNOWLEDGMENT The work described in this paper was supported by the Research Grant Council of HK SAR, China (Projects No 610405 and HKUST6148/03E). R EFERENCES [1] B.S. Carlson, Comparison of modern CCD and CMOS image sensor technologies and systems for low resolution imaging, IEEE Sensors Proceedings, Vol. 1, pp. 171−176, Jun. 2002 [2] A. Kitchen, A. Bouzerdoum and A. Bermak, Time domain analogue to digital conversion in a digital pixel sensor array, Electronic Design, Test and Applications, DELTA, pp. 108−122, Malaysia, Jan. 2004 [3] A. Kitchen, A. Bermak, A. Bouzerdoum, PWM digital pixel sensor based on asynchronous self-resetting scheme, IEEE Electron Device Letters, Vol. 25, Issue 7, pp. 471−473, Jul. 2004 [4] A. Bermak, Conversion time analysis of time domain digital pixel sensor in uniform and non-uniform quantizers, Fifth International Workshop on System-on-Chip for Real-Time Applications, pp. 172−175, Jul. 2005 [5] J. Doge, G. Schonfelder, G. T. Streil, and A. Konig, An HDR CMOS image sensor with spiking pixels, pixel-level ADC, and linear characteristics, Circuits and Systems II, IEEE Transactions on Analog and Digital Signal Processing, Vol. 49, pp. 155−158, Feb. 2002
