and $, are user controllable parameters. The use of eqn. 1 results in force components at frequencies no,, 2oRFk no,, n = 0, 1 , 2. We monitor the probe deflection at or using a lock-in amplifier, which is given by
Az(w,)
Y
Q A2 da z C -[A
-
Pk;
V ,cos($p - 4c)]Kcos(w,t) (2)
By adjusting A and the phase $, so that the deflection Az(o,)is nulled, the circuit signal amplitude and phase, V, L & can be determined. By using a nulling method, knowledge of values for aCplaz, Q, and k are not required to accurately measure V, L Cp,. This eliminates the need for complex calibration and accurate probe positioning. Further, since the method is independent of Cp the measurement of passivated circuits is possible.
Discussion: The scanning probe based method enables sirnultane-
ous submicrometre resolution imaging and non-invasive vectorvoltage measurements. Tests performed at lOGHz on a coplanar waveguide transmission line using known applied vector signals V, .L,$cindicate that our current probe has a 20dB dynamic range w t h a 20mV amplitude and a 3” phase resolution. The probe-circuit coupling C, has been shown to be < 1 fF [4]. This would yield a load of only 15ka at 1OGHZ. Acknowledgment: The author thanks B. Beggs of Nortel Networks for providing the phase shifter and the Natural Sciences and Engineering Research Council of Canada and Micronet.
0 IEE 1999
6 July 1999 Electronics Letters Online No: 19991154 DOI: 10.1049/el:19991154 G.E. Bridges (Department of Electrical and Computer Engineering, University of Manitoba, Winnipeg, R3T 5 V6, Cunadu)
E-mail:
[email protected]
References 270f 15mVppL120+ 6” OZAKI, K., SEKIGUCHI, H., WAKANA, s., GOTO, Y., UMEHARA, Y., and MATSUMOTO, J.: ‘Novel optical probing system with submicron
spatial resolution for internal diagnostics of VLSI circuits’. Proc. IEEE Int. Test Conf., Washington, 1996, pp. 269-275 THONG, J., (Ed.): ‘Electron beam testing technology: microdevices, physics, and fabrication technologies’ (Plenum, New York, 1993) LAI, R.K., HWANG, J.-R., and NEES, J.: ‘A fiber-mounted, micromachined photoconductive probe with 15 nV/Hz”* sensitivity’, Appl. Phys. Lett., 1996, 69, pp. 1843-1845 HOU, A S , NECHAY, B.A., HO, F., and BLOOM, D.M.: ‘Scanning probe microscopy for testing ultrafast electronic devices’, Opt. Quanzurn Electron., 1996, 28, pp. 819-841 BRIDGES, G.E., NORUTTUN, D., SAID, R.A., THOMSON, D.J., LAM, T., and QI, R.: ‘Non-contact probing of high speed microelectronics using electrostatic force sampling’, J. Vac. Sei. Technol. A , 1998, 16, pp. 830-833 LEYK, A., and KUBALEK, E.: ‘High spatially resolved MMlC internal millimetre-wave measurements of sinusoidal signals by high frequency electric force microscope-testing’, Electron. Lett., 1998, 34,pp. 196-197 BRIDGES, G.E., SAID, R.A., and THOMSON, D.J.: ‘Heterodyne electrostatic force microscopy for non-contact high frequency integrated circuit measurement’, Elrctron. Lett., 1993, 29, pp. 1448-1449
Fig. 2 Microphotograph of 10 GHz GaAs phase-shfter showing scanning probe image of internal measurement location and measured vector Jignu1 9770 I
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-1 0 1 2 phase control voltage, V
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Digitally controlled dB-linear CMOS variable gain amplifier
4
Fig. 3 Phase shft at two internal locatiom (A/B in Fig. 2) meusitred -tising non-contact probe and compured with measirremerits at circuit output using smnpling oscilloscope
H. Elwan, A. El Adawi, M. Ismail, H.K. Olsson and A. Soliman A novel technique to implement a digitally controlled precise dBlinear variable gain amplifier (VGA) in CMOS technology is proposed. The technique is used to realise a robust low power CMOS VGA circuit without component spread. Experimental results from a 1 . 2CMOS ~ chip are provided.
Measurements taken at 9.95GHz
__ circuit output using sampling oscilloscope - _ - _ at node A using non-contact probe (scaled by 5/4)
at node B using non-contact probe Probe meusurenients: Measurements were performed using a 3 5 0 p long metallised silicon probe. The probe was typically located 0 . 3 above ~ the test point during vector measurements. A GaAs analogue/digital phase shifter operating at lOGHz was measured as shown in Fig. 2. The circuit has five equivalent analogue phase shifter cells, a 4 bit digital phase shifter cell, and input/output buffers, A micophotograph of an internal measurement point, along with the topography obtained using the probe in a contact imaging mode is shown in Fig. 2. The vector signal shown is the result of seven tests over a 3 month period. Fig. 3 shows the phase shift measured at the fourth phase shifter and at the output buffer against the phase control voltage. The phase shift from the entire circuit was also measured using a sampling oscilloscope and shows agreement to < lops of the non-contact probe result. All internal points were passivated during measurements.
ELECTRONICS LETTERS
30th September 7999
Introduction: The variable gain amplifier (VGA) is an essential block in many mixed signal applications [l, 21. VGAs are usually employed before the analogue to digital conversion to maximise the dynamic range of the data converter used. The AGC loop is usually formed in the digital part of the chip using digital signal processing. The DSP then digitally controls the gain of the VGA to maintain the signal level at the input of the data converter at a suitable level. Thus, a digitally controlled VGA circuit is required in order to simplify the interface between the digital and analogue portion of the chip. To maintain a constant AGC loop settling time independent of the signal amplitude an exponential VGA gain characteristicis required. In this Letter we introduce a novel digitally controlled VGA circuit that utilises a new concept to generate a precise dB-linear gain characteristic.The circuit has precise and process-independentdigitally controlled dB-linear gain characteristics with no component spread leading to a compact and
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simple implementation.The VGA can also process current or voltage signals and provide low power class AB rail-to-rail operation.
"-D$q2 dn
a
'in
1
1 I
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I
This is not the case in R-2R ladders, where the MOS switch resistance has to be kept much smaller than the resistance used in the ladder to maintain good accuracy. The current division principle only holds if the two output terminals A and B of the current division network are kept at a fixed voltage level. If the voltage levels of the two output terminals are equal, the current division network dissipates almost no standby power. All transistors of the current division network are of equal dimensions. Thus this circuit provides precise digital trimming without any spread in the transistor aspect ratios, which helps to maintain a compact layout area. As will be demonstrated, good linearity between the two outputs of the CDN is expected. To realise the VGA circuit the CDN is placed in the feedback path of an amplifier circuit as shown in Fig. 2. It can be shown that
..._...__.......
-;;;j
(7)
a l - i f l ~ ~ a z + ~ ~
.&
It is thus clear that the gain of the VGA is exponentially controlled by the digital control word. This gain characteristic is independent of process and temperature variations. The VGA stage can process a current input signal as well by applying the current directly to the input virtual ground of the first amplifier. At standby, the CDN consumes no power and the standby power consumption of the VGA circuit can be kept low if class AB amplifiers are used. Higher gain control ranges can be easily obtained by cascading the appropriate number of stages.
I &
... b
Fig. 1 Digitally controlled current division network a Symbol b Circuit
Digitally controlled CMOS VGA: The proposed technique for realising a precise digitally controlled exponential function is based on the digital implementation of the approximation cy= (1 + x)/(l x) [l]. The dB-linear relation can be achieved by dividing a digitally controlled linearly increasing function A , by a digitally controlled linearly decreasing function A*, i.e.
amplifier
"in c _
101
where
1937121 Fig. 2 dB-linear digitally controlled VGA
The resolution n of the digital control word d,,, d, determines the number of gain steps of the VGA circuit. A , is a multiplicative constant. This approximation of an exponential function is valid over a range of 25dB with a gain error of 0.5dB and about 32dB with a gain error of 1dB. In the case of digital control of the exponential function, it is also important to specify the gain step or the resolution of gain control. When the function is implemented using two digital words the valid control range for 25dB is -70% of the total control range. Since a digital word of resolution n has a control range of 2" the gain step in dB is approximatelygiven by
(4)
Experimental results: The VGA circuit was fabricated using a 1 . 2 nwell ~ CMOS process. A class AB circuit with rail-to-rail output swing is used in realising the amplifier circuits to maintain low power consumption. The fabricated circuit provides a 6 bit gain control resolution. Fig. 3 shows the measured VGA gain for a linearly increasing digital control word. The x-axis represents the digital control word and the y-axis is the VGA gain in dB. The ideal cygain is shown by a solid line, the measured gain values are denoted by 'x' and the gain error is shown by the dotted line. A gain range of 25dB can be achieved with a gain error < 0.5dB.
where the gain step is defined as the increase in gain for 1 LSB increment in the digital control word. To effectively implement the proposed method in CMOS technology the complementary nature of the two output terminals of a MOS current division network (CDN) is utilised. The CDN symbol is shown in Fig. la and the CDN circuit is shown in Fig. lb. According to the current division principle [3], the input current 4, of this network divides into two digitally weighted output currents given by n
l o a = I,,
ii,2-2 2=1
The CDN implementationhas the advantage that the switch transistors are a part of the network and thus they have the same aspect ratio and their finite resistance does not contribute any error to the current division. Therefore, all MOS transistors in the CDN can be selected to be small to save area and the equivalent resistance can be small without degrading the division accuracy.
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control word
Fig. 3 VGA measured gain characteristic X
ideal Z gain measured gain
_ _ _ gain ~ error
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30th September 1999
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" " " " -15 -0 5 -0.4 -03 -0.2 -0 1
' 0
~ 0.1
02
0.3
04
05
input voltage, V
Fig. 4 Output voltage against input voltage of VGA circuit for different gain settings
(i) gain = 12 (ii) gain = 18 (iii) gain = 46 ~ _ linearity _ error
The gain control step size is found to vary slightly between 0.55 and 0.59dB over the 25dB gain range. These values agree well with the step size of 0.56dB predicted by eqn. 4. To measure the linearity of the VGA the input voltage is swept and the output voltage is plotted for different gain settings. The result is shown in Fig. 4. The linearity error for one of the gain settings is shown by a dotted line and found to be < 0.04% which corresponds to -1 1 bits of linearity. The three solid lines are for gain control words 12, 18 and 46, respectively. The input referred noise of the VGA is 2lnVdHz at 12dB gain setting. The circuit consumes 387pA of standby current from a 3V supply. The bandwidth of the different components of the circuit was measured. The CDN exhibits a bandwidth of > 18MHz, the first amplifier exhibits a bandwidth of 13MHz when current driven by the CDN. Finally the whole VGA has a bandwidth of -4.1 MHz at unity gain. 0 IEE 1999 Electronics Letters Online No: 19991193 DOI: IO. 1O49/el:I999 I I93
18 June 1999
H. Elwan and M. Ismail (Analog VLSI Lab, Department of Electrical Engineering, The Ohio State University, USA) A. El Adawi and A. Soliman (Electronics and Cornm. Department, Cairo University, Egypt)
H.K. Olsson (Rudio Electronics Laboratory, Royal Institute of Technology, Kista, Stockholm, Sweden)
Introduction; The design of fully integrated tranceivers for mobile communication systems in the R F band entails the realisation of high quality inductors built on standard silicon technologies to avoid extra processing steps. To increase the quality factor, many techniques have been presented, from the shunt connection of all available metallisation layers [11, to the introduction of pnp junctions underneath the inductor to reduce substrate losses [2]. Nevertheless, it is not easy to obtain quality factors greater than 8 for inductors of a few nanohenries; moreover, the achievable values of Q decrease as the inductance rises. In [3] a promising CMOS technique based on an active gyrator was presented. Results showed the possibility of separately regulating the inductance and Q values for frequencies up to 1GHz. Kuhn et al. [4] have suggested a novel technique in which an active device is used to implement a negative resistance, to compensate for the losses in the integrated inductor. This method, however, does not provide any increase in the inductance value and may lead to instability. The circuit concept presented in this Letter provides 20nH of inductance and a peak Q (defined as the ratio between the imaginary part and the real part of the inductor impedance) greater than 45 at the working frequency of 1.8GHz.
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Fig. 1 Basic principle of inductor Circuit design: The active inductor exploits the magnetic coupling between two spiral inductors (L, and in Fig. 1) to increase the inductancevalue seen at the input terminals. The current across L, is amplified by the cascode stage and driven into b.The magnetic coupling results in an increase in the voltage drop on L, by the factorjwMh&, where M is the mutual inductance between L, and and hfeis the current gain of the cascode. The third inductor L3 the input resistance and the emitter junction capacitance of Q, realise a shunt LRC filter, the resonant frequency of which has to be chosen according to the desired operating frequency. The input impedance of the circuit is expressed by the following formula:
+
ZV = [RI - w . M . h j , .sin 'p] + j w . [LI M . h j , .cos 'p] (1)
References HARJANI,R.: 'A low-power CMOS VGA for 50 Mbis disk drive read channels', IEEE Trans. Circuits Syst. II. 1995, 42, (6), pp. 370-376 MOTAMED, A , HWANG, c., and ISMAIL, M.: 'CMOS exponential current-to-voltage converter'. Electron. Lett., 1997, 33, (12), pp.
998-1000 BULT, K., and GEELEN, c.J.M.: 'An inherently linear and compact MOST-only current division technique', IEEE J. Solid-State Circuits, 1992, 27, (12), pp. 1730-1735
High-quality active inductors G. D'Angelo, L. Fanucci, A. Monorchio, A. Monterastelli and B. Neri A high-quality active integrated inductor is presented. The circuit has an inductance of 20nH and a quality factor of 47 at 1.8GHz. It is designed to be realised using standard silicon bipolar technology and consumes 2.6mW at a supply voltage of 3V.
ELECTROhilCS LETTERS
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30th September 1999
where RIis the parasitic series resistance of L, and cp is the angle between the current flowing through L1 and that through L,; it should be noted that cp depends on the resonant frequency of the L3RC filter. As the formula predicts, the quality factor of the resulting inductor is high, since the imaginary part of Z,, increases and the real part decreases. Moreover, control of the angle cp, achieved by tuning the bias voltage of the common-base bipolar junction transistor (BJT) Q2, and control of the current gain hfe, obtained by varying the bias current of Q,, allows the differences in the circuit response due to process tolerances or thermal excursions to be compensated for. These controls may also be exploited for the design of voltage-variable inductors for VCOs. Layout: The active inductance has been designed to be realised on a 0 . 2 silicon ~ bipolar process supplied by ST, which is characterised by three layers of metal and the cutoff frequency of the BJT above 2OGHz. The overall circuit area is 1mm2 (Fig. 2) for a core dimension of 0.64mm2.The main core area contribution is due to ) the the need to decouple the transformer ( 2 5 0 x~ 2 5 0 ~ and . distance must be at least inductance L3 ( 1 6 0 x~ 1 6 0 ~ )This NOW, to obtain an acceptable magnetic decoupling between the two structures [5].To reduce substrate coupling, thick grids of iso-
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