approach for board power distribution network design. The proposed approach relies on the decomposition of the board metallization layers into parallel-plate ...
A Modular Segmentation Approach for Comprehensive Electromagnetic Modeling of the Power Distribution Network Varvara Kollia and Andreas C. Cangellaris ECE Department, University of Illinois, Urbana-Champaign 1406 W. Green St., Urbana, Illinois 61801, U.S.A. {kollia, cangella}@uiuc.edu Abstract The accurate electromagnetic modeling of the power distribution network at the board level is critical for today's digital applications. In this work, we propose a modular approach for board power distribution network design. The proposed approach relies on the decomposition of the board metallization layers into parallel-plate polygons and the various geometric discontinuities introduced by vias, slots and splits in metallization planes, and the edges of the board. Electromagnetic models for the various segments are generated a-priori and are brought together in a physically consistent manner to yield a compact model for the board that lends itself to an expedient numerical solution toward the generation of a SPICE-compatible, broadband, frequencydependent multi-port network. Numerical studies are presented that validate the proposed methodology and demonstrate its attributes. 1. Introduction Recent technological trends in high-speed digital circuits have prompted the need for accurate electromagnetic (EM) modeling of the power distribution network (PDN) at the printed circuit board (PCB) level during the design phase. Such modeling is needed to anticipate signal and power integrity violations during switching, and explore PDN redesign and decoupling strategies for their mitigation or suppression. The electrical behavior of the PDN in state-of-the-art PCBs benefits a lot from the implementation of planar multiple layers of power and ground metallization that facilitate PDN impedance control. However, the escalating functional complexity of the supported electronics translates into PDN complexity to provide for multiple voltage references, isolation between them, multi-pin access to them from the package. All of the above result in a multi-plane PDN with numerous geometric discontinuities introduced by splits in planes and the large numbers of pins and vias that traverse the planes. It is this added, three-dimensional complexity of these discontinuities that complicates the electromagnetic modeling of the PCB PDN, and requires the implementation of sophisticated field solvers for its electrical analysis. Over the years several methods have been put forward for PDN electrical modeling [1]-[7]. Both finite method-based electromagnetic models and integral equation based ones have been proposed. Most popular and computationally most efficient among these methods are those that exploit the predominantly cylindrical, transverse electromagnetic field behavior between parallel metallization planes in close proximity [3],[4]. The most popular, commercially available
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PDN modeling tools take advantage of this behavior and combine it with the modeling flexibility of finite difference and/or finite element discretization to tackle the complexity of the multi-layer PDN. Improved accuracy in the modeling of three-dimensional effects in such an approach is possible using ideas such as those presented in [5]. The computer-aided design (CAD) tools that have resulted from the implementation of the aforementioned modeling methodologies seem to be driven predominantly by PDN performance verification objectives. However, as designers push for PDN modeling capability with electromagnetic accuracy during the design phase, the opportunity arises for the exploitation of modeling techniques that provide the efficiency and modeling versatility necessary for design iteration. In particular, the ability for quick assessment of the impact on PDN performance of changes in metallization layout, number of pins, and placement of decoupling capacitances (see, for example, [8], [9]), are some of the desirable features for a design-iteration driven PDN modeling tool. The need for such a capability and a way through which such capability can be implemented was presented in [6]. An alternative approach toward the development of a PDN design iteration tool was proposed in [10], where a segmentation methodology that had been successfully applied to planar circuit design [11] was relied upon to provide the required versatility and expediency in PDN geometry definition, iteration and subsequent solution. Building upon the introductory ideas in [10], we demonstrate in this paper the ease with which layout modifications are supported within the segmentation-modeling framework of the proposed methodology. The synthesis process through which a multiport network model of the PDN is generated, is described in detail, including a brief overview of the development of models for the various types of PDN three-dimensional discontinuities. In addition to validation studies, numerical studies demonstrating the attributes of the proposed methodology are presented. 2. The Integral Equation Model The PDN at the board level consists of multiple, power and ground metallization planes, traversed by a large number of pins and vias, and interrupted by isolation slots and, in general, arbitrarily shaped metallization voids. The inter-plane separation of the metallization pairs (of the order of 1 mm) is a small fraction of the minimum wavelength (of the order of 2 cm) for the applications of interest. This key observation reduces the three-dimensional (3D) EM problem to a twodimensional (2D) one, as the field exhibits no variation in the direction perpendicular to the planes in the domain in between
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the planes and away from discontinuities. The resulting, reduced 2D EM problem can be solved using the integral equation (IE) approach [11].
original geometry of Fig. 1 can be decomposed into three subsections. To describe further the way voltage and current continuity conditions are imposed at common ports, consider the ports Q and P in subsection 2 and 3, respectively. The pertinent continuity conditions are,
VP I P + IQ
Figure 1. PDN metallization plane pair of rectangular shape.
For the sake of simplicity and without loss of generality of the approach, we consider a pair of two rectangular plates, with separation h and cross-sectional dimensions a×b, as depicted in Fig. 1. In the reduced 2D EM problem, in the absence of field variation along z, the electric field vector has only one, z directed component and the magnetic field has only two components, the ones parallel to the plane metallization. Following [11], under the assumption that the medium between the two plates is isotropic and homogeneous, the electromagnetic field everywhere between the plates can be obtained in terms of its values along the boundary C. In particular, the quantities of interest in the model are the electric and magnetic field components along the boundary and in the two directions tangent to it; hence, with tˆ denoting the tangential direction along the periphery, the two quantities of interest are E z , H t along the contour C. The integral equation statement that relates these field components is discretized using the Method of Moments (MoM) [12]. Moreover, a circuit interpretation of the resulting discrete model is possible. As described in [11], with ∆wn , n = 1, 2, K , N denoting the length of the nth segment in the discretization of the contour C, each segment represents a port with voltage Vn and current In, defined as
Vn
=
− Ez h
In
=
− H t ∆wn
(1)
With this interpretation, the discrete model resulting from the approximation of the integral equation is cast in terms of the following multi-port network form,
{I} = [ Y ]{V}
(2)
where {I}, {V} are the vectors containing the voltage and the current ports respectively. It becomes immediately evident that this interpretation of electromagnetic models of sections parallel-plate metallization pairs lends itself to the systematic development of models for multiple metallization planes of arbitrary shapes through the interconnection of the sections along their common ports subject to voltage and current continuity constraints [11], [13]. To elaborate, the PDN metallization layout is divided into a number of subsections and a multi-port model for each subsection is constructed. For example, Fig. 2 shows how the
= VQ =
0
(3)
The enforcement of these continuity conditions at all common ports constitutes the de-segmentation approach through which the overall multi-port network matrix for the entire PDN structure is formed. For the purposes of PDN performance assessment and design iteration, ports associated with the power/ground pins that connect the board PDN to the package, as well as ports formed by power/ground pin pairs for decoupling capacitor assignment are of interest. These ports are associated with three-dimensional discontinuities of the PDN which are not accounted for in the aforementioned integral equation model. The way they can be modeled and incorporated in the overall multi-port network model is described in the next section.
Figure 2. Decomposition of the PDN geometry of Fig. 1 into three subsections.
The suitability of this approach for PDN layout iteration is apparent. Subsections can be either removed from an original layout, their shapes can be modified, or additional metallization blocks may need to be incorporated. This requires model changes at the subsection level only, hence, enabling a modular, expedient approach to layout iteration. It will become apparent from the discussion in the next section, insertion of additional pins and vias and, hence, insertion of additional decoupling capacitors, can be done in a convenient and straightforward manner. The block diagram of Fig. 3 illustrates the process for model development using the proposed methodology. 3. Synthesis Process In the vicinity of a PDN discontinuity the electromagnetic field behavior is three dimensional and thus impossible to model accurately using the cylindrical transverse model of the previous section. Since pin, via, and slot discontinuities are in a large part responsible for field coupling between metallization pairs in multi-layer PCBs, their EM modeling is essential for accurate prediction of the PDN electrical attributes. To accurately model the field behavior in the immediate neighborhood of the discontinuities, special localized models can be used. Furthermore, these models can be developed a-priori and abstracted in terms of compact
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multi-port models appropriate for seamless interfacing to the multi-port network models of metallization plane pairs.
structure and to the outer sides of the slots S1 – S7. For this segment of metallization the IE yields
⎧ I o(1) ⎫ ⎡Y11(1) Y12(1) ⎤ ⎧Vo(1) ⎫ ⎨ (1) ⎬ = ⎢ (1) (1) ⎥ ⎨ (1) ⎬ ⎩ I s ⎭ ⎣Y21 Y22 ⎦ ⎩Vs ⎭
(4)
where the superscript (1) represents the nodes on contour C1 and the vectors with the subscripts (o,s) correspond to the outer periphery of the structure or to the outer slot boundaries respectively. Likewise, the boundary nodes for the subdomain D2 reside on C2 that is comprised of the inner slots S1 – S7 and the mathematical boundaries for the two vias that we introduce to accommodate their integration into the segmentation process. In a similar manner, we can denote the boundary nodes on contour C2 for the subdomain D2 with the superscript (2), followed by the subscript (s) or (v) to refer to the inner slot boundaries or the vias, respectively. By the IE we have
⎧ I v(2) ⎫ ⎡Y11(2) Y12(2) ⎤ ⎧Vv(2) ⎫ ⎨ (2) ⎬ = ⎢ (2) (2) ⎥ ⎨ (2) ⎬ ⎩ I s ⎭ ⎣Y21 Y22 ⎦ ⎩Vs ⎭ Figure 3. PDN model development flow.
Fig. 4 shows a metallization plane pair with multiple slots, denoted by S1 – S7, and two via holes. If the top plane is assumed to be a power plane and the bottom one a ground plane, the via holes are associated with two ground pins that connect to the ground plane. The structure can be decomposed into the following generic segments: two multiply connected metallization pairs, seven slots and two vias. The boundary element nodes associated with the corresponding EM problems reside on the periphery of each subdomain.
(5)
The two subdomains are coupled through the slots. The coupling across the slot between is assumed to occur in the direction transverse to the slot axis, involving voltage nodes opposite to each other. Thus, assuming a uniform slot of constant width, the electromagnetic model describing coupling across the slot model requires the extraction of a two-port admittance matrix that quantifies the frequencydependent coupling between two nodes opposite to each other in the direction perpendicular to the slot axis. With yij , i , j = 1, 2 , denoting the elements of this admittance matrix
and assuming that there are N of opposite nodes along a given slot, the (2N×2N) admittance matrix defining coupling across the slot is given by ⎧ I side1 ⎫ ⎡ y11U N y12U N ⎤ ⎧Vside1 ⎫ ⎨ ⎬=⎢ ⎬ ⎥⎨ ⎩ I side 2 ⎭ ⎣ y21U N y22U N ⎦ ⎩Vside 2 ⎭ where U N denotes the (N×N) unit matrix. This process can be directly applied to the slots of Fig. 4. Different admittance parameters should be extracted for slots with different widths and the slot lengths indicate the distribution of the parameters, as the currents are proportional to the port widths, according to (1). Eventually, we would have a matrix system that describes the coupling between the nodes, -denoted by slt-, on the inner and the outer sides of all slots
⎧ I 1slt ⎫ ⎡Y11( s ) ⎨ slt ⎬ = ⎢ ( s ) ⎩ I 2 ⎭ ⎣Y21
Figure 4. Top view of a power/ground plane pair with a power island introduced in the top metallization plane.
For each one of the metallization segments the IE equation will be used. The first subdomain D1 is bounded by the contour C1 that corresponds to the outer periphery of the
Y12( s ) ⎤ ⎧V1slt ⎫ ⎬ ⎥⎨ Y22( s ) ⎦ ⎩V2slt ⎭
(6)
assuming that each slot has the same number of unknowns on its inner and outer boundary. According to (3) it is, I1slt = − I s(1) , I 2slt = − I s(2) , V1slt = Vs(1) and V2slt = Vs(2) . It is straightforward to combine these continuity conditions along with the IE equations by (4) and (5) and the coupling conditions of (6) into the following system [K t ] {I} = [ Yt ] {V}
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where
{I} = {I o(1)
I s(1)
I v( 2)
I s( 2)
}
T
and
{ V}
is defined
accordingly. In this system [ Yt ] is defined as
⎡Y11(1) ⎢ (1) ⎢Y21 ⎢ 0 [ Yt ] = ⎢ ⎢ 0 ⎢ 0 ⎢ ⎢⎣ 0
Y12(1)
0
0 ⎤
(1) 22
0
0
Y11( 2)
0 ⎥
Y12( 2) ⎥
0
Y21( 2)
−Y11( s )
0
Y22( 2) ⎥ −Y12( s ) ⎥
−Y21( s )
0
−Y22( s ) ⎥⎦
Y
⎥ ⎥ ⎥
and [ K t ]
⎡U o(1) 0 0 0 ⎤ ⎢ ⎥ (1) 0 0 ⎥ ⎢ 0 Us ⎢ 0 0 U v( 2) 0 ⎥ [K t ] = ⎢ ⎥ 0 0 U s( 2) ⎥ ⎢ 0 ⎢ 0 U (1) 0 0 ⎥ s ⎢ ⎥ 0 0 U s( 2) ⎥⎦ ⎣⎢ 0 (i )
where U j , i={1,2}, j={o,v,s} are the corresponding unit matrices. In a similar manner, other types of discontinuities can be incorporated in the overall system, provided that an admittance matrix description is available for the behavioral, frequency-dependent modeling of the discontinuity. Once all the discontinuities are incorporated, the overall matrix system can be cast in terms of the unknown boundary nodes as a function of the driving port nodes (either voltage or current nodes) residing on the via gaps. This would result in the formulation of a square sparse system that can be solved to provide for the admittance or impedance parameters of the structure. In summary, the integration of the individual subcomponents is done in consistency with the desegmentation procedure described in the previous section. 4. Admittance Matrix Extraction of PDN Discontinuities In this section we discuss through specific examples the process through which the admittance matrix describing a PDN discontinuity can be computed. We begin with the case of a slot in a metallization plane. Exploiting the radial transverse electromagnetic field supported by the parallelplate pair and the fact that, for small slot widths, coupling is predominantly between voltage nodes on opposite sides of the slot, a two-dimensional model suffices for the extraction of the frequency-dependent admittance parameters. The pertinent two-dimensional geometry used for the numerical scheme is depicted in Fig. 5. z
×
hs h
t
s
superstrate substrate
n
Referring to the geometry depicted in Fig. 5, the voltage and current port parameters on either side of the slot are to be computed, respectively, in terms of the z-directed electric field, Ez, and the tangential magnetic field, Ht. Either integral equation techniques or finite methods can be used for the extraction of the slot admittance matrix. For the latter, and for the case where the slot occurs at the top metallization layer, the computational grid used for the calculation of the admittance parameters must be truncated through an artificial boundary on which appropriate radiation boundary conditions must be imposed. Because of the rectangular nature of the structure, a finite difference method is used for the numerical solution of the problem [5]. During the numerical solution the ports are placed at a sufficient distance away from the slot such that the TEM component of the field is the one involved in the calculation of the admittance parameters. Subsequently, de-embedding is used to transfer the port parameters at the physical edges of the slot. It is noteworthy that due to the fact that the problem is two-dimensional, special attention should be drawn to the definition of the local coordinate system. In particular, for all cases, the normal vector, nˆ , is defined as looking into the slot, and, thus, the tangential unit vector is the cross product of zˆ × nˆ . This leads to a consistent way of eliminating the common nodes, as the direction of the current is uniquely defined at the boundary nodes. The next discontinuity we consider here is that of a ground via. More specifically, with reference to Fig. 4, the discontinuity is that of a ground via with one of its ports associated with the circular slot formed between its anti-pad and the metallization of a power metallization layer through which the via is drawn. The pertinent anti-pad boundaries are depicted by the circular contours in Fig. 4. Next, we assume that the radial electrical field along the slot exhibits rotational symmetry. Furthermore, it is assumed that rotational symmetry is also exhibited by the electric field between the ground and power metallization plates along a circular, cylindrical boundary, co-axial with the via, which will be used as the second port for interfacing the via with the rest of the model. With these assumptions, the electromagnetic boundary value problem exhibits rotational symmetry, thus lending itself to a two-dimensional analysis involving its ρ − z cross section. Similarly to the case of the slot in a metallization plane, the cylindrical boundary along which one of the ports is assigned is placed at a distance sufficiently far away from the anti-pad gap for the TEM component of the field to be the one involved in the calculation of the admittance parameters. Subsequently, de-embedding techniques are used to shift the boundary at the edge of the gap. The second port is assigned at the gap. At this point it is appropriate to mention that if one of the terminals of a decoupling capacitor is connected to a ground via described in terms of the aforementioned two-port admittance matrix, the port associated with the anti-pad gap is eliminated and the associated port voltage and current are constrained through the I-V relationship describing the lumped circuit model, YC(ω), of the capacitor. If m nodes are
Figure 5. Slot geometry on a plane transverse to the slot axis.
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associated with the description of the gap port, then the admittance assigned at each node equals YC/m. We conclude this section by pointing out that a commonly encountered discontinuity is the one associated with the truncation of a metallization plane pair. A simple, one-port model of such a discontinuity, which can be used to account for both electric field fringing at the edge as well as radiation loss, is the truncated waveguide discontinuity described in [14]. Its implementation in the proposed modeling methodology was elaborated in [10]. 5. Grouping of Dense Clusters of Pins/Vias One of the challenges in the modeling of the package and board PDN entails the computationally efficient representation of dense clusters of pins/vias. Consider, for example, the case of a cluster of ground pins, all associated with the same reference ground. If the electrical size of the footprint of the cluster is a small fraction of the minimum wavelength of interest (e.g., less than 0.1λmin ), it can be safely assumed that all vias are at the same potential. For such cases, a quasi-static approach can be used to abstract the cluster in terms of a single equivalent via that exhibits the same electrical properties as the cluster. This is done as follows. With all N vias in the cluster assumed to have the save voltage drop along their length h, their effective inductance is found to be
(
Le = [P ] [L ] [P ] −1
)
T −1
(
The geometry for the first numerical study is depicted in Fig.6. It is a power/ground metallization pair consisting of two 10 cm by 10 cm parallel plates placed at h = 1 mm apart. The edges are truncated with perfect magnetic conductors (PMCs); hence, the current goes to zero at the plate edges and the structure, except for the via ports is expected to behave as a resonant cavity. The three ports are associated with the ground via gaps at the top plate with (x,y) coordinates given by (1,1), (5,5), and (9,9), where all dimensions are in centimeters. A decoupling capacitor of 1 µF is connected through a fourth via at (5, 6.5) cm. The via gap width is 0.05 mm, equal to the via radius. The anti-pad radius is 0.38 mm. The discrete model of this structure required 192 unknowns. Figure 7 depicts the comparison of results obtained using our model with those obtained using HFSS. Very good agreement is observed.
(7)
where [ P ] = {1,1,K ,1} and the matrix [ L ] contains the self and mutual partial inductances of the vias. These inductances are given by [15] µ ⎛ h2 + d 2 + e d − h2 + d 2 Lij = o ⎜ h ln 2π ⎜⎝ d
bandwidth 25 MHz to 4 GHz with frequency step of 25 MHz. The insulating material considered is taken to have relative electric permittivity of ε r = 3.4 and loss tangent of 0.02.
)
⎞ ⎟ ⎟ ⎠
Figure 6. PDN structure used for validation purposes.
(8)
In the above expression, for the mutual partial inductances d is the axial distance of the two vias, while for the self inductances d denotes the via radius. The factor e is an empirical factor that accounts for the image contributions for the self partial inductances for the case of grounded vias, in which case its value is 1.5, as proposed in [16]; otherwise, e = 1.0. Once Le has been computed, (7) can be used to calculate the radius of an equivalent of the same height as each one of the vias in the cluster. This serves as the equivalent via description of the cluster. This equivalent via is placed at the center of the footprint of the cluster and its modeling in terms of an admittance two-port is done as described in the previous section. The aforementioned approach can be extended to reduce the complexity of clusters containing both power and ground pins/vias and provides for a significant reduction in the complexity of the PDN model. 6. Numerical Studies To demonstrate the effectiveness of the proposed algorithm, we developed a prototype code in MATLAB. All simulations were performed on an Intel Core Duo processor with 1 GB of RAM. For each numerical study PDN impedance parameters are computed over the frequency
Figure 7. Impedance parameters for the PDN structure of Fig. 6.
The purpose of the second numerical study is to examine the accuracy of the segmentation and de-segmentation processes employed in the proposed methodology. The structure under investigation is a square parallel-plate pair, one power and the second ground of side 23.86 cm. Fringing and radiation from the edges is accounted for using the oneport edge boundary condition discussed at the end of Section 4. The plate separation is 1 mm. Two vias, with their center coordinates given by (4.7, 10) cm and (11, 17) cm, are used as
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the ports of the PDN structure. Each via has radius and gap width equal to 0.125 mm. The via gap is at 0.275 mm from the via axis. The structure is first analyzed as a single block. A second model of the structure is generated by using the 24-sided polygon depicted in Fig. 8 to define boundaries of subdomains along which the board is segmented. The comparison of the calculated impedances of the board using the two models is presented in Fig. 9. Very good agreement is observed, demonstrating the accuracy of the implementation of the segmentation and de-segmentation processes.
0.25 mm. A sketch of the top plane is depicted in Fig. 11. A total of 134 slots are present, of lengths varying from 0.6 mm to 23.86 cm. Along the outer periphery of the board, the oneport model of the parallel-plate edge was used to account for fringing and radiation.
Figure 10. Impact of slot and decoupling capacitor on the partial impedance | Z 21 | . Figure 8. Top view of generic power plane using decomposition.
Figure 9. Comparison of computed impedances for the PDN structure of Fig. 8 with and without use of segmentation.
Next a slot is introduced along the periphery of the polygon. The slot width is 0.25 mm. In addition, through the introduction of a via, a decoupling capacitor of 10 µF is introduced in close proximity to the second port at (12.4, 18.4) cm. The calculated impedances depicted in Fig. 10 show that the introduction of the slot reduces significantly the coupling between the two ports. Furthermore, through the introduction of the decoupling capacitor, isolation between the two ports is further reduced in the lower frequencies. The final study concerns the modeling of a realistic board structure consisting of a pair of metallization planes, one for ground and one for power. The bottom plane is a solid ground plane of square shape and side 23.86 cm. The top metallization is power, consisting of a multitude of power islands, isolated from one another through slots of widths of
Figure 11. Top view of a realistic, two-layer board.
Indicated in Fig. 11 with the letters A and B are the two islands in which the ground via ports used for the definition of the multiport model are located. The structure is modeled as an 18-port, with each port corresponding to an equivalent ground via. The first 9 vias (numbered 1-9) are placed in subdomain A and the remaining (9-18) in sub-domain B. Each one of these equivalent vias represents a cluster of vias, with the number of vias in each cluster varying from 4 to 24. The largest cluster had a circular footprint of radius 4.8 mm. The various clusters, including the number of vias per cluster, the radius of the cluster footprint and the resulting effective inductance are listed in Table I.
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In Figures 12-14 we plot the magnitude of several of the calculated PDN impedance parameters for different values of the 18 decoupling capacitors that were inserted in close proximity to the via ports. It is noted that ports 2 and 5 belong to sub-domain A while port 14 is a port in sub-domain B. The isolation provided by the slot as well as the suppression of resonances by means of the decoupling capacitances is evident in the plotted impedance profiles. The developed model involved 2848 nodal unknowns. From them, 108 nodes were associated with the driving ports. It is important to stress that if a finite method were to use to discretize this structure, the presence of the slots would have resulted in discrete models with very large numbers of discrete unknowns with obvious consequences on computation efficiency. For our methodology, the solution time per frequency point is 15.7 seconds.
Figure 13.
| Z 25 | for the PDN structure of Fig. 11.
Table I. Equivalent Vias N
R (mm)
L (pH)
Eq. Via 1 Eq. Via 2 Eq. Via 3 Eq. Via 4 Eq. Via 5 Eq. Via 6 Eq. Via 7 Eq. Via 8 Eq. Via 9 Eq. Via 10 Eq. Via 11
11 24 12 24 9 5 6 10 12 24 10
1.1150 1.2793 0.8077 1.3313 0.7025 0.6449 0.6751 0.7190 0.8077 1.2738 0.9213
46.4846 40.3211 64.6992 38.6909 74.4309 81.0043 77.4290 72.7348 64.6992 40.5002 56.5800
Eq. Via 12
20
1.1137
46.5407
Eq. Via 13 Eq. Via 14 Eq. Via 15 Eq. Via 16 Eq. Via 17 Eq. Via 18
24 5 4 4 4 4
1.3050 0.6127 0.5666 0.5854 0.5860 0.5453
39.4995 85.1551 91.8214 88.9999 88.9041 95.2343
Figure 14. | Z 2,14 | for the PDN structure of Fig. 11. 7. Future Model Enhancements Future work on the enhancement of the proposed methodology includes the parameterization of the discontinuities in terms of not only frequency but their geometrical features, as well. Additional activities involve the investigation of the accuracy of the proposed pin/via clustering technique, toward the development of robust guidelines for its application to model complexity reduction for the various types of PDN discontinuities (vias, slots, plane edges). Numerous numerical studies were presented to validate the method and highlight its key attributes. Acknowledgments The authors would like to thank Mrs. Limin Dong for her help with the extraction of the board geometry. This work was supported in part by the Semiconductor Research Corporation and Qualcomm, Inc. References 1. J. Fang, Z. Wu, Y. Chen and Y. Liu, “Application of the finite-difference time-domain method in the simulation of Delta-I noise in electronics packaging,” Proc. IEEE 10th Annual Rev. Prog. in Appl. Comput. Electromagn., Vol. 2, Monterey, CA, March 1994, pp. 30-37.
Figure 12.
| Z 22 | for the PDN structure of Fig. 11. 644
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2. W. Pinello, A. C. Cangellaris and A. Ruehli, “Hybrid electromagnetic modeling of noise interactions in packages electronics based on the partial-element equivalent circuit formulation,” IEEE Trans. Microwave Theory Tech., Vol. 45, No. 10, Oct. 1997, pp. 1889-1896. 3. J. Fang, Y. Chen, and Z. Wu, “Modeling of electrical properties of power/ground planes in electronics packaging,” Proc. 1st Int. Symp. Microelectron. Packag. PCB Technol., Beijing, China, Sept. 1994, pp. 74-83. 4. W. Shi and J. Fang, “New efficient method of modeling electronics packages with power and ground planes,” Proc. 10th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Cambridge, MA, Oct. 2001, pp. 237-240. 5. M. J. Choi and A. C. Cangellaris, “A quasi threedimensional distributed electromagnetic model for complex power distribution networks,” IEEE Trans. Adv. Packag., Vol. 25, No. 1, Feb. 2002, pp. 28-34. 6. C. Wang, J. Mao, G. Selli, S. Luan, L. Zhang, J. Fan, D. J. Pommerenke, R. E. DuBroff and J. L. Drewniak, “An efficient approach for power delivery network design with closed-form expressions for parasistic interconnect inductances,” IEEE Trans. Adv. Packag., Vol. 29, No. 2, May 2006, pp. 320-334. 7. J. Fan, H. Shi, A. Orlandi, J. L. Knighten, J. L. Drewniak, “Modeling DC power-bus structures with vertical discontinuities using a circuit extraction approach based on a mixed-potential integral equation formulation,” IEEE Trans. Adv. Packag., Vol. 24, No. 2, May 2001, pp. 143157. 8. Y. F. Yuan, “Analysis of power/ground noises and decoupling capacitors in printed circuit board systems,” Proc. IEEE Int. Symp. Electromagn. Compat., Austin, TX, Aug. 1997, pp. 425-430.
9. T. Takken and D. Tuckerman, “Integral Decoupling Capacitance Reduces Multichip Module Ground Bounce,” Proc. IEEE Multi-Chip Module Conference, Santa Cruz, CA, March 1993, pp. 79-84. 10. V. Kollia and A. C. Cangellaris, “Extended Segmentation Procedure for Electromagnetic Modeling of the Power Distribution Network,” Proc. 16th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Atlanta, GA, Oct. 2007, pp. 65-68. 11. T. Okoshi, Planar Circuits for Microwaves and Lightwaves, Springer Verlag, Inc. (New York, NY, 1985), pp. 1-96. 12. R. F. Harrington, Field Computation by Moment Methods, The IEEE/OUP Series on Electromagnetic Wave Theory (Piscataway, NJ, 1992), pp. 41-58. 13. R. Chadha and K. C. Gupta, “Segmentation method using impedance matrices for analysis of planar microwave circuits,” IEEE Trans. Microwave Theory and Tech., Vol. MTT-29, No. 1, Jan. 1981, pp. 71-74. 14. N. Marcuvitz, Waveguide Handbook, Peter Peregrinus Ltd on behalf of the Institution of Electrical Engineers (Cambridge, United Kingdom, 2005), pp. 179-183. 15. J. R. Miller, I. Novak, I. and T. Chou, “Calculating partial inductance of vias for printed circuit board modeling,” Proc. 11th IEEE Topical Meeting on Electrical Performance of Electronic Packaging, Monterey, CA, Oct. 2002, pp. 123-126. 16. M. E. Goldfarb and R. A. Pucel, “Modeling via hole grounds in microstrip,” IEEE Microwave Guided Wave Lett., Vol. 1, No. 6, June 1991, pp. 135-137.
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