A-Priori Wirelength and Interconnect Estimation Based on ... - CiteSeerX

A-Priori Wirelength and Interconnect Estimation Based on Circuit Characteristics∗ Shankar Balachandran

Dinesh Bhatia

Center for Integrated Circuits and Systems Department of Electrical Engineering University of Texas at Dallas, TX - 75080, USA

Center for Integrated Circuits and Systems Department of Electrical Engineering University of Texas at Dallas, TX - 75080, USA

[email protected]

[email protected]

ABSTRACT

tempts are made to predict wirelength and routing at different stages of design cycle to break the repetitive design convergence loop. A-priori estimation techniques are a class of prediction methods that perform estimation without any knowledge of the actual placement of the circuit. Many a-priori estimation techniques use Rent’s Rule [1] [5] to predict the average wirelength and routing demand for ASIC design flow. But these methods can only give a rough idea of the interconnection requirements of the circuits. The estimates produced are often qualitative and cannot be used directly without extensive calibration of results. This is a serious handicap for designers who rely on the estimation techniques to plan their designs. Predicting interconnect requirements for FPGA designs is a fairly new area. It involves two main factors i) predicting wirelength and ii) predicting maximum channel width. In this work, we try to alleviate some basic problems with interconnect prediction for FPGAs. Firstly, we use the circuit characteristics and knowledge of the underlying FPGA architecture to produce bounding box estimates on every single net. By doing so, we provide more than a rough view of the interconnection requirements for the design at hand. Secondly, we use the bounding box estimates and predict the channel width for successfully routing the design. We use various circuit parameters including the number of nodes in different levels in the circuit, the shape of the circuit, the reconvergences in the circuit etc. along with the device size requirements for a tight placement of the design. We theorize how an optimized placement will be for every net based on the “push” and “pull” of cells on each other. We do this without performing pre-characterization of either the placement or the routing tool. Several methods have been proposed to build an optimized placement model to estimate wirelength/routing demand. A very early work by Sechen [9] builds an optimized placement model by calculating the average connectivity of a cell and by enumerating the location of the cell and its closely connected cells in a tight bounding box. The method requires complex numerical calculations and produces only average wirelength. Hamada et al. [6] performed neighborhood analysis and brought in probability arguments to get wirelength distribution for circuits. They don’t produce estimates for individual nets though. Recently proposed work [3] by Bodapati et al. produces individual bounding box estimates but requires a careful characterization and calibration of specific placers and routers. None of these methods predict maximum routing demand. A Rent’s rule based method

Interconnect prediction is very important for early feasibility studies in modern design flows. Most of the interconnect estimation techniques estimate average or total wirelength and some qualitative measure of routing demand for circuits. A-priori techniques estimate these characteristics without actually performing circuit placement. We propose a new a-priori interconnect and wirelength estimation methodology for island style FPGAs. For a given design, we estimate bounding box lengths of all nets for an optimized placement and the minimum number of tracks per channel required for successful routing on an FPGA device. We analyze the structural characteristics of circuits and limitations posed by the FPGA architecture to derive a consistent model for wirelength and routing demand estimation. Our results show that we have an average error of 11.6% w.r.to bounding box spans measured from the optimized layout using VPR [2]. Also, the number of routing tracks is predicted with an average error of 6.1% of the detailed routing results from VPR.

Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids—Placement and Routing; B.7.1 [Integrated Circuits]: Design Styles—Gate Arrays

Keywords Interconnect Estimation, Routing Demand, Placement, Wirelength

1.

INTRODUCTION

Interconnect prediction is getting more and more relevance as modern CAD flow requires repetitive cycles of placement and routing to converge on a solution. Many at∗Supported in part by ACM SIGDA Design Automation Conference Graduate Scholarship.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. SLIP’03, April 5–6, 2003, Monterey, California, USA. Copyright 2003 ACM 1-58113-627-7/03/0004 ...$5.00.

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by Yang et al. [11] calculates routing demand by performing Rentian analysis on the circuit, but does not produce any wirelength distribution or individual wirelengths. These shortcomings of other works make our work unique in building a common methodology to predict both individual wirelengths and routing demand.

2.

maximum level in the circuit is stored as cmax. For sequential circuits, the circuit is divided into different sequential levels at the Flip-Flop boundaries. Now, every node x ∈ C is associated with a pair (s(x), c(x)), where s(x) is the sequential level in the circuit , and c(x) is the combinational level within that particular sequential level. The PIs have a sequential level of 0. FlipFlop x with its input x0 has sequential level s(x) = s(x0 ) + 1. All the combinational nodes in the circuit have sequential level s(x) = min(s(x0 )|x0 ∈ f anin(x)). The maximum sequential level is stored as smax. For combinational circuits, smax is 0. The combinational and sequential levels are used in this method to identify how the nodes are distributed in the layout after placement.

METHODOLOGY

A conventional island style FPGA is shown in Figure 1. It comprises of a two dimensional array of logic blocks marked L. The routing matrix comprises of programmable connection boxes (C), switch boxes (S) and routing channels. The number of routing tracks per channel is referred to as channel width. For a circuit that is placed on such an FPGA, we estimate the wirelengths of the nets as their bounding box widths. Also, the channels in the FPGA must be wide enough to successfully route the design. This width is dependent on both the circuits and their optimal placements, and hence varies from one circuit to another. We estimate this as the maximum channel width. L

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• Shape : Shape[c] nodes in tend this levels.

Shape of the circuit is a crucial factor in our estimation method. Circuits come in different shapes. We theorize about the how the cells in the shape vector are distributed in an optimized layout. This is discussed in detail in Section 4.3.

}

Channel Width

We also define some parameters useful in this estimation methodology : • Reconvergence : Reconvergence is defined to originate on a node x, if branches of multiple fanouts of x join later at a node y. The reconvergence will be referred by the name Rxy . x is the “origin” and y is the “destination” of the reconvergence Rxy . All such paths form a set Pxy . For each path p ∈ Pxy , the length of the path is noted as l(p).

Channels

Figure 1: Island Style FPGA Architecture

• Number of Reconvergences : For a particular reconvergence Rxy , the parameter RNxy is the number of reconvergences with x as origin and y as destination.

We take circuits that are technology mapped for LUT based FPGAs. Based on the number of logic blocks and the IOs in a design, we first calculate the dimensions of the smallest device on which the design will fit. We then estimate wirelength and maximum channel width required for this design. We validate the results with a popular academic tool suite VPR [2]. The bounding box calculations are done on optimized placements produced by VPR and compared against our estimates. We also route the design using VPR and note down the channel width required by VPR and we compare it with our estimates of maximum channel width. Since VPR is well known to produce very tight results for both placement and routing, validation against it provides more reliability on our method.

3.

Shape of a circuit is defined as a vector = c0 · · · ccmax , where ci is the number of the level i. For sequential circuits, we exdefinition for all cells in different sequential

• Length of Reconvergence : For a particular reconvergence Rxy , the sum of all the path lengths from x to y is defined as the reconvergence length. The origin and destination nodes are associated with two parameters, ROxy (x) and RIxy (y) respectively. They are calculated as : 1 ROxy (x) = RIxy (y) = l(p) RNxy p∈P xy

This is the average length of reconvergence between the nodes x and y. Applications of these parameters are discussed later in Section 4.2. Note that these parameters are applicable only to the nodes x and y and not to the rest of the nodes on the reconvergent paths.

DEFINITIONS AND OVERVIEW

CIRC [7] identified certain important characteristics of a digital circuit for synthetic benchmark generation. We use two of these parameters in our estimation methodology, namely

We illustrate the definitions using an example in Figure 2. There are 7 nodes in the circuit with A as input and G as output. The combinational levels c of all the nodes are shown just below the nodes. Since this is a combinational circuit all nodes have s = 0 and left out from the figure for brevity. The shape of the circuit is noted down by summing up the number of nodes in each level. There are two

• Level : Combinational level c(x) of a node x in a circuit C is defined as c(x) = max(c(x0)|x0 ∈ f anin(x))+ 1, where f anin(x) is the fanin set for node x. The primary inputs (PIs) have a combinational level of 0. The

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R = 2; RI1 = 2, RI2 = 2; AG R = 2; RO1 = 3, RO2 = 2;

A

is referred to as the span of the net in the following discussions. Our discussions relate to both the horizontal and vertical spans, and hence we assume that all discussions are w.r.to horizontal span till Section 4.4. Furthermore, we also classify the nets as, 1) IO-Nets which run from input pads in the circuit, and 2) Logic Nets which run from CLBs and may sink either CLBs or output pads. Our method is divided into three phases. The first phase identifies the absolute minimum span that is required by every net. This calculation is done by bringing a counting argument on the number of sites available around the source terminal, and the number of terminals in every net. The second phase applies dilation on the minimum span by using weight of the nodes in the immediate neighborhood according to their reconvergence behavior. The third phase uses the shape of the circuit and the arguments about how the nodes in the circuit may be distributed in an optimized placement to derive the final estimation figures.

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c=2

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BE R = 2; RI1 = 2, RI2 = 2;

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c=3

AG R = 2; RI1 = 3, RI2 = 2;

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Shape = { 1, 2, 2, 1, 1}

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Figure 2: Illustration of Definitions reconvergences, AG and BE in the circuit. From our definitions, RNBE = 2, ROBE (B) = RIBE (E) = 2, RNAG = 2, ROAG (A) = RIAG (G) = 2.5. A brief overview of our technique is provided in Figure 3. /*Reconvergence Calculations - See Section 4.2 */ Perform Reconvergence Analysis on the Circuit. Assign weights to all nodes based on reconvergences. /*End of Reconvergence Calculations*/

4.1

Phase 1 : Minimum Span

The minimum horizontal span L, required by a net is calculated by using a counting argument on the number of sites required for the net. Assume that the source for a net is placed in the center of a 2-dimensional layout. There are 4 sites available around the source at a distance of 1, a total of 12 sites are available at distance at most 2, 24 sites are at distance at most 3 and so on. This is illustrated in Figure 4(a).

/*Bounding Box Estimation - See Section 4 */ For every net N in the netlist do Phase 1: Calculate the smallest bounding box required. Phase 2: Find dilation factor on the net using the reconvergence weights of nodes in the immediate neighborhood. Phase 3: Calculate the grid size which will make specific nodes in the net to be distributed uniformly over the layout. Find Bounding Box Span : Calculate the actual span from the three factors above. End For; /*End of Bounding Box Estimation*/

L=3 N=9

Sinks Sinks N=12

L=2

L=1

N=4

Source

/*Channel Width Estimation - See Section 5*/ For every net N in the netlist do Calculate the number of routing elements required using RISA. End For; Calculate the total number of routing elements. Distribute the routing elements evenly in the layout to obtain maximum channel width. /*End of Maximum Channel Width Estimation*/

L=3 N=24

(a) Sites Around A Logic Block

L=1 N=2

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(b) Sites Around A I/O Block

Figure 4: Finding Minimum Span (L) If we assume that a net N with tN terminals (sinks) is tightly placed by an optimizing placer, then the source can be expected to be in the center and all the sinks tightly placed around it. Clearly, the minimum number of sites required by the net is tN . Assuming such a tight placement, the maximum length of any such sink from the source is calculated by the inequality shown below :

Figure 3: Overview of Our Estimation Methodology Section 4 discusses the wirelength estimation technique in detail and also provides the results and analysis of wirelength estimation. Section 5 discusses channel width estimation and provides the corresponding results.

4.

Source

4 + 8 + 12 + 16 + · · · + 4 · L ≥ tN The inequality sign here is interpreted as “just greater than”. A term at position i in the left side stands for the number of sites available at length i. We are interested in L, the maximum length needed. The right side of the inequality is the number of terminals. Simplifying the expression we get

WIRELENGTH ESTIMATION

In this section, we explain our wirelength estimation technique in detail. Wirelength of every net is dependent on two factors, 1) the number of terminals belonging to the net and 2) how the net interacts with other nets. In the absence of placement information, all that we have is a circuit netlist and the knowledge of the underlying FPGA architecture. We define the wirelength of a net as the bounding box size of the terminals in the net. Half of the bounding box size

2 ∗ L ∗ (L + 1) ≥ tN Solving for L in the quadratic equation, ignoring the negative value, and incrementing by 1 to account for inequality, we get √ L = ( 1 + 2 · tN + 1)/2

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4.1.1

For IO-Nets

and reconvergence lengths. For a given reconvergence Rxy , the origin x has a out-bound reconvergence length which averages to ROxy (x). The destination node y has a in-bound reconvergence length averaging RIxy (y). These two factors capture the connectivity of these cells to the rest of the cells in the circuit. For all nodes x that form the origin of any reconvergence Rx∗ , we calculate the out-weight RO(x) as follows :

The above said argument is valid for logic nets because in the absence of actual placement, this is the best guess possible. This counting argument does not hold well for IO-Nets though. Typically, the IO-Pads feed a lot of combinational logic in its immediate neighborhood. Also, there is no sure way to tell where the IO will be placed along the FPGA boundary. So, we adopt a worst-case approach for IO input nets. We assume that these IOs are placed in one of the possible corners of the FPGA. Thus, no IOs are on the edge along the FPGA. This is obviously not true in real-life as placers also tend to optimize the placement of the IOs. Also, our assumption that all IOs are in the corners will allow only a maximum of 4 IO-Pads. Since we are dealing with worst-case spans, this assumption suffices. To calculate the minimum span of the net under these assumptions, we need to have a different counting argument. The reason is that the IOs placed in a corner of the FPGA obviously do not have as many sites as the logic nets do in their proximity. Assume that the IO-PAD driving the net N is placed as shown in Figure 4(b). Then, there is 1 site at a distance of 1, 2 at a distance of 2 and so on. Thus, the minimum span L is given by the inequality

RO(x) =


the average of all out-bound reconvergences from x. The notation “*” is used to denote the set of all destination nodes for reconvergence with x as the source node. If the node is not the origin of any reconvergence, then its RO(x) = 0. For all nodes y that form the destination of any reconvergence R∗y , calculate the in-weight RI(y) as follows : RI(y) =


RI∗y RN∗y

RW 0 (x) = RI(x) + RO(x)

Solving for L in the quadratic equation we get

4.2




the average of all in-bound reconvergences on y. If the node is not the destination of any reconvergence, then its RI(y) = 0. The raw weight RW 0 (x) of any node in the circuit, regardless of being origin/destination of any reconvergence (or being neither) is defined as :

2 + 3 + 4 + · · · + L ≥ tN

L=

ROx∗ RNx∗


This weight is deemed “raw”, because this weight is factored into different nets based on the net’s properties. Reconvergence based weighing however results in very large weights for flipflops. The reason is that the nets which are driven from flip-flops usually reconverge many times at different levels. In order to prevent such high weights, we scale the weights logarithmically by the LUT-size k (4 in our case) for all FF nodes. Thus the overall weight of a node is:

2 · Nt + 9/4 − 1/2

Phase 2 : Dilation

At the end of phase 1, every net has absolutely minimum span that is dictated by the number of terminals in the net. However, this does not account for the mutual interaction between the nets. Typically, placement tools place logic blocks in order to minimize the total wirelength. As cells are shared by many nets, it is not possible for all cells to be in the minimum span of all their respective nets. So, we introduce a dilation factor into all the spans. This dilation is enforced by the nature of reconvergences in the circuit. Reconvergences in a circuit dictate what kind of “forces” are exerted by cells on each other. If there are no reconvergences in a circuit, placement of any cell is only constrained by the fanin and the fanout of the cell. However, if there are a lot of reconvergences, cells will “compete” with each other for sites in the layout so as to minimize the wirelength. If a particular cell is a destination of many reconvergences, all the origin cells vie for a good position of this cell. Similarly, if a node has many out-bound reconvergences, then this cell is expected to influence the position of many cells in the circuit. Now, we extend this discussion on “forces” and “competition” to nets. Span of any net is most influenced by the immediate neighborhood of the net. The neighborhood includes the cells which feed the source of the net denoted as fanin, the source node of the net itself and all the sinks of the net denoted as fanout. For technology mapped circuits, fanin is restricted to size k, the size of the LUTs. Fanout can have anywhere from 1 cell (for 2-terminal nets) to all the other cells in the circuit. For the example circuit shown in Figure 2, node B has node A as fanin and nodes C,D as fanout. Node A has no fanin and Node G has no fanout. Recollect from Section 3 the definitions of reconvergence

RW (x) = 

log RW 0 (x)/ log 4 RW 0 (x)

; if x is a FF-Node ; otherwise

Now, for a specific net N , let vN be the source of the net. The dilation factor R(N ) of the net is calculated as follows Rf anin (N ) = Rf anout (N ) = R0 (N ) =

RW (x) x∈f anin(vN )

RW (y) y∈f anout(vN )

Rf anin (N ) + Rf anout (N ) + RW (vN ) tN

Essentially the dilation factor R0 (N ) captures the reconvergence at the local neighborhood of the cells in the net. Rf anin (N ) and Rf anout (N ) accounts for the connectivity on the fanin and fanout nodes of the net. The intuition is, if the sum of raw weights of fanin is high, the fanin cells are going to pull the source node towards themselves and thus dilate the net. Similarly, if the sum of raw weights of the fanout is high, the fanout cells are probably going to be pulled away by the respective reconvergences. The scaling by tN calculates the average weight of the neighborhood. If the raw weights of the immediate neighborhood is zero, then there are no reconvergences in the local neighborhood

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4.4

and hence the net is not expected to dilate from the minimum span. If the raw weights are high, then the net is going to be dilated because of the pull from the rest of the circuit. Similar to large weights for flip-flops, nets that start from input pads get very large dilation factors. We empirically found that the reconvergence factor for any input-pad must √ be no greater than 3/ 2 to prevent large dilation of IO-Nets. The modified dilation factor is thus √ 3/ 2 ; if N is a IO-Net R(N ) = 0 R (N ) ; otherwise

The horizontal span of the net N is calculated as HSpan(N ) =

Phase 3 : Uniform Distribution

Nets may further dilate because of the shape of the circuit. Let us consider the shape vector defined in Section 3. Let p be the position in which the shape is the maximum. The nodes in this peak level are denoted by the set SV (p). A big chunk of nodes are at the level p in the circuit. All primary inputs go through many levels of logic and converge at level p. From this level, they again diverge into many more levels of logic before they reach the primary outputs. Thus, the nodes in this level are pulled from both the input and the output side during placement. For such nodes in the peak level, it is safe to assume that these cells are uniformly spread across the device layout in an optimized placement. To the contrary, if these cells were all to be lumped in some region of the layout, there will be many wires either coming in or leaving this region. That will result in an increase of both the wirelength and routing congestion. Since placement tools try to address both wirelength and congestion, at least indirectly, we can assume that these nodes are not going to be lumped into a specific region, but will be uniformly spread across the device. In practice, the circuits may have small bumps in their shapes across different levels in the circuit. Finding one such peak may be insufficient. In our methodology we find three peaks in the circuit shape, namely p1, p2 and p3. Such peaks occur at different levels for different circuits, and may even be in different sequential levels within a circuit. We define a set SP which contains the union of all the cells in levels p1, p2 and p3. We calculate a parameter G which denotes the gridsize as follows : G = N/

max(L, U ) max(L × R(N ), U )

R(N ) < 1 R(N ) > 1

Span(N ) = HSpan(N ) + V Span(N ) = 2 · HSpan(N )

4.5

Experimentation and Results

The wirelength estimation technique was implemented in C and the results were validated with VPR [2]. Six combinational circuits and four sequential circuits were chosen from the ISCAS-89 benchmark suite for evaluation. These circuits are all technology mapped for 4-input LUTs and packed using t-vpack and were obtained from [10]. Among the sequential circuits, bigkey and dsip are pad-constrained (explained in Section 5.2); s38417 has 6 levels of sequential logic; and s298 has very few IOs and Flip-Flops. The combinational circuits differ in their sizes and shapes. The circuits vary in size from 1371 to 6407 cells, 1411 to 6434 nets and 10 to 426 IO-nets. The details of circuits can be readily obtained from [2]. The circuits were first placed and routed using VPR. The tool along with all benchmarks can be obtained from University of Toronto [10]. The tool was launched with no routing segmentation, one logic block per site and one IO-Pad per site for the architecture. All the runtime options for VPR were set at default. The placement file thus produced is used to calculate the bounding box of every single net and the total span V . Then we used our estimation technique on the same set of benchmark netlists and we note down the estimated bounding box spans and the total span M . We calculate the error in estimation as the ratio (V − M )/V . The results are tabulated in column 2 of Table 1. The average error from all the benchmarks is 11.6%. Most of the benchmarks have negative estimation error implying that the estimation method tends to over-estimate the spans of the nets. We then isolated the IO-Nets and calculated error again. The results are noted in column 3 with an average of 12.4%. Usually the nets from input pads tend to spread across the whole device and predicting the span of these IOs within 15% is very useful for interconnect planning. Other interconnect estimation techniques( [9]; [6]) report just these average figures. In addition to the average wirelengths, we also show the accuracy of our estimation technique on a net by net basis. All the benchmarks have large number of nets, and so we group the nets according to their terminal sizes. The results are shown in Figure 5 and Figure 6 for two benchmarks dsip and misex3. We plot two graphs in each figure, i) the ratio of our estimated span to the spans obtained using VPR for particular terminal size and ii) what percentage of nets have that terminal size. Terminal size is plotted on the x-axis. We can see from Figure 5 that between terminal sizes 20 and 100, the ratio is the highest, meaning that the error is highest. However, from the

|SP |

where N is the width of the FPGA device. The formula stems from the fact that if all the cells in SP were assumed to be uniformly spread on a hypothetical grid, each of them will be in exactly one grid position. This grid size should however be scaled with respect to the gridsize in the actual FPGA layout and hence the ratio. For example, if G = 2, then for every grid element in the modified layout, there are 2 ∗ 2 = 4 grid elements in the actual layout. If there is any node x in the fanout of net N such that x ∈ SP , then the span of that net must respect the assumption that these nodes are spread out. To account for this , we bring in a new uniformity factor U . This factor is calculated as : U =



If R(N ) < 1, then the reconvergence factor is ignored. Otherwise, it is used as a multiplication factor with L. In either case, by applying max() of the dilated span and U , we ensure that the cells in the net are spread out according to the uniformity distribution assumption. The vertical span V Span(N ) for net N is defined in a similar manner and hence takes the same value as HSpan(N ). The total span of the net Span(N ) is given as



4.3

Total Span

|SP ∩ f anout(vN )| · G

The intersection finds out how many cells in the fanout of net N are in the peak level, and G is a scaling factor on this to give span in the original layout.

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Ckt

Total Error (%) 2.95 -19.68 -21.45 11.08 4.49 13.44 -5.15 -32.42 4.66 -0.68 11.6%

alu4 apex2 bigkey dsip misex3 pdc s298 s38417 seq spla Totals Average

I/O Error (%) -2.24 29.10 34.47 -4.07 6.77 -14.70 0 -4.84 13.24 -14.34 12.4%

#Nets Err< N4 1299 1616 1699 1367 1170 4051 1837 5955 1522 3329 23845 -

#Nets Err> N 4 223 262 8 3 227 524 94 451 228 361 2194 -

very small fanout and hence accuracy is important in this region. For these regions, the span ratio is within 1.5 for all the circuits. Another region of interest is the rightmost region which represents most terminals per net. Usually nets with such high fanout are from input pads and hence good estimation is required for proper interconnect planning, as mentioned earlier. The number of such nets may be small, but accuracy cannot be sacrificed. With our estimation technique, we have almost flat regions close to ratio of 1 for all the benchmarks as seen in the right extreme of the plot. We also perform analysis of the accuracy of our estimates with respect to the FPGA device size N . We calculate the number of logic nets for which the absolute error in estimation is less than 2, 4, 8, N /4, N /2 and 3 · N /4. These thresholds for errors are on the x-axis and the percentage of nets whose error is less than the threshold is on the y-axis for 5 different benchmarks in Figure 7. From these figures, we can notice that on an average 50% of the nets have error less than 2. That is just one logic block misprediction in each dimension for about half of the nets. For a threshold of 8, we have almost 80% of the nets accounted for. If we allow a threshold of N /4, almost 90% of the nets are covered. In other words, only 10% of the nets were estimated wrongly to extend beyond a quadrant of the device. The actual numbers are shown in columns 4 and 5 of Table 1 for the threshold of N /4 for all the circuits.

Table 1: Estimation of Bounding Box Spans plot below it, we can notice that these nets constitute less than 3% of the total number of nets. We also see that for most of the terminals, the ratio is around 1.0 and the curve is very flat. Only for 2 nets, of terminal sizes 9 and 10, the ratios were 2.6 and these points were lost in smoothing out the graph. 3

dsip − Span Ratio Vs Terminal Size dsip − Ratio of Nets Vs Terminal Size

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