multiplication of both sign-magnitude and two's complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand.
A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier S. M. Aziz and C. N. Basheer School of Electrical and Information Eng. University of South Australia, Mawson Lakes, SA 5095, Australia
Abstract This paper presents a synthesisable VHDL model for a generalised multiplier capable of performing multiplication of both sign-magnitude and two’s complement operands. The multiplier is testable with a constant number of test vectors irrespective of operand word-lengths thereby reducing automatic test generation, simulation and testing times. The model has been used successfully for generating multiplier macros of various operand lengths in different target technologies. A test generation program has been developed for automatic generation of vectors of variable lengths.
1. Introduction Multiplication is the fundamental operation in most digital signal processors. Many applications require multiplication of signed numbers while others require multiplication of unsigned numbers. A high-level parameterised model that can be used to synthesise multipliers capable of performing multiplication of both sign-magnitude and two’s complement numbers would be very useful for automatic generation of such multiplier macros. The multiplier presented in this paper is based on the modified Booth’s algorithm [1]-[3]. This algorithm normally treats the operands as two’s complement numbers and generates the product in two’s complement form. The hardware architecture based on this algorithm has been enhanced in [4] by adding an extra input and a couple of two-input multiplexers in order to use it for multiplication of signed as well as unsigned numbers. Further enhancement made to the sign extension circuitry and the addition of extra inputs has rendered the architecture testable with a constant number of vectors irrespective of operand lengths. Such an architecture is said to be C-testable [5]. In this paper we present a VHDL model based on this testable generalised architecture.
J. Kamruzzaman Faculty of Information Technology Monash University, Australia
2. Architecture Design Several researchers have presented C-testable architectures for multiplication of either sign-magnitude or two's complement binary numbers [6]-[12]. The architectures presented in [8]-[12] are based on the modified Booth's algorithm for multiplication of two's complement numbers only. We have enhanced the architecture presented in [11], in order to perform multiplication of both sign-magnitude and two’s complement operands. To produce an m-by-n generic multiplier, where m and n are the lengths of the operands, we utilize a (m+1) by (n+1) two’s complement multiplier as detailed in [11]. The additional bit for each operand is then manipulated to perform either two’s complement or sign-magnitude multiplication [4]. Two MSB manipulation blocks, as shown in Fig. 1, are incorporated into the architecture which supply the (m+1) and (n+1)-th inputs individually. The A input is the m-th bit (or n-th bit) of the operand. The MS input is used to select either sign-magnitude operation (logic 0) or two’s complement operation (logic 1). The A+ and TM inputs are used for testing purposes and should be driven low during normal multiplication operation. A MS
MSB
A+ TM
Figure 1. MSB manipulation block
3. C-Testability The inclusion of the two MSB manipulation blocks required reanalysis of the overall C-testability of the architecture. In [11] a set of 19 test vectors and six extra inputs were required for testing the multiplier. Assuming a single stuck-at fault model for the MSB manipulation block, a further three test vectors and three test inputs are
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
required for C-testability of the generic architecture presented in this paper. Table 1 details the required test vectors for an 8 by 8-bit multiplier. The vectors are extended (as shown by an underscore) for larger operands. Test vectors 1, 19 to 22 test the MSB manipulation blocks. The remaining test vectors along with 1 and 19 test all other components as described in [11]. Table 1. Test-vector set Test 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
X+.X 0000 0000 1000 0000 1111 1111 1000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0101 0101 0101 0101 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 1111 1111 0000 0000 1111 1111 1111 1111 0100 0000 1100 0000 1100 0000
X0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 0
Y+.Y 0000 0000 0101 0101 0101 0101 1010 1010 1111 1111 0011 0011 0101 0011 0100 0100 1100 1100 0011 0011 0011 0011 1100 1100 1010 1010 1010 1010 1001 1001 0110 0110 0110 0110 1001 1001 1111 1111 0100 0000 1100 0000 1100 0000
Y0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0
MS.TM.E 0 0 0000 0 1 0000 0 1 1111 0 1 1111 0 1 1100 0 1 0011 0 1 0011 0 1 1100 0 1 0110 0 1 1001 0 1 0011 0 1 1100 0 1 1100 0 1 0000 0 1 1111 0 1 0000 0 1 1111 0 1 1001 1 1 0000 0 1 1100 0 0 1100 1 0 1100
C-Testable test patterns. The application also interfaces with VHDL Simili™ to allow automatic compilation and simulation of our VHDL multiplier model. We have used the exhaustive test pattern generation facility combined with the VHDL Simili interface to ensure the correctness of our VHDL model through exhaustive testing. Given that we have validated the model for a number of multiplier sizes, it is only necessary for the user to test their synthesised multiplier with the 22 C-test vectors presented in Table 1. The developed application enables users to automatically generate the Ctest vectors of appropriate lengths. As a visual example of our multiplier’s operation, waveform results of both sign-magnitude and two’s complement multiplication are shown in Figures 2 and 3 as produced by ModelSim™. Consider the multiplication between 82 (hex) and 3C (hex). Figure 2 shows this situation with MS high, specifying sign-magnitude multiplication. The operands are therefore taken as 130 and 60 (in decimal), producing a product of 7800. Figure 3 shows the same multiplication when MS is low, specifying two’s complement multiplication. In this case the operands are taken as -126 and 60, producing a product of -7560.
Figure 2. Sign-magnitude multiplication
4. VHDL Modelling A hierarchical VHDL model of the generalised architecture described above has been developed. The design has been made parameterised in terms of the widths of the two operands using the ‘generic’ VHDL construct. This allows instant automatic generation of multipliers of arbitrary size. The model is technology independent. This allows synthesis software to target the design to most mainstream Programmable Logic Devices (PLD). A top-level VHDL module is employed to instantiate multiple Modified Booth Encoder (MBE) blocks, multiplexer-complementers (MC), full-adders (FA) and two MSB manipulation blocks. The details and arrangement of MBEs, MCs and FAs within the architecture are described in [11].
5. Test Generation and Simulation A Visual C++ application has been developed to facilitate automatic generation of multipliers of arbitrary size, and for automatic generation of both exhaustive and
Figure 3. Two’s complement multiplication
6. Synthesis The developed VHDL model requires no further modification to successfully target a PLD of choice. Using Leonardo Spectrum™ synthesis software, the generic modified Booth’s multiplier model, a signed only modified Booth’s multiplier model, and an unsigned only (pencil and paper) multiplier model were synthesised to several PLDs, each in 8-by-8, 16-by-16 and 32-by-32 bit configurations. When comparing the maximum delay performance between the three architectures, little difference was observed. For example, a 32-by-32-bit version of each multiplier was synthesised to a Xilinx Virtex-II FPGA. The generic, signed-only and unsigned-only architectures incurred a maximum delay of 33.06, 32.71 and 31.50 ns
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
respectively. Despite the modified Booth’s architectures producing only half the number of partial products compared to the pencil and paper architecture, no carry look-ahead techniques have been employed to take advantage of this. The generic architecture will compare favourably against the pencil and paper architecture if fast carry look-ahead techniques are employed [12]. The generic model becomes attractive however when we consider hardware requirements. Table 2 shows the required gate count for various configurations of the unsigned-only, signed-only and generic multipliers. Table 2. Multiplier Gate Requirements Size
8x8 16x16 32x32 64x64
Pencil & Paper (Unsigned) 400 1,696 6,976 28,288
Modified Booth’s (Signed) 431 1,513 5,585 21,409
Combined (Unsigned & Signed) 831 3,209 12,561 49,697
Modified Booth’s (Generic) 601 1,791 6,109 22,413
The third column shows the total gate count of separate unsigned and signed-only multipliers. Considering a 32by-32 bit multiplier, our single-architecture generic multiplier requires 51.4% less gates than the twoarchitecture alternative.
Figure 4. RTL Schematic
Figure 5. Technology Schematic
Figures 4 and 5 show a synthesized 4-by-4 bit version of our generic multiplier. Initially the VHDL model is elaborated by synthesis software to produce a RegisterTransfer Level (RTL) schematic, as shown in Fig. 4. This elaboration is then mapped to the desired target device’s resources with the result shown in Fig 5, which is then used to configure the targeted programmable device.
7. Conclusions A synthesisable VHDL model of a generalised multiplier capable of performing multiplication of signmagnitude and two’s complement numbers has been presented. The multiplier is testable with only 22 vectors. An application has been developed that allows automatic generation of multipliers of arbitrary size and automatic generation of accompanying C-test vectors.
8. References [1] J. J. F. Cavanagh, Digital Computer Arithmetic Design and Implementation, McGraw-Hill, Inc., New York, 1985. [2] M. Roorda, “Method to reduce the sign bit extension in a multiplier that uses the modified Booth algorithm”, Electronic Letters, Vol. 22, No. 20, 25th September 1986, pp. 1061-1062. [3] N. Burgess, “Removal of sign-extension circuitry from Booth's algorithm multiplier-accumulators”, Electronic Letters, Vol. 26, No. 17, 16th August 1990, pp. 1413-1415. [4] S. M. Aziz, Z. Rouf and J. Kamruzzaman, “Signed and unsigned multiplication using a single cellular array”, Proc. of the 7th Int. Symp. on IC Technology, Systems and Applications, Singapore, Sept. 10-12, 1997, pp. 569-572. [5] D. Friedman, “Easily testable iterative systems”, IEEE Trans. Comput., Vol. C-22, Dec. 1973, pp. 1061-1064. [6] J. P. Shen and F. J. Ferguson, “The design of easily testable VLSI array multipliers”, IEEE Trans. Comput., Vol. C-33, No. 6, June 1984, pp. 554-560. [7] A. R. Takach and N. K. Jha, “Easily testable gate-level and DCVS multipliers”, IEEE Trans. Computer-Aided Design, Vol. 10, No. 7, July 1991, pp. 932-942. [8] W. A. J. Waller and S. M. Aziz, “A C-testable parallel multiplier using Differential Cascode Voltage Switch (DCVS) Logic”, IFIP Trans. A, Vol. A-42, 1994, pp. 133-142. [9] S. M. Aziz, “A C-testable modified Booth array multiplier”, Proc. of Int. Conf. VLSI Design, New Delhi, India, January 4-7, 1995, pp. 278-282. [10] K. O. Boateng, “Design of C-testable multipliers based on modified Booth algorithm”, Proceedings of 6th Asian Test Symposium, Japan, 1996, pp. 42-47. [11] S. M. Aziz and I. Ahmed, “Easily testable array multiplier design using VHDL”, Malaysian Journal of Computer Science, Vol. 11, No. 2, Dec. 1998, pp. 1-7. [12] D. Gizopoulos, “C-Testable Modified-Booth Multipliers”, Journal of Electronic Testing: Theory and Applications, Vol. 8, No. 3, June 1996, pp. 241-260.
Proceedings of the First IEEE International Workshop on Electronic Design, Test and Applications (DELTA’02) 0-7695-1453-7/02 $17.00 © 2002 IEEE
