A VARIABLE GAIN CMOS PHASE SHIFTER FOR PHASED ARRAY ANTENNA APPLICATIONS Dipankar Mitra, Palash Roy, and Debasis Dawn Department of Electrical and Computer Engineering, North Dakota State University, NDSU Dept. 2480, PO Box 6050, Fargo, ND, 58108-6050; Corresponding author:
[email protected] Received 4 July 2016 ABSTRACT: This letter presents for the first time the development of a variable gain CMOS phase shifter using 0.18 mm CMOS process in the S-band frequencies to be integrated with conformal phased array beamforming antenna for smart communication radar applications. The vector modulator based phase shifter has an integrated variable gain amplifier codesigned with the phase shifter circuitry in order to be capable of controlling both phase and gain simultaneously which is necessary to recover the degraded radiation pattern due to the conformal shaping of the phased array antenna. The phase shifter achieves measured continuous phase shift of 3038 along with measured 7 dB gain control range over 2–2.60 GHz and an insertion loss of 7.12 dB at 2.2 GHz. The measured DC power consumption of the phase shifter is 34.2 mW from a 2 V supply with a smaller chip area of 1.12 mm2 including all pads. C 2016 Wiley Periodicals, Inc. Microwave Opt Technol Lett 59:324– V 328, 2017; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.30283 Key words: CMOS; phase shifter; beamformer; vector modulator; variable gain; conformal; phased array antenna 1. INTRODUCTION
Phased array systems have been extensively used in wireless communications applications like aerospace designs, wearable antenna, spacesuit, mobile devices etc. to achieve electronic beam forming and thus helping to avoid huge mechanical arrangement of phase rotation of the antenna systems. However, the radiation pattern of a phased array antenna gets changed
from its original pattern with degradation of performances such as radiation angle and gain due to its incident on a nonplanar surface depending on the bending radius of the surface [1]. Beam steering concept can be implemented to correct the degraded radiation pattern of the antenna array by proper phase correction in each element of the antenna array [2] and using a phase shifter array shown in Figure 1 can do this phase correction. Thus phase shifter has become an intrinsic part of the phased array antenna system. Because of significant advancement in fabrication process and rapid device scaling, silicon-based CMOS radio frequency integrated circuits (RFICs) has become a very effective and acceptable solution for phased array systems. There are many ways to implement phase shifters. Some of the common and popular phase rotator architectures are switched line phase shifters [3], loaded-line phase shifters [4], loaded-line phase shifters [5] and vector-modulator based phase shifters [6]. In this letter, the single CMOS phase shifter of Figure 1 has been developed in the S-band frequency using 0.18 mm CMOS process to control the both phase (/1, /2,.) and amplitude (A1, A2,. . .) of the phase shifter output signal. A vector-modulator, a passive hybrid, two active baluns and a variable gain amplifier (VGA) along with two buffer stages are integrated to build this unit-cell CMOS phase shifter. As an advancement of the work in [7], in this work the proposed phase shifter architecture is fabricated and characterized to find out its suitability to be integrated with phased array antenna systems. The measurement results show that the proposed phase shifter has achieved simultaneous phase and gain control ability. This letter is arranged with circuit design procedure in Section 2, measurements in Section 3 followed by conclusion in Section 4. 2. CIRCUIT DESIGN PROCEDURE
The block diagram of the proposed CMOS phase shifter is shown in Figure 2. A double balanced Gilbert cell based vectormodulator circuitry is used as the phase rotator, which is shown
Figure 1 CMOS integrated beamformer with conformal phased array antenna for wireless communications. [Color figure can be viewed at wileyonlinelibrary.com]
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Figure 2 Block diagram of proposed CMOS integrated phase shifter
in Figure 3. Four RF signals with phases 08 (I1), 908 (Q1), 1808 (I2), and 2708 (Q2), respectively, are fed to the upper differential pair transistors of the double balanced Gilbert cell as shown in Figure 3. To achieve the continuous phase shift, the vector components of these RF signals are needed to be added as shown in Figure 4 and the amplitude of these RF signals need to get controlled via control voltages through four tail transistors used as the control ports named as control 1, control 2, control 3 and control 4, respectively shown in Figure 3. By applying appropriate control voltages to these control ports desired phase shift can be achieved. Now, to generate the four input RF signals that fed to the vector-modulator, an on-chip passive hybrid and two active baluns are used. The quadrature splitter is a passive LC hybrid, as shown in Figure 5(a), which is used to generate in-phase (I) and quadrature (Q) signals with a 908 phase difference. This
passive hybrid provides a loss of 3 dB. Both I and Q signals are fed to two active baluns to produce two differential signals from each balun. The active balun is designed with a common source (CS)/common-gate (CG) topology, as shown in Figure 5(b). This active balun compensates the 3-dB loss incurred in passive hybrid. To achieve variable gain capability, a variable gain amplifier (VGA) is used after the vector-modulator. The VGA, shown in Figure 3, is basically a differential amplifier. The gain of the VGA is controlled by its tail transistor, which actually works as a voltage-controlled variable resistor. The equivalent circuit model of the VGA is shown in Figure 6. From the equivalent circuit model of VGA, the output voltage of the VGA can be written as follows: VO 5 2I2 RD 52 gm ðV1 2VS Þ RD
(1)
Z5R6 2JXC1
(2)
As XC1 is very high, I1 0. Now, the drain voltage of the VGA tail transistor is given by VS 5I2 R7 5 2
R7 VO RD
(3)
Using the Eqs. (1)–(3), the output voltage of the VGA can be written as follows: VO 5 2
gm RD V1 ð1 1 gm R7 Þ
(4)
Using Eqs. (1), (3), and (4), the voltage gain of the VGA can be written as following:
Figure 3 Circuit schematic of the vector-modulator integrated with the VGA and buffers
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Figure 4 Phase control diagram. [Color figure can be viewed at wileyonlinelibrary.com]
Figure 6 Equivalent circuit model of VGA
GVGA 5VO =V1
The resistor R7 is a voltage-controlled variable resistor, which is given by
52
gm RD ð11gm R7 Þ
(5) R7 5
b ð Vvga
gain
1 2 VT 2 VDS Þ
(6)
where b5ln Cox WL , Vvga_gain is the gate bias voltage of VGA tail transistor (VGA gain in Fig. 3), VT is the threshold voltage of the VGA tail transistor, ln is the electron mobility, and W and L are the width and length of the VGA tail transistor gate, respectively. From Eq. (6), it is noticeable that the resistor R7 is dependent on Vvga_gain and the gain of the VGA is dependent on R7, which is noticeable from Eq. (5). So, it is possible to vary R7 by tuning Vvga_gain. Thus, variable gain feature of the integrated phase shifter circuit is achieved. The phase of the vector-modulator output can be affected by the VGA if both of them are not designed properly. To get an idea how the vector-modulator (VM) phase gets affected by the VGA, a thevenin equivalent circuit of VM output with VGA input impedance, as shown in Figure 7, has been analyzed. The input impedance of VGA was given by Eq. (2). The output impedance of vector modulator is given by (7). Z1 5R 7 2 JXC2
Figure 5 (a) Schematic of passive hybrid. (b) Schematic of active balun
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(7)
Figure 7 Thevenin equivalent circuit of VM output with VGA input impedance
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Figure 8 Micrograph of the fabricated CMOS phase shifter die with size of 1.5 mm 3 0.75 mm. [Color figure can be viewed at wileyonlinelibrary.com]
Figure 11 Measured input and output return loss of the phase shifter. [Color figure can be viewed at wileyonlinelibrary.com]
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi R6 2 1XC1 2 where jG1 j5 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ðR6 1R7 Þ2 1ðXC2 1XC1 Þ2 XC2 1XC1 XC1 2tan 21 /G1 5 tan 21 R6 1R7 R6
(12)
(13)
The circuit was designed in that way to keep the ratio R7/R6 1 and XC2/XC1 1. So, Eqs. (12) and (13) can be written as following: jG1 j 1 and /G1 0 Figure 9 Measured frequency characteristics of the phase variation of the CMOS phase shifter by changing phase control signals. [Color figure can be viewed at wileyonlinelibrary.com]
V1 5jVVM j
Vi 5 jVVM j /u
(8)
R6 2JXC1 /u ðR6 1R7 Þ2JðXC2 1XC1 Þ
(9)
where VVM is the output voltage of the vector-modulator and u is the phase of the vector-modulator output signal. Now, the output of the VGA is given by following: VVGA 5 jGVGA j jVVM j
R6 2JXC1 /u ðR6 1R7 Þ2JðXC2 1XC1 Þ
VVGA 5 jGVGA j jVVM j jG1 j /ðu 1G1 Þ
So, the vector-modulator phase and gain do not get affected with the variation of VGA gain. Now, the output of the VGA can be written as follows: VVGA 5
gm RD jVVM j /u 1 1 gm R7
(14)
The VGA is followed by source follower as buffers in order to terminate the phase shifter output to 50 X. To ensure the minimum chip area and DC power consumption, all the circuit blocks in the Figure 2 are designed using codesign methodologies while taking into appropriate consideration of the input and output complex impedances of each block for better RF performances as integrated circuit.
(10) (11)
3. MEASUREMENTS
The phase shifter chip is fabricated using 0.18 mm CMOS process. The micrograph of the fabricated phase shifter die is
Figure 10 Measured gain response of the phase shifter. [Color figure can be viewed at wileyonlinelibrary.com]
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Figure 12 Measured phase variation response over gain variation at a particular phase setting. [Color figure can be viewed at wileyonlinelibrary.com]
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TABLE 1 Performances Comparison Ref. Frequency (GHz) Conversion gain (dB) Gain control range (dB) Phase range (o) Area (mm2) DC power (mW) Process technology
[8]
[9]
[10]
[11]
This Work
2.5–3.2 22.5 – 360 4.16 60 0.18 mm CMOS
0.5–6 8–10 – 360 1.21 27.5 0.13 mm CMOS
5.15–5.7 29 – 360 0.9 0 0.6 mm GaAs MESFET
4–6 22.2 – 90 0.5 0 0.6 mm GaAs MESFET
2–2.60 27.12 7 360 1.12 (with pads) 34.2 0.18 mm CMOS
shown in Figure 8. The dimensions of the chip are 1.5 mm 3 0.75 mm including all bondpads. The phase shifter is measured using an Agilent ENA E5071C network analyzer with frequency sweeping from 100 KHz to 8.5 GHz. Cascade Microtech probe station is used for probing the phase shifter die. ACP (Air Co-planar) series GSG probes are used for probing the RF input and output of the phase shifter die. All the measurements are done with two-port SOLT (Short, Open, Load, Thru) calibration to the ACP probe tips. Impedance Standard Substrate ISS 101-190 C is used as calibration substrate for calibration. The measured phase response of the phase shifter is presented in Figure 9. The phase shifter has demonstrated a continuous phase shift of 3038 over the 2–2.60 GHz frequency. The phase shift is measured at the highest gain setting. The phase shifting characteristics are achieved by changing the bias voltages (control signals) of the tail transistors of the vector modulator of the phase shifter. The measured gain response of the integrated phase shifter is depicted in Figure 10. The phase shifter has demonstrated a measured insertion loss of 7.12 dB at 2.2 GHz along with a gain variation of 7 dB at a particular phase setting over 2– 2.60 GHz. The gain variation of the phase shifter is achieved by varying the tail transistor bias voltage of the VGA. The measured input return loss is
