Active Power Decoupling Method for Single-Phase ... - IEEE Xplore

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 8, AUGUST 2016

Active Power Decoupling Method for Single-Phase Current-Source Rectifier With No Additional Active Switches Yao Sun, Member, IEEE, Yonglu Liu, Mei Su, Xin Li, and Jian Yang, Member, IEEE

Abstract—This paper proposes an active power decoupling method without adding additional active switches for single-phase current source rectifiers. Two identical decoupling capacitors connected across the two bridge arms operate alternatively to buffer the ripple power at twice the line frequency. First the operational principle of the proposed circuit is presented. Thereafter, a hybrid modulation method, in which input current synthesis and ripple power buffering can be carried out simultaneously, is developed. Moreover, a new effective closed-control strategy is presented, in which the decoupling control is responsive for regulating dc-link current and the rectification control is in charge of power factor correction as well as maintaining the dc component of the decoupling capacitor voltages at a given level. Consequently, complete ripple power decoupling is achieved and sine input current is obtained. Finally, the theoretical analysis is favorably verified by the simulations and experimental results. Index Terms—Active power decoupling, closed-loop control, current-source rectifier, ripple power.

I. INTRODUCTION INGLE-PHASE power converters are dominant in lowpower applications such as residential and industrial power supplies [1]. Unfortunately, the inherent ripple power at twice the line frequency results in undesirable low frequency components in the dc-link voltage/current and even ac current. That degrades the system performances, for examples, reducing the maximum power point tracking efficiency of the photovoltaic (PV) panels [2], generating low-frequency flicker of the lightemitting diodes [3]–[5], causing overheating of batteries [6], [7], and shortening fuel cell’s lifetime [8]. It is intuitive to restrict the ripple within allowable limit by significantly increasing the volume of the dc-link capacitor/inductor, which is simple and easy to implement. However, that is adverse to the power density, cost, and reliability, which is unacceptable especially for volume-critical, weight-critical, and/or lifetime-critical applica-

S

Manuscript received June 24, 2015; revised August 21, 2015 and September 22, 2015; accepted October 20, 2015. Date of publication October 26, 2015; date of current version March 2, 2016. This work was supported by the National Natural Science Foundation of China under Grant 61573384, the National Hightech R&D Program of China (863 Program) under Grant 2012AA051603, the Hunan Provincial Natural Science Foundation of China under Grant 14JJ5035, and the Project of Innovation-driven Plan in Central South University. Recommended for publication by Associate Editor R. Redl. The authors are with the School of Information Science and Engineering, Central South University, Changsha 410083, China (e-mail: yaosuncsu@ gmail.com; liuyonglu@ csu.edu.cn; [email protected]; lixin_@csu. edu.cn; [email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2015.2494742

tions, such as electrical vehicles, aircraft power system, and/or PV system [2]. To eliminate the aforementioned deficiencies, active decoupling methods, in which the ripple energy is temporarily stored in additional passive component(s) with long lifetime and small volume, are proposed. They have been extensively studied in the last few years [9]–[40] and can be categorized into two groups in terms of the circuit structures: independent and dependent active decoupling methods. In the former, usually the decoupling circuits are based on full-bridge [10]–[15] or half-bridge [16]–[22] circuit structures. They are connected into the dc link of the original circuit in series [10]–[12] or parallel [13]–[22]. Among of them, in [21] and [22], the dc-link capacitor is split into two identical ones to buffer the ripple energy as well as filter high frequency harmonics. In independent concept, decoupling circuits and original circuits are noninterfering, which leads to flexible designs in control and modulation strategies. However, this kind of decoupling method usually involves a lot of additional power semiconductor devices, which may be not a cost-effective solution. The dependent active decoupling approaches benefit from fewer power semiconductor switches. As a result, it has the advantages in cost and reliability. Its main idea lies in sharing the semiconductor devices between the decoupling circuit and the original circuit. The shared switching semiconductors play dual roles of power decoupling and rectification/inversion. Thus, power semiconductor devices of the decoupling circuit can be reduced partially [23]–[32] and even entirely [33]–[40]. In [23]–[28], a whole bridge arm is shared by the decoupling circuit and the original circuit, which can be termed as horizontal multiplexing method. In [29] and [30] two upper/lower switches of the original inverter/rectifier are shared, which can be termed as vertical multiplexing method. In [31] and [32], the circuit configuration is based on the H-bridge differential circuit, and the ripple energy is buffered by two identical capacitors which are also used as ac filters. Decoupling solutions requiring no additional power semiconductors can be further dived into two kinds. In one of the solutions, the decoupling capacitors are used for both energy storage and filtering [33]–[36]. In the other, the decoupling capacitors mainly serve for the purpose of energy storage [37]–[40]. The former is usually formed by differential circuits, such as buck differential inverter [33] and boost differential converters [34], [35]. They mitigate the ripple power by controlling the common mode voltages of the output filter capacitors. As for the latter, it is realized by completely sharing switches with the original circuit. However, the

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SUN et al.: ACTIVE POWER DECOUPLING METHOD FOR SINGLE-PHASE CURRENT-SOURCE RECTIFIER

Fig. 2.

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Equivalent circuit model of the proposed converter.

also proposed, which could accurately decouple the ripple power irrespective of the system parameter deviations. The proposed circuit and control algorithm are finally verified by simulations and experimental results. II. CIRCUIT CONFIGURATION AND OPERATING PRINCIPLE A. Circuit Configuration

Fig. 1.

Single-phase CSCs. (a) Conventional circuit. (b) Proposed circuit.

locations of the decoupling capacitor are different from each other. In [37], the decoupling capacitor is series with the grid voltage, which may limit the viable operating range of the dclink voltage. In [38], the decoupling capacitor is connected to the center tap of the isolation transformer, which increases the transformer current and makes the design of the transformer complex. The decoupling capacitors in [39] and [40] are both in series with the battery/dc-link capacitor, which increases the switching voltage stress to be the sum of the dc-link voltage and the decoupling capacitor voltage. It could be found that usually some penalty has to been paid for reducing active switches. According to the review of the exiting active decoupling methods, the majority of the existing solutions are developed for voltage-source converters, only a few of them are oriented to current-source converters (CSCs) [12], [27], [30], [32]. In addition, all the decoupling solutions proposed in [12], [27], [30], and [32] need additional two active switches and two diodes. What is worse, the dc-link current is always flowing through half of the additional semiconductor devices of the decoupling circuit in [12] and [30], which results in significant conduction losses. To overcome aforementioned shortcomings of the existing active decoupling methods, this paper proposes a decoupling solution for current-source rectifier without requiring additional active switches. The decoupling of the double frequency pulsating power is accomplished by employing two small film capacitors. The decoupling capacitors work alternatively to absorb/release the ripple power. A closed-loop control method is

The circuit topologies of the conventional single-phase CSC and the proposed one with power decoupling function are shown in Fig. 1(a) and (b), respectively. Compared with the conventional CSC, the proposed requires two additional identical capacitors to buffer the ripple power (C1 and C2 ) and two more diodes (D3 and D4 ) to guarantee the safety operation of the converter during start-up and stop processes. B. Operating Principle Assume that the source ac voltage ug and current ig are expressed as ug = V cos(ωt)

(1)

ig = Icos(ωt + ϕ)

(2)

where V and I are, respectively, the amplitudes of ac voltage and current, ω is angular frequency, and ϕ is the displacement angle. Then, the instantaneous power pac of the grid is expressed as pac = ug ig = V Icos (ϕ) /2 + V Icos (2ωt + ϕ) /2       P¯

(3)

p˜

where P¯ is the average power, i.e., the load power. P˜ is the ripple power, which should be buffered by the decoupling capacitors. Suppose the power losses caused by the semiconductor devices and the input filters are ignored and dc-link current is constant. If the ripple power is completely buffered by the decoupling capacitors C1 and C2 , according to power balance, the equivalent series voltage us should be us =

P˜ V Icos (2ωt + ϕ) = . idc 2idc

(4)

The decoupling capacitors absorb/release ripple energy when us is positive/negative. From the view of voltage–second balance, us is used to ensure that the net voltage–second of the dc-link inductor Ldc is zero over each switching period Ts .

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Fig. 3.

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 8, AUGUST 2016

Switching states in the proposed single-phase CSC. TABLE I OPERATION MODES AND CORRESPONDING SWITCHING STATES

Then, only a small dc-link inductor is required to filter high frequency harmonics caused by switches. According to Fig. 1(b), the equivalent circuit model of the proposed converter is illustrated in Fig. 2. And ur is equivalent to ur c which is the average value of the rectified output voltage over a switching period in the conventional single-phase CSC. III. SWITCHING STATES AND MODULATION SCHEME A. Switching States In conventional single-phase CSC, each switching state involves two active switches and only four switching states are

available. But in the proposed CSC the number of the conduction switches in each switching state can be one, two, or three, which enriches the available switching states greatly. To avoid misgating-on of diodes D1 and D2 , the decoupling capacitor voltages u1 and u2 are always controlled to be higher than |ug |. Under the aforementioned conditions, 11 available switching states are shown in Fig. 3. In the figures, T = (S1 S2 S3 S4 ) denotes the states of the four active switches, where Si = “1”(i = 1, 2, 3, 4) indicates the corresponding switch Si is turned on and “0” turned off. The switching states in Fig. 3 are further divided into four groups in terms of functions. First group includes switching

SUN et al.: ACTIVE POWER DECOUPLING METHOD FOR SINGLE-PHASE CURRENT-SOURCE RECTIFIER

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Fig. 4. Distributions of d1 , d2 , and d3 in one switching period T s . (a) Charging. (b) Discharging when T d = 0. (c) Discharging when T d = 1.

states 1 and 2, in which the ac side is connected into the dc loop and the decoupling capacitors C1 and C2 are both bypassed. This group is exclusively used for synthesizing the input current. Second group consists of switching states 3, 4, 5, and 6, in which the ac side is disconnected from the dc loop on the right side. This group is exclusively used for decoupling the ripple power. Third group is composed of switching states 7, 8, 9, and 10, in which the ac-side capacitor Cf and one of the decoupling capacitor C1 or C2 are connected in series to supply the dc loads. This group is carried out to achieve the goal of input current synthesis and ripple power buffering simultaneously. Forth group is composed of switching states 11. This group provides the freewheeling path for the dc-link current idc . B. Modulation Scheme To accomplish the dual purposes of input current synthesis and ripple power mitigation, a hybrid modulation method is developed. During each line frequency period ac current reference ii ref , which is the average value over a switching period Ts and synthesized by dc-link current idc , is classified as two main sectors: ii ref > 0 and ii ref ≤ 0. And each main sector is further divided into two modes according to the operations of decoupling capacitors, i.e., charging operation (us ref > 0) and discharging operation (us ref ≤ 0). Therefore, there are four basic operational modes and three possible switching states exist in each mode, which are summarized in Table I. In discharging modes, if the sum of the durations of synthesizing input current and decoupling is more than unity, Td = 0; or Td = 1. d1 , d2 , and d3 are duty ratios of the corresponding operational state and d1 + d2 + d3 = 1. To reduce the dc-link current ripple, the distributions of d1 , d2 , and d3 in each switching period Ts are shown in Fig. 4.

Fig. 5. Operating waveforms for the proposed single-phase CSC in steady state by ignoring the effect of input filters.

According to the developed hybrid modulation method, steady-state operating waveforms for the proposed single-phase CSC are shown in Fig. 5. Four operational modes are briefly introduced as follows. 1) Energy Absorbed Modes: Modes I and III are energy absorbed modes, in which us ref is always positive. In Mode I, ac current reference ii ref is positive and capacitor C1 is charged; whereas in Mode III ac current reference ii ref is negative and capacitor C2 is charged. Here, Mode I is taken for an example to analyze the operational case. According to Fig. 4(a), in each switching period Ts there are three switching states: Interval 0 (0 ≤ t < d1 Ts ): Switching state 7 in Group III is carried out. Then, switch S4 is turned on and switches S1 , S2 , and S3 are turned off. The power in ac grid is transferred to the capacitor C1 and the load. Interval 1 [d1 Ts ≤ t < (d1 + d2 )Ts ]: Switching state 1 in Group II is carried out. In this state, switches S1 and S4 are turned on and S2 and S3 are turned off. In this state, the decoupling capacitors are bypassed and the power in the ac side is transferred to the load, which is identical to that in the conventional CSC. Interval 2 [(d1 + d2 )Ts ≤ t ≤ Ts ]: Switching state 11 in Group IV is carried out. Then, switches S1 and S2 are turned on and S3 and S4 are turned off. Both of the capacitors C1 and C2

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IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 8, AUGUST 2016

and ac grid are bypassed. Here, switching state 11 (T = 1100) is adopted rather than T = 0011 to reduce the conduction power losses. In other modes, the freewheeling is also accomplished by employing switching state 11 for the same purpose. 2) Energy Released Modes: Modes II and IV are energy released modes, in which us ref is always negative. In Mode II, ac current reference ii ref is positive, and capacitor C2 is discharged; whereas in Mode IV ac current reference ii ref is negative and capacitor C1 is discharged. In each discharging mode, there are two subintervals, i.e., Sub-I and Sub-II. That is, the absorbed energy will be released by twice. In the following, Mode IV is taken for an example to analyze the operational case. According to Fig. 4(b) and (c), in each switching period Ts there are three switching states: Interval 0 (0 ≤ t < d1 Ts ): If Td = 0, switching state 8 in Group III is carried out. Then, switches S1 , S2 , and S3 are turned on and S4 are turned off. The power from ac grid and the capacitor C1 is transferred to the load. If Td = 1, switching state 2 in Group I is carried out. In this state switches S2 and S3 are turned on and S1 and S4 are turned off. This state is identical to that in the conventional CSC. Interval 1 [d1 Ts ≤ t < (d1 + d2 )Ts ]: Switching state 4 in Group II is carried out in despite of the value of Td . In this state switches S1 , S3 , and S4 are turned on and S2 are turned off. This state contributes to discharging capacitor C1 . Interval 2 [(d1 + d2 )Ts ≤ t ≤ Ts ]: If Td = 0, switching state 2 is carried out again, i.e., the duration of synthesizing input current is split into two pieces in a switching period. If Td = 1, switching state 11 is carried out for freewheeling.

as

⎧ ⎪ ⎨ u ¯20 − u1 =  ⎪ ⎩ u ¯20 +

V I cos(2ω t+2ϕ) 2ω C

Mode IV − Sub − I

V I cos(2ω t+2ϕ) 2ω C

Mode IV − Sub − II.

Similar analysis can be done on C2 . Then, u2 is expressed as ⎧ sin(ϕ) ⎪ ¯20 − V I2ω Mode I ⎪ C ⎪ u ⎪ ⎪  ⎪ ⎪ t+2ϕ) ⎪ ⎪ u ¯20 − V I cos(2ω Mode II − Sub − I ⎪ 2ω C ⎪ ⎪ ⎪  ⎪ ⎪ t+2ϕ) ⎪ ⎨ u ¯20 + V I cos(2ω Mode II − Sub − II 2ω C u2 =  (9) ⎪ ⎪ 2 + V I sin(2ω t+ϕ) ⎪ u ¯ Mode III ⎪ 0 2ω C ⎪ ⎪ ⎪  ⎪ ⎪ VI ⎪ ⎪ u ¯20 − 2ω Mode IV − Sub − I ⎪ C ⎪ ⎪  ⎪ ⎪ ⎩ VI u ¯20 + 2ω Mode IV − Sub − II. C Apparently, u1 and u2 are both piecewise functions. Moreover, u1 can be obtained by shifting u2 to the right with π rad/s. It is also founded that for each decoupling capacitor the discharging durations of Sub-I and Sub-II are, respectively, (π/4 − ϕ/2)/ω and (π/4 + ϕ/2)/ω during each line frequency period. According to the aforementioned analysis and Fig. 4, the synthesized current ii and the equivalent voltage us provided by C1 or C2 are obtained as follows: sgn(ii ref )(d1 + d2 )idc Mode I or III ii = sgn(ii ref ) [d1 + (1 − Td )d3 ] idc Mode II or IV

C. Expressions of Decoupling Capacitor Voltages As for the capacitor C1 , as can be seen from Fig. 5, in Mode I it is charged to absorb the ripple power. Therefore, the following differential equation is satisfied: C

du1 u1 = p˜ac dt

(5)

⎧ d1 u 1 ⎪ ⎪ ⎪ ⎨ [d + (1 − T )d ] u 2 d 1 2 us = ⎪ d1 u 2 ⎪ ⎪ ⎩ [d2 + (1 − Td )d1 ] u1

u1 =

(10) Mode I Mode II Mode III Mode IV

(11)

where sgn() is the sign function.

where u1 is the voltage of capacitors C1 . By integrating both sides of (5) with respect to time, u1 can be expressed as 

(8)

IV. MODELING AND CONTROL A. Modeling

u ¯20

V Isin (2ωt + ϕ) Mode I + 2ωC

(6)

where u ¯0 is the dc component of u1 . In Modes II and III, capacitor C1 is bypassed. Then, u1 is kept constant and expressed as ⎧ ⎪ u ¯20 − ⎪ ⎪ ⎪ ⎨ u1 = u ¯20 + ⎪ ⎪  ⎪ ⎪ ⎩ u ¯20 −

VI 2ω C

Mode II − Sub − I

VI 2ω C

Mode II − Sub − II

V I sin(ϕ) 2ω C

Mode III.

(7)

In Mode IV, capacitor C1 is discharged to release the ripple power. As the ripple energy is released by twice, u1 is expressed

According to Fig. 2, the average model of the proposed converter is formulated as follows: dig = ug − uc (12) Lf dt duc = ig − ii Cf (13) dt didc = iidic uc − us − Ridc Ldc (14) dt us ii · us ≥ 0 du1 u 1 idc , = C1 (15) dt 0, ii · us < 0 us ii · us < 0 du2 u 2 idc , C2 = (16) dt 0, ii · us ≥ 0

SUN et al.: ACTIVE POWER DECOUPLING METHOD FOR SINGLE-PHASE CURRENT-SOURCE RECTIFIER

Fig. 6.

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Block diagram of the overall control scheme.

where ig , idc , u1 , and u2 are controlled variables; ii and us are control input variables. B. Controller There are three control targets: 1) to keep dc-link current constant (i.e., buffering the ripple power); 2) to obtain sine input current; and 3) to maintain dc component of u1 and u2 (i.e., u ¯0 ). According to (14), both ii and us could be used for regulating dc-link current idc in theory. To improve the overall control performance, us is used to control the dc-link current and ii is in charge of implementing PFC as well as maintaining the dc component of the u1 (u2 ) at a given level. The overall control block diagram is shown in Fig. 6. Regarding to the dc-link current control, a proportional-integral (PI) controller is used. The transfer function of the current controller is expressed as follows: ki (17) s where kp is the proportional term, and ki is the integral gain. Substitute us ref in Fig. 6 to (14), the closed-loop error dynamic equation for the dc-link current is expressed as

Ldc de = k e + k e(τ )dτ (18) p i dt Gi (s) = kp +

where e = idc r e f − idc . Clearly, to guarantee the stability, the parameters of Gi (s) should satisfy kp < 0, ki < 0. In addition, the bandwidth of the dc-link current subsystem is determined by ki , and the damping ratio is dependent on kp . In both simulations and experiments, the control bandwidth is designed to be around 200 Hz and the damping ratio is selected to be 0.707 for fast dynamic responses in dc-link current control. Before introducing the voltage control of C1 and C2 , assume the dc-link current subsystem is in steady state, according to

(14), us in steady state can be expressed as us =

ii id c r e f

uc − Ridc

ref .

(19)

Substitute (19) to (15), the obtained voltage dynamic of C1  C1 dx uc ii − Ri2dc ref , ii · us ≥ 0 = (20) 0, ii · us < 0 2 dt where x = u21 . Clearly, the voltage across C1 can be controlled by control input ii . To obtain a sinusoidal grid current, the average of ii over a switching period should satisfy the following expression: ii = m · cos(θ + ϕ)

(21)

where θ is the phase of uc , which is obtained by a digital PLL. m is the control input, which will be designed later. If the subsystem (12) and (13) are stable and the effect of the input filter can be ignored, uc could be approximated to Vcos(θ). As (20) is a periodic system, the periodic averaging method [41] is used to design the controller. Then, the average differential equation of (20) is C1

d¯ x = 0.5 mV cos(ϕ) − Ri2dc dt

ref

(22)

t where x ¯ = T1 t−T x(τ )dτ , and x ¯ is obtained by a moving average filter in implementation. Equation (22) is a simple integrator; thus, Gv 1 (s) can be designed as Gv 1 (s) = kp1 +

ki1 . s

(23)

To guarantee stability, the parameters of Gv 1 (s) should satisfy kp1 > 0, ki1 > 0. Since C1 and C2 are equivalent in functionalities, Gv 2 (s)is designed to be the same with Gv 1 (s). In the decoupling capacitor voltage control loop, to make a tradeoff

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TABLE II PARAMETERS USED IN ANALYSIS, SIMULATION, AND EXPERIMENT Parameters Input phase voltage Source angular frequency Input filters DC-link filter inductor Active buffer capacitor Load Switching frequency PI parameters

Symbol

Value

V ω L f /C f Ld c C R fs kp , ki kp 1 , ki 1

1102 V 314 rad/s 0.6 mH/20 μF 5 mH 90 μF 8.7ω 20 kHz −17.5, −3.1 × 10 3 2 × 10 −4 , 4.5 × 10 −3

between the input current quality and the decoupling capacitor voltage control, the designed control bandwidth is around 10 Hz and the selected damping ratio is 2.0 in the subsequent simulations and experiments. After the references of us and ii have been determined, by combining (10) and (11), the duty ratios for all the switches can be calculated. V. VOLTAGE AND CAPACITANCE OF DECOUPLING CAPACITORS As mentioned before, the decoupling capacitor voltages have to be higher than the grid voltage for safety operation. Thus, the minimum voltage of the decoupling capacitors should be controlled to be higher than the peak of the grid voltage. On the other hand, to ensure that the IGBT’s loci of operation do not exceed safe operating area, the decoupling capacitor voltages should lower than its maximum voltage limit VM . According to (7)–(9), the dc component of the decoupling capacitor voltages can be selected as   VI VI 2 ≤u ¯0 ≤ VM2 − . (24) V + 2ωC 2ωC

Fig. 7.

Simulation results.

Fig. 8.

Photograph of the prototype.

According to (24), the capacitance of the decoupling capacitors should satisfy C≥

VI . ω (V M2 −V 2 )

(25)

Inequation (25) gives a low bound for the selection of the decoupling capacitors. According to (7)–(9), when the decoupling capacitance is small, the maximum voltages across the decoupling capacitors are relatively large, which increases the voltage stresses and dc-link current ripple significantly. On the other hand, when the decoupling capacitance is large, the voltage stresses are reduced, but the cost and volume of the decoupling capacitors increase. Therefore, the selection of the decoupling capacitance is the comprehensive considerations of efficiency, volume of the dc filter inductor, and cost. VI. SIMULATIONS AND EXPERIMENTAL RESULTS A. Simulations Results In order to verify the correctness of the theoretical analysis before, simulations under ideal conditions are carried out in MATLAB/Simulink environment and the circuit parameters are listed in Table II. The dc-link current reference is set to 7 A.

The decoupling capacitor rated at 90 μF is employed and u ¯0 is selected to 230 V with a proper safe margin. Fig. 7 shows the steady-state simulation results under unity power factor operation. As can be observed, the dc-link current idc is flat with only very small fluctuations with the proposed decoupling solution. The input current ig is sinusoidal and in phase with the input voltage ug . The waveforms of u1 and u2 are in accordance with theoretical analysis as shown in Fig. 5 exactly. B. Experimental Results An experimental prototype shown in Fig. 8 is built for experimental verification. The experimental parameters are the same as those in the simulation. The control algorithm of the converter is realized by a combination of digital signal processor TMS320F28335 and field-programmable gate array

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Fig. 9. Experimental results. (a) Experimental waveforms of input voltage u g , input current ig , and dc-link current id c . (b) Spectral analysis of input current ig . Fig. 11. Experimental waveforms of decoupling capacitor voltage u2 , input voltage u g , input current ig , and dc-link current id c in the proposed converter. (a) ϕ = π/18. (b) ϕ = −π/18.

Fig. 10.

Experimental waveforms of decoupling capacitor voltages u1 and u2 .

EP2C8T144C8N. Each decoupling capacitor is formed by connecting three 30 μF/490 V film capacitors in parallel. The experimental results in steady state and transient state are presented. Fig. 9(a) shows the steady-state experimental waveforms. Clearly, the dc-link current idc is almost constant with only a little high frequency harmonics because of the decoupling function of the capacitors C1 and C2 . Meanwhile, the low dc-link

current ripple verifies the effectiveness of the designed switching patterns. It can also be found that the source current ig is sine shaped and in phase with the source voltage ug . The total harmonic distortion value of the source current ig is 4.47% and its harmonic spectrum is given in Fig. 9(b), which meets the requirements of standard IEC/EN 61000-3-2 Class A. Fig. 10 shows the waveforms of the decoupling capacitor voltages u1 and u2 . Each of them can be divided into six subintervals which is the same as that shown in Fig. 5. In ideal cases, the decoupling capacitor voltages should be fixed when decoupling capacitors are bypassed. However, in practice they drop slightly. The main reasons for the voltage drops include the power losses due to snubber circuits and the self-consumption caused by the insulation resistance of the decoupling capacitor [42]. Therefore, as can be seen the capacitor voltages u1 and u2 are not kept constant when capacitors C1 and C2 are bypassed. Furthermore, it is also founded that u1 and u2 are the same in shapes, which is in good agreement with theoretical analysis in Section III. Note that the spikes in Fig. 10 are introduced in measurements. Because the self-inductance of the ground loop of the used oscilloprobe is too large, the measured results are affected by the

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Fig. 12. Dynamic experimental waveforms by disabling the decoupling function abruptly.

Fig. 13.

Spectral analysis of the dc-link current with/without decoupling.

electromagnetic interference caused by the switching transients in measurements. Fig. 11 shows the experimental results when the input current leads and lags the input voltage π/18. As shown in Fig. 11(a), the duration of Sub-I is longer than that of Sub-II in energy released mode when ϕ = π/18. Whereas as shown in Fig. 11(b), the contrary is the case when ϕ = −π/18. According to previous analysis results in Section III, regarding to ϕ = π/18(−π/18) the durations of Sub-I (Sub-II) and Sub-II (Sub-I) are 5π/(18ω) and 2π/(9ω), respectively. The experimental results are accordance with the theoretical analysis. In both cases, the ripple power is well buffered by the capacitors C1 and C2 and the dc-link current idc is well kept constant. Fig. 12 illustrates the experimental waveforms when the decoupling function is disabled abruptly and the modulation scheme in [43] is adopted. As can been seen, the dc-link current idc has a large fluctuation immediately, which the peak–peak value is up to 9 A and corresponds to 128.6% of the nominal dclink current because the ripple power is buffered by the dc-link inductor. Moreover, the spectral analysis of the dc-link current idc is shown in Fig. 13 for the cases with and without activating the decoupling function. It is obvious that the second-order harmonic component, i.e., 100 Hz, is significantly reduced with activating the decoupling function. To realize the same current ripple level without activating the decoupling function, the required inductance is 440 mH. So, the proposed circuit improves

Fig. 14. change.

Dynamic experimental waveforms showing 50– 100% step-up load

Fig. 15.

System efficiency curve with/without decoupling.

system power density significantly. In addition, other order harmonic components in the dc-link current with activating the decoupling function are much lower than those without activating the decoupling function. Fig. 14 shows the dynamic response of the system when the load power subjects to 50% to 100% step-up change. As can be seen, the dc-link current idc tracked the reference well and quickly with the proposed control algorithm. And the transient process is smooth and there is no obvious distortion in the input current. The fluctuation ranges of u1 and u2 increase accordingly due to the increased ripple power. Fig. 15 illustrates the efficiency curves under different load power with/without the decoupling circuit. The tests have been done under unity power factor. As can be seen, the efficiency of the proposed converter is lower than that of the traditional CSC. This is because the increased equivalent switching frequency (increased by 1/2) and voltage stresses contribute to additional switching power losses, and the conduction power losses are also increased. VII. CONCLUSION In this paper, an active power decoupling solution without requiring any additional active switches is proposed for singlephase current source rectifiers. In the proposed decoupling concept, the ripple power is buffered by two identical decoupling capacitors, which work complementarily. The developed hybrid

SUN et al.: ACTIVE POWER DECOUPLING METHOD FOR SINGLE-PHASE CURRENT-SOURCE RECTIFIER

modulation scheme is analyzed in detail. Moreover, a closedloop control strategy is proposed to enhance the decoupling effect. Finally, simulations and experimental results showed that the excellent power decoupling performance and good input current quality are achieved with the proposed solution. The ripple power is almost diverted into the decoupling capacitors and the second-order harmonic component in dc-link current is significantly reduced to 2.36% of that in the traditional CSC. However, the drawbacks of the proposed solution are the increased voltage stresses, power losses, modulation complexity, and control complexity

[17] [18] [19]

[20] [21]

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Yao Sun (M’13) was born in Hunan, China, in 1981. He received the B.S., M.S., and Ph.D. degrees from the School of Information Science and Engineering, Central South University, Changsha, China, in 2004, 2007, and 2010, respectively. He has been an Associate Professor with the School of Information Science and Engineering, Central South University. His research interests include matrix converter, microgrid and wind energy conversion system.

Yonglu Liu was born in Chongqing, China, in 1989. He received the B.S. and M.S. degrees in electrical engineering from Central South University, Changsha, China, in 2012 and 2015, respectively, where he is currently working toward the Ph.D. degree in electrical engineering. His research interests include matrix converter and ac/dc converter.

Mei Su was born in Hunan, China, in 1967. She received the B.S., M.S., and Ph.D. degrees from the School of Information Science and Engineering, Central South University, Changsha, China, in 1989, 1992 and 2005, respectively. Since 2006, she has been a Professor with the School of Information Science and Engineering, Central South University. Her research interests include matrix converter, adjustable speed drives, and wind energy conversion system.

Xin Li was born in Shaanxi Province, China, in 1994. He received the B.S. degree from the Central South University, Changsha, China, in 2015, where he is currently working toward the M.S. degree in electrical engineering. His current research interests include matrix converters and ac/dc converters.

Jian Yang (M’09) received the Ph.D. degree in electrical engineering from the University of Central Florida, Orlando, FL, USA, in 2008. He was a Senior Electrical Engineer with Delta Tau Data Systems, Inc., Los Angeles, CA, from 2007 to 2010. Since 2011, he has been with Central South University, Changsha, China, where he is currently an Associate Professor with the School of Information Science and Engineering. His main research interests include control application, motion planning, and power electronics