Advanced Memory Optimization Techniques for Low-Power ...
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Advanced Memory Optimization Techniques for Low-Power ...
Advanced Memory Optimization Techniques for. Low-Power Embedded
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Advanced Memory Optimization Techniques for Low-Power Embedded Processors
Dissertation zur Erlangung des Grades eines DOKTORS DER NATURWISSENSCHAFTEN
der Universität Dortmund am Fachbereich Informatik von
Manish Verma
Dortmund 2006
CONTENTS
List of Figures
viii
List of Tables
x
1
Introduction 1.1 Design of Consumer Oriented Embedded Devices 1.1.1 Memory Wall Problem 1.1.2 Memory Hierarchies 1.1.3 Software Optimization 1.2 Contributions of the Dissertation 1.3 Outline 1.4 Author's Contribution to the Dissertation
1 2 3 4 5 6 7 8
2
Related Work 2.1 Power and Energy Relationship 2.1.1 Power Dissipation 2.1.2 Energy Consumption 2.2 Survey on Power and Energy Optimization Techniques 2.2.1 Power vs. Energy 2.2.2 Processor Energy Optimization Techniques 2.2.3 Memory Energy Optimization Techniques
11 11 11 13 13 14 15 17
3
Memory Aware Compilation and Simulation Framework 3.1 Uni-Processor ARM 3.1.1 Energy Model 3.1.2 Compilation Framework 3.1.3 Instruction Cache Optimization 3.1.4 Simulation and Evaluation Framework 3.2 Multi-Processor ARM 3.2.1 Energy Model 3.2.2 Compilation Framework 3.3 M5 DSP
19 21 23 25 26 27 29 30 30 32
i
CONTENTS 4
Non-Overlayed Scratchpad Allocation Approaches for Main / Scratchpad Memory Hierarchy 4.1 Introduction 4.2 Motivation 4.3 Related Work 4.4 Problem Formulation and Analysis 4.4.1 Memory Objects 4.4.2 Energy Model 4.4.3 Problem Formulation 4.5 Non-Overlayed Scratchpad Allocation 4.5.1 Optimal Non-Overlayed Scratchpad Allocation 4.5.2 Fractional Scratchpad Allocation 4.6 Experimental Results 4.6.1 Uni-processor ARM 4.6.2 Multi-processor ARM 4.6.3 M5DSP 4.7 Summary
35 36 37 39 40 41 42 43 44 44 45 46 47 49 51 53
5 Non-Overlayed Scratchpad Allocation Approaches for Main / Scratchpad + Cache Memory Hierarchy 55 5.1 Introduction 56 5.2 Related Work 57 5.3 Motivating Example 61 5.3.1 Base Configuration 61 5.3.2 Non-Overlayed Scratchpad Allocation Approach 62 5.3.3 Loop Cache Approach 64 5.3.4 Cache Aware Scratchpad Allocation Approach 65 5.4 Problem Formulation and Analysis 66 5.4.1 Architecture , 66 5.4.2 Memory Objects 66 5.4.3 Cache Model (Conflict Graph) 67 5.4.4 Energy Model 69 5.4.5 Problem Formulation 71 5.5 Cache Aware Scratchpad Allocation 71 5.5.1 Optimal Cache Aware Scratchpad Allocation 72 5.5.2 Near-Optimal Cache Aware Scratchpad Allocation 75 5.6 Experimental Results 76 5.6.1 Uni-processor ARM 77 5.6.2 Comparison of Scratchpad and Loop Cache based Systems . . 87 5.6.3 Multi-processor ARM 89 5.7 Summary 91 ii
CONTENTS 6
7
Scratchpad Overlay Approaches for Main / Scratchpad Memory Hierarchy 6.1 Introduction 6.2 Motivating Example 6.3 Related Work 6.4 Problem Formulation and Analysis 6.4.1 Preliminaries 6.4.2 Memory Objects 6.4.3 Liveness Analysis 6.4.4 Energy Model 6.4.5 Problem Formulation 6.5 Scratchpad Overlay Approaches 6.5.1 Optimal Memory Assignment 6.5.2 Optimal Address Assignment 6.5.3 Near-Optimal Address Assignment 6.6 Experimental Results 6.6.1 Uni-processor ARM 6.6.2 Multi-processor ARM 6.6.3 M5DSP 6.7 Summary Data 7.1 7.2 7.3
7.4 7.5 7.6 7.7 8
Partitioning and Loop Nest Splitting Introduction Related Work Problem Formulation and Analysis 7.3.1 Partitioning Candidate Array 7.3.2 Splitting Point 7.3.3 Memory Objects 7.3.4 Energy Model 7.3.5 Problem Formulation Data Partitioning 7.4.1 Integer Linear Programming Formulation Loop Nest Splitting Experimental Results Summary
Scratchpad Sharing Strategies for Mutliprocess Applications 8.1 Introduction 8.2 Motivating Example 8.3 Related Work 8.4 Preliminaries for Problem Formulation 8.4.1 Notation 8.4.2 System Variables m