An Accurate and Scalable MOSFET Aging Model for Circuit Simulation Bogdan Tudor, Joddy Wang, Zhaoping Chen, Robin Tan, Weidong Liu and Frank Lee Synopsys, Inc., 700 E. Middlefield Road, Mountain View, CA, 94043 Email:
[email protected] trapped, which leads to a partial recovery of the degradation, depending on the trap location and trapping/detrapping time constants [2, 5]. This partial-recovery phenomenon has been particularly challenging to model. So far, reliability simulation tools mostly address it in an empirical way. [5, 6, 7]. Accurate aging models, capable to handle various processes and different gate and dielectric materials, are still needed. For the advanced technology nodes, the models must meet the following criteria: • Accurate description of the HCI and N/PBTI effects’ dependence on device bias, temperature and circuit operating time, including physical partial-recovery effect models for BTI. • Flexible scaling with device geometry. • Good integration with the circuit simulation engine to perform electrical stress computation under specified operating conditions and to carry out the stress and degradation over designated operation time period. • Ability to account for the stress accumulation effect. For example, as a MOS device is aged, the drain current decreases and that, in turn, slows down the subsequent device degradation [8]. This paper describes an accurate and scalable MOSFET aging model which meets the above criteria.
Abstract The degradation of MOSFET device performance in time (aging), caused by hot-carrier injection (HCI) and negative/positive bias-temperature instability (N/PBTI), is increasingly more responsible for IC reliability failure in advanced process technology nodes. Device scaling, that has allowed increased performance of CMOS circuits, has also resulted in a magnification of such reliability issues. At the same time, device and circuit designers face increasingly stronger requirements to provide realistic estimates of product reliability as a function of circuit operation conditions. Accurate aging modeling and fast yet trustable reliability signoff have thus become mandatory in process development and circuit design. This paper presents an accurate and scalable compact device aging model that takes into account accurately the HCI and BTI mechanisms and is silicon proven for various processes down to 32/28nm. The model formulation on bias, geometry and temperature and, in particular, a unique methodology for modeling the AC partial-recovery effect of BTI, is analyzed in detail. The model has been embedded in an efficient MOSRA circuit simulation flow and has been used successfully for numerous takeouts and silicon debugging for 45nm and below.
Keywords MOSFET, aging, NBTI, PBTI, HCI, reliability, model.
2. Aging modeling for circuit simulation
1. Introduction
The physical mechanisms associated with the BTI and HCI effects show that device aging is a result of continuous degradation of device characteristics, under the applied electrical stress. A MOSRA model is used for translating the amount of electrical stress to the actual device degradation, or “age”. There are two ways to describe this dependence, resulting in two types of models: parameterized or tablebased. A physics-based, parameterized model has the advantage of being predictive and capable to more easily address many modeling dimensions, compared with an empirical table-based solution. Furthermore, for circuit simulation purpose, the resulted degradation can be applied in two ways: 1) The amount of stress is converted in the degradation of key MOSFET compact model parameters (e.g., threshold voltage, mobility, etc.). 2) As an alternative, the stress can be directly converted into a degradation of device characteristics (e.g., direct percentage degradation of the drain current and of its conductances). While the second approach has the advantage of simplicity, the first approach allows for a separation of
MOS device aging has become a critical reliability metric to check for 45nm and below, as it results in such undesired effects as the degradation of circuit performance in time, shorter circuit lifetime and narrower reliability margins. One major physical mechanism responsible for the device aging is the well-known hot-carrier injection (HCI) into the gate dielectric from the drain end of the channel [1], where the electric field is very high even with aggressive power-supply reduction in the past. The other is the negative bias-temperature instability (NBTI) for p-channel MOSFETs [2] and the positive bias-temperature instability (PBTI) for n-channel MOSFETs [3]. PBTI is notably present in high-k metal-gate stacks. In both BTI cases, the amount of charges in the gate dielectric depends strongly on the gate bias, due to charge trapping and detrapping phenomena. When a constant bias is applied, the amount of trapped charges increases continuously, further degrading the threshold voltage VTH and decreasing channel carrier mobility. This effect is also strongly proportional with the device operating temperature [4]. In the case of a variable gate voltage, some of the trapped charges can become de978-1-61284-914-0/11/$26.00 ©2011 IEEE
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different effects that contribute to thee total device degradation, resulting in a better accuracyy of current and conductance degradation over a wide range oof device biases. Also, monitoring the degradation in the tottal drain current instead of its separate parametric compoonents, requires additional value normalizations (for exam mple, with the channel length and applied drain voltage), inn order to obtain a meaningful lifetime estimate value [9]. Ultimately, any aging model is a functtion of the total time the circuit has operated. Typically, a poower function is used to account for this dependence [1, 4] (E Eq. 1): N (1) Δ V TH ,OT ~ t
ΔVTH , AC = TTD 0 ⋅ ΔVTH , DC ⋅ exp( −TDC CD ⋅ g )
3. The BTI Model Two main physical mechanisms are connsidered for BTI modeling: one related to the contribution oof interface traps and another related to traps inside the dieleectric layer [10]. These two contributions are reflected in equuations 2 and 3, respectively, where the degradation of the thhreshold voltage has been used for illustration purpose. ⎤ ⎛ TITTD ⎞ ⎡ ε Δ VTH , IT ~ exp ⎜ − ⎟ ⋅ ⎢ (V gs − Vth ) ⎥ ⎝ K ⋅ T ⎠ ⎣td ⎦ TOTTD ⎡ ⎢ TOTFD + T Δ V TH ,OT ~ exp ⎢ − E d (V gs , V ds ) ⎢ ⎣
TITCE
⎤ ⎥ NOT ⎥ ⋅t ⎥ ⎦
[
]
⋅ exp TITFD ⋅ E d (V gs , V ds ) ⋅ t NIT
V gs − V th − TOTDD ⋅ V dsTOTDE
(5)
where the g quantity representts a measure of the duty cycle of the waveform applied on o the device during the transient simulation.
(2)
(3)
In the above equations, Ed(VGS, VDS) dennotes the strength of the electric field of the dielectrics: E d (V gs , V ds ) =
binning approach, the geometry scaaling equations embedded in the model provide for accurate global g modeling. The partial-recovery effect (Fig gures 1 and 2) is modeled by taking into account the streess stimulus duty cycle, similarly to the approach described d in [7]. While according to theory, the recovery effect depends on both the operating frequency and the duty cycle [7], it has been shown that in reality the frequency dependence can be neglected up to within the GHz range [6]. When the partial-recovery effect is considered, the total degradation becomes smaller:
Figure 1. The effect of partial reecovery on ring oscillator’ frequency degradation. The dashed line represents the degradation without partial recoverry.
(4)
td
Equations (2) and (3) are further combiined into a total degradation that is also dependent on the dielectric material’s thickness and permittivity. In paarticular for the accurate modeling of PBTI, an enhanced dependence of equation (2) on Vgs has been added. The BTI effect is usually taken into aaccount by just considering the degradation of the threshoold voltage [4]. This is also due to the difficulty of separrately extracting multiple components of BTI degradation, without causing partial recovery in the device subject to m measurement [5]. Our modeling approach allows us to takke into account, besides just the threshold voltage, thee simultaneous contribution of multiple other componennts to the BTI degradation, where virtually any key ccompact model parameter can be used. Recent publications [11, 12] and submiccron device data show a significant dependence of NBTI annd PBTI on the channel length. The dependence trend vvaries based on process conditions [12]. According to these observations we have included flexible channel width and lenngth dependence equations. While our BTI modeling sollution allows a
Tudor, An Accurate and Scalable MOSFET T Aging Model…
t BTI partial-recovery This approach to modeling the allows us to consider its effect on degradation dynamically, me. (Figure 2). as a function of circuit operating tim
Figure 2. Partial recovery of degradation d during circuit operation, as illustrated based on deevice IDsat degradation.
4. The HCI Model The most challenging part of deeveloping a HCI model is to guarantee an accurate bias dependence over a wide range of drain, gate and substrate biaases, and over different temperatures, but also for a wide array of channel lengths and for different oxide thicknessess. Our research shows that
the energy-based paradigm developed inn [9] is indeed accurate for a broad range of drain and ggate biases. The minant electron approach is based on identifying the dom energy (for NMOS) as the main reasoon behind HCI degradation, and on distinguishing three m main hot carrier degradation modes, based on the correspoonding dominant energy. With this, the established Lucky Electron Model (LEM), which considers the lateral electric fi field as the major cause of HCI [1], becomes only one of thhe proposed hotcarrier degradation modes, mostly valid forr longer channel devices in the low Vgs regime. The original lifetime model proposed in [9] includes three separate terms that depend on the drainn current, on the substrate current and on the applied drrain voltage. In practice, however, we have found it difficullt to separate all these effects for the sake of parameter eextraction. As a result, we propose a modified model that inncludes only two bias-dependent terms, by combining two of the original terms into a single one, while maintaining alll of the key bias dependencies in [9]: ⎡ ⎛ I ΔVTH , HCI ~ ⎢THCI1 ⋅ ⎜ ds ⎜W ⎢ ⎝ eff ⎣
⎞ ⎟ ⎟ ⎠
TDCE
⎛ I sub,ii ⎞ ⋅ ⎜⎜ ⎟⎟ ⎝ I ds ⎠
TDII
⎛ I + THCI 2 ⋅ VdsTDVD ⋅ ⎜ ds ⎜W ⎝ eff
⎞ ⎟ ⎟ ⎠
TDID
(6) ⎤ ⎥ ⋅ t HN ⎥ ⎦
In equation (6) the term multiplied by the THCI1 coefficient represents the combined low andd moderate drain current regime terms in [9] (correspondinng to the LEM THCI2 accounts paradigm [1]), while the term multiplied by T for the high current regime term in [9]. Furthermore, a comprehensive model for the impact ionization substrate current (Isub,ii) is criticaal to the overall accuracy of the HCI model. The MOSR RA HCI model includes two Isub,ii equation alternativees: the impact ionization induced substrate current from m the existing compact model such as BSIM4, and a deddicated MOSRA HCI impact ionization equation (Iii), which iis more accurate for the saturation region than BSIM4’s Isub (F Figure 3). With the alternative substrate current moddel, equation (6) has been proven accurate over a wide range of drain and gate biases for several technologies, down to 28nm. However, we have found that, by considerinng only the bias dependence in (6), the effect of substrate bias on degradation is not taken into account correctly. Theerefore, explicit dependence on Vbs of equation (6) haas been added. Similarly, for enhanced accuracy, the tempeerature effect has also been taken into account explicitly by using the equivalent activation energy approach [4]. Finally, a separate dependence on devicce length is also considered: TDLE (7) ⎡ ⎤ ⎛ 1 ⎞ ⎟ ΔVTH , HCI ~ ⎢TDLT + ⎜ ⎜L ⎟ ⎢ ⎝ eff ⎠ ⎣
a
⎥ ⎥ ⎦
This allows for an accurate global HCI m modeling. Like in the case of the BTI model, the possibility off a binned model approach is also provided, as an alternative.
Tudor, An Accurate and Scalable MOSFET T Aging Model…
b Figure 3. The Isub model of BSIM4 model (a) vs. the HCI impact ionization current model, Iii (b). The lines represent the simulated curves, the dots repreesent the data points.
5. Aging Models in MOSRA Flow F The BTI and HCI models have been implemented in our MOSRA flow for HSPICE and HSIM circuit simulators (Figure 4). The flow is develop ped based on one single unified engine between aging com mputation and non-aging normal simulations, hence an efficient e approach, with optimized data movement.
Figure 4. The MOSRA Flow. In Figure 4, EOL refers to the end of lifetime of a MOS device, defined as the device opeeration time at which the device parameters such Idsat degraades by a given percentage (typically, 10%) of its fresh (un-ageed) value.
The MOSRA flow includes two phases: the pre-stress simulation phase and the post-stress simulation phase, respectively (Figure 4). The two simulation phases can be executed either in the same simulator run, or independently, as needed.
5.1 Pre-stress simulation During the pre-stress (“fresh”) simulation phase, the simulator computes the electrical stress of user-selected MOSFETs in the circuit, based on the MOSRA models. The calculation depends on the electrical simulation conditions of each targeted device. The stress value from the MOSRA equation is integrated over a user-specified simulation time interval, through the duration of the transient analysis. The result is then extrapolated to calculate the total stress after a user-specified time of circuit operation (age). The total amount of electrical stress is then converted into device performance degradation, based on the MOSFET aging models. Besides the built-in aging model presented here, custom-based models can also be used, through a MOSRA Application Programming Interface (API).
5.2 Post-stress simulation During the post-stress phase, a second simulation is launched. At this point, the degradation of device characteristics is thus translated to performance degradation at the circuit level. The post-stress MOSRA simulation phase can support transient, .DC, or .AC analysis. 100
∆Idsat (%)
10 1
0.1 1E-5
1E-4
1E-3
1E-4
1E-3
1E-2
1E-1 1E+0
1E-2
1E-1 1E+0
time(yr) a
1000
∆Vth (mV)
100 10 1 1E-5
time(yr) b Figure 5. The effect of accumulated stress on IDsat (a) and on VTH (b). The dashed line represents the degradation without the effect of accumulated stress, which produces unnecessarily pessimistic circuit lifetime. Tudor, An Accurate and Scalable MOSFET Aging Model…
The effect of accumulated stress illustrates the aging simulation capabilities due to a seamless integration of the aging models within the MOSRA flow. At each MOSRA circuit operation time step the flow considers the accumulated degradation information from previous time steps. As a result, the accumulated stress effect is taken into account implicitly, with no need for empirical “equation bending” [8]. This is illustrated in Figure 5.
4. Summary An accurate and scalable MOSFET aging model for HCI and BTI is presented. This solution, embedded in an efficient and versatile MOSRA flow for SPICE and Fast SPICE circuit simulation, has been used successfully in several tapeouts and silicon debugging for 45nm and below.
5. References [1] C.Hu et al., “Hot-electron-induced MOSFET degradation - Model, monitor, and improvement”, IEEE Journal of Solid-State Circuits, vol. SC-20, no. 1, pp. 295-305 (1985). [2] V. Huard et al., “Physical Modeling of Negative Bias Temperature Instabilities for Predictive Extrapolation”, Proceedings of IRPS, pp.733-734 (2006). [3] W.-L. Lin et al., “Trapping and Detrapping Characteristics in PBTI and Dynamic PBTI between HfO2 and HfSiON Gate Dielectrics”, Proceedings of IPFA (2008). [4] M. Denais et al., “Paradigm Shift for NBTI Characterization in Ultra-Scaled CMOS Technologies”, Proceedings of IRPS, pp. 735-736 (2006). [5] R. Fernandez et al., “AC NBTI studied in the 1Hz – 2GHz range on dedicated on-chip CMOS circuits” Proceedings of IEDM (2006) [6] S.S. Tan et al, “A New Waveform-Dependent Lifetime Model for Dynamic NBTI in PMOS Transistor”, Proceedings of IRPS, pp. 35-39 (2004). [7] C. Guérin et al, “The Energy-Driven Hot-Carrier Degradation Modes of nMOSFETs”, IEEE Trans. on Device and Materials Reliability, Vol. 7, No. 2, pp. 225235 (2007). [8] T. Nigam, “Impact of Transistor Level Degradation on Product Reliability”, Proceedings of CICC, pp. 431-438 (2009). [9] X. Li et al, “Compact Modeling of MOSFET Wearout Mechanisms for Circuit-Reliability Simulation”, IEEE Trans. on Device and Materials Reliability, Vol. 8, No. 1, pp. 98-121 (2008). [10] T. Grasser et al, “The Universality of NBTI Relaxation and its Implications for Modeling and Characterization”, Proceedings of IRPS, pp. 268-280 (2007). [11] J.C. Liao et al, “Strain effect and channel length dependence of bias temperature instability on complementary metal-oxide-semiconductor field effect transistors with high-k/SiO2 gate stacks”, Applied Physics Letters, Vol. 93, Issue 9 (2008). [12] T.J.J. Ho et al, “Role of Nitrogen on the Gate Length Dependence of NBTI”, IEEE Electron Device Letters, Vol. 30, Issue 7, pp. 772-774.
