1, JANUARY 1998. An Improved MOSFET Model for Circuit Simulation. Kuntal Joardar, Kiran Kumar Gullapalli, Colin C. McAndrew, Senior Member, IEEE,.
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An Improved MOSFET Model for Circuit Simulation Kuntal Joardar, Kiran Kumar Gullapalli, Colin C. McAndrew, Senior Member, IEEE, Marie Elizabeth Burnham, and Andreas Wild
Abstract— Problems that have continued to remain in some of the recently published MOSFET compact models are demonstrated in this paper. Of particular interest are discontinuities observed in these models at the boundary between forward and reverse mode operation. A new MOSFET model is presented that overcomes the errors present in state-of-the-art models. Comparison with measured data is also presented to validate the new model.
I. INTRODUCTION
A
LTHOUGH many compact models for MOSFET’s have been published in the literature over the years, most of these models have drawbacks stemming from simplifying assumptions made during their development. These drawbacks limit the accuracy of these models in specific regions of device operation. For example, the earliest models such as the SPICE level1 and level2 models were highly empirical and contained discontinuities in their current and capacitance characteristics. They did not conserve charge and did not incorporate the physics of short-channel devices accurately. Over time most of these problems were eliminated and state-of-the-art models are not only more physically-based but are also able to replicate device characteristics quite accurately over a large geometry space [1]–[7]. However, a survey of several recently published nonproprietary and public domain MOSFET models has shown that even these advanced models continue to be plagued by subtle yet fundamental errors that have potentially deleterious effects on the accuracy of analog circuit simulations. For instance, a common problem with the BSIM3v3 model from Berkeley, the MM9 model from Philips, the PCIM model from DEC, and the EKV model developed by Enz et al., is the presence of discontinuities in the derivatives of the drain current and terminal charges at the boundary between forward and reverse mode operation. These discontinuities arise primarily from the use of the source as the reference terminal, the nature of the velocity-field expressions, and the smoothing functions used in the transition area between the linear and saturation regions in these models. Other models such as the MISNAN model from Carleton University and BNR and the Seimens model developed by Miura-Mattausch do not have these discontinuities under certain limited conditions, but display unrealistic conductance behavior at the linear/saturation transition boundary on the output – Manuscript received January 28, 1997; revised July 21, 1997. The review of this paper was arranged by Editor A. H. Marshak. K. Joardar, M. E. Burnham, and A. Wild are with Motorola, Semiconductor Products Sector, Mesa, AZ 85202 USA. K. K. Gullapalli is with Motorola, Austin, TX 78731 USA. C. C. McAndrew is with Motorola, Tempe, AZ 85284 USA. Publisher Item Identifier S 0018-9383(98)01158-7.
characteristics [6], [7]. Furthermore, some models such as the original version of SSIM from Motorola have a discontinuity at the subthreshold/linear boundary as well. This error shows up as “spikes” if the transconductance to drain current ratio in linear operation is plotted as a function of gate voltage [8]. Yet another problem that many exisiting models have is the poor simulation of transcapacitance behavior versus bias, such as nonidentical and values at . It should be noted that for many circuits the errors mentioned above do not produce gross inaccuracies in simulation results. These deficiencies mainly affect the simulation of higherorder effects in precision analog and communication circuits such as amplifier distortion. In some cases the discontinuous characteristics mentioned earlier can affect the convergence rate of transient simulations. A better MOSFET compact model is therefore required that overcomes the problems mentioned above. Such a model is described in this paper. The new model is surface potential based and is quasistatic in nature. In Section II some of the errors present in the recently published models are demonstrated using BSIM3v3 from Berkeley as an example. The theoretical aspects of the new model are then given in Section III. In Section IV the new model is compared with measured data and finally Section V provides a summary discussion. II. ERRORS
IN
EXISTING MODELS
Most of the well-known problems with earlier compact models for MOSFET’s were related to discontinuities in conductances at the boundary between linear and saturation region or at the boundary between weak and strong inversion conditions. These problems have been resolved quite successfully by utilizing a single expression for current in all regions of operation. The components of this expression are made to vary smoothly between their physical limits as a function of bias. This ensures that the current and all its derivatives with respect to the terminal biases are always continuous. A similar approach is used for modeling terminal charges. However, in all models attention has been given to maintaining continuity in the charge and current expressions exclusively in the forward or reverse regions, but not across the boundary between these two regions. The resulting errors are demonstrated in this section using the popular BSIM3v3 model from Berkeley. The Gummel Symmetry Test can be used to demonstrate the problem most compact models have around the bias point [9]. This test uses the circuit shown in Fig. 1 which basically drives a MOSFET symmetrically in both forward and reverse directions by sweeping only one source. The gate-
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Fig. 1. Schematic drawing of circuit used to demonstrate errors in MOSFET compact models. Fig. 2. Plot of the transconductance dId =dVx for a hypothetical NMOS device versus Vx as obtained from a simulation using the BSIM3v3 model. The second derivative is also shown. The discontinuity in the second derivative 0 is obvious. The dots represent measured data, which displays at Vx smooth behavior at Vx = 0.
TABLE I MODEL PARAMETERS USED TO DEMONSTRATE FLAWS IN BSIM3v3
=
substrate bias is fixed at . The source-substrate bias is and the drain-substrate bias is , where is the initial nonzero source-substrate and drain-substrate bias, and is an independent voltage source. Note that is always equal to . If is swept from a negative value to an equal positive value, the transistor is driven symmetrically from reverse mode to forward mode. It is evident from fundamental considerations of symmetry that for a laterally uniformly doped device the drain current should be an odd function of , that is, (1) and all its higher-order derivatives with respect Further, if to the terminal voltages are continuous, (1) also implies that the second derivative of in the above circuit with respect to should be equal to zero at . That is, (2) To check if (2) is satisfied it is enough to plot the derivative as a function of . If a model is truly continuous, the slope of this characteristic should be zero at . In addition to the drain current behavior, proper modeling of the terminal charges in a compact model can also be checked using the circuit shown in Fig. 1. This is accomplished by simulating the gate, source, drain, and bulk charges of the MOSFET , and , respectively, while sweeping from a negative value to a positive value. The derivatives of these charges with respect to are then plotted as a function of . Ideally, all of these plots should pass smoothly and show no discontinuities. Further, since a through symmetric device is always assumed a priori, the derivatives of and should be equal and opposite at .
Fig. 3. Plot of the transcapacitance dQG =dVx for a hypothetical NMOS device versus Vx as obtained from a simulation using the BSIM3v3 model. The discontinuity in the derivative at Vx = 0 is clear.
The circuit shown in Fig. 1 was simulated using Motorola’s in-house circuit simulator MCSPICE. The BSIM3v3 MOSFET model was used. The model parameters used for this purpose are listed in Table I and represent a somewhat idealized, hypothetical device without second-order and extrinsic effects such as junction leakage currents. Furthermore, the device of 10 m/10 m, minimizing all small simulated had a geometry effects. Any model parameter not listed in Table I assumed its default value. BSIM3v3 default parameter values are listed in [1]. with . Fig. 2 shows the simulated variation of It is evident that while the drain current and its first derivative , higher-order are symmetric and continuous about derivatives are discontinuous at this point. For reference, data from measurements on a similar sized device is also included. The measured data agree with the type of behavior that is expected from fundamental physical considerations. The reasons for the improper simulation results will become clear when the new model is described in the following section. Figs. 3–5 show the errors in BSIM3v3 associated with the computation of terminal charges. The derivatives of the gate,
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Fig. 4. Plot of the transcapacitances dQD =dVx and dQS =dVx for a hypothetical NMOS device versus Vx as obtained from a simulation using the BSIM3v3 model. The discontinuity in the derivatives at Vx 0 is clear.
=
Fig. 6. Plots of the capacitances Cgs and Cgd for a NMOS device versus drain bias Vds as obtained from simulations using BSIM3v3. Although the two capacitances are expected to be identical at Vds = 0 from physical principles, the BSIM3v3 model yields different values indicating a flaw in the model.
Fig. 7. Schematic representation of the MOSFET structure used in developing the new compact model. Fig. 5. Plot of the transcapacitance dQB =dVx for a hypothetical NMOS device versus Vx as obtained from a simulation using the BSIM3v3 model. The discontinuity in the derivative at Vx = 0 is clear.
source/drain, and bulk charge with respect to are plotted in Figs. 3, 4, and 5, respectively. All three plots show a discontinuity at . Another error with BSIM3v3 lies in the capacitance models. From simple physical considerations it is expected that for and symmetric devices the capacitances should have identical values at . Fig. 6 shows a plot of the capacitances and as a function of , as obtained from a simulation using BSIM3v3. As before, the model parameters in Table I were used. The gate voltage was set at 3 V (strong inversion) and the substrate bias was zero. Clearly, the two capacitances do not coincide at , indicating a flaw in the model. The problems with MOSFET compact models described in this section are present not only in BSIM3v3 but in several other models as well. For example many of the MOSFET models in the HSPICE simulator from Metasoftware also contain the modeling errors described above. Others such as the EKV model or the Philips MM9 model could not be tested for these defects because they were not included in any of the circuit simulators available at the time of this writing. However, as the reasons for these modeling errors are outlined
in the following section, it will become evident that these and most other public domain models also have these drawbacks. III. IMPROVED MODEL Fig. 7 shows the device structure and nomenclature used in the development of the new MOSFET model. A uniformly doped, symmetric NMOS device structure is assumed. The channel region is hypothetically divided into three sub-regions. In regions A and C carriers are assumed to flow at the saturation velocity . In region B carrier velocity is assumed to be less than . That is, this region is taken to be ohmic. It is important to note that regions A and C do not exist simultaneously. In the forward mode of operation, i.e., , is zero and region A completely vanishes, while is positive. Similarly in reverse mode operation, , is zero and region C vanishes, while takes a positive value. To avoid model discontinuities at the forward/reverse operation boundary it is very important that and from zero to positive values the variation of is accomplished smoothly. It will be shown that while this condition is adequately satisfied in this new model, it is not met in existing models and is one source of the errors described earlier. It is also worth noting that for both regions A and C vanish completely.
JOARDAR et al.: IMPROVED MOSFET MODEL FOR CIRCUIT SIMULATION
In the rest of this paper, forward mode operation will be assumed. So, for the purposes of all subsequent work region A is nonexistent, i.e., . For application in reverse mode operation an analogous approach can be taken, starting with the fact that region C does not exist.
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where optimizes to an even integer, these models will also result in drain current discontinuites at the forward/reverse operation boundary arising from the use of an improper expression. Under these considerations the - expression chosen for use in this new model is (7)
A. Static Drain Current Model Following standard practice the drain current
is written as (3)
is the effective channel width, is the average carrier where drift velocity, represents the inversion charge density, and is an effective diffusion constant. The quantities and are taken to be functions of position . The first term on the right-hand side (RHS) of (3) represents the drift current and the second term represents the diffusion component of the drain current. Defining a normalized inversion charge density as (4) where area, as
is , the gate oxide capacitance per unit denoting the gate oxide thickness, (3) is rewritten (5)
Next, a suitable expression for the variation of carrier velocity with lateral electric field is chosen. It is important to use an expression for the carrier velocity that 1) is symmetric with respect to the zero field point, 2) is continuous for all fields, and 3) has first- and higher-order derivatives that are also continuous, particularly at the zero field point. If the last condition is not satisfied discontinuities in the drain current, such as those shown in Section II, will result. The most commonly used velocity-field ( - ) expression has the form (6) where is an effective mobility, is the saturation velocity, is an empirical fitting parameter, and is the lateral field [5]–[7]. It can be seen that (6) will satisfy all three conditions above only if takes even integer values. In Berkeley’s BSIM3v3, Motorola’s SSIM, DEC’s PCIM, and in Philips’ MM9 model the value of is fixed at unity as this makes the resulting drain current expression integrable (with respect to position) in closed form. This, however, leads to a violation of condition (3) above because is not smooth around (i.e., around ). This is one of the reasons why these models have discontinuites at the forward/reverse operation boundary. In other models such as the EKV, MISNAN, and the Miura-Mattausch model is a model parameter that is optimized to get a good fit between measured and modeled data and typically lies between 1 and 2 [3], [6], [7]. The use of a nonunity value for in these models makes the resulting drain current expression unintegrable, but this problem is resolved by using an average, position independent, field in the ( - ) expression. In any event, except for the limited cases
is the surface potential and is the lateral where field. Further, is an effective mobility given as (8) being the low-field mobility and a mobility degradation factor due to the vertical (gate) field. Equation (7) satisfies the necessary conditions for a good - model and also represents measured characteristics adequately [10]. The mobility degrais typically expressed in terms of the excess dation factor gate voltage over the threshold voltage. However, since this model is surface potential based can be expressed in a more fundamental form as a function of the vertical field. in this new model is given as UBRED
(9)
where UBRED and EAVEXP are model prameters and the effective vertical electric field calculated from EAVF
is (10)
In (10) EAVF is another model parameter and represents the permittivity of silicon. The form of this model for vertical field induced mobility degradation is suggested in [11]. Next, following well-known principles of MOS physics, the normalized inversion charge density is expressed as (11) where is the surface potential with respect to the bulk, is the gate to bulk applied voltage, and is the flatband voltage [12]. represents the depletion charge density under the gate. In general, at any location is a complex function of the surface potential at that location. At (source) the exact values of the surface potential and depletion charge are denoted as and , respectively. Similarly at the drain end, , the exact values of the surface potential and depletion charge are denoted as and , respectively. In the region is expressed as the following approximate but linearized function of : (12) where is Gummel’s linearization factor and
is given as [12] (13)
Equation (12) is derived in the following manner. First, is linearized around by expanding it in a Taylor series around and retaining only the first two terms. Next, is similarly linearized around . Finally, the above
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two linearized versions of are averaged to yield (12). It is important to note that (12) expresses as a balanced or symmetric function of source and drain end potentials and charges. In surface potential based models such as SSIM where such a charge linearization is done, is usually expressed as a function of the source side quantities only. In threshold voltage based models such as BSIM3v3 the bulk depletion charge density and the threshold voltage are also expressed in a onesided manner, i.e., as functions of the source to bulk voltage only. This is yet another reason for discontinuities in current and charges at the forward/reverse operation boundary in these models. Inserting (12) in (11) yields the following simplified expression for the normalized inversion charge density that is linearized in terms of the surface potential : (14) and in (14) are the exact values of at the source and drain, respectively. Following standard practice, (7) is inserted in (5) and Einstein’s relation is invoked. The resulting expression is rearranged and both sides of the equation are integrated from to giving
(15) The RHS of (15) can be integrated simply by using the linearized form of given in (14). However, the left-hand side (LHS) cannot be integrated without further simplification because both and are complex functions of position. To integrate the LHS of (15) the following approximations are made. 1) The term on the LHS is replaced by the average lateral electric field in the ohmic region . is replaced by , the 2) The effective mobility average of its values at and at . The error due to these approximations is expected to be small as the field variation across the ohmic portion of the channel is not large. The error was estimated to be about 2–3% by integrating (15) numerically for a few typical cases. With these approximations, the LHS of (15) can be integrated to yield the expression for the drain current (see (16) at the bottom of the
page), where is a channel length reduction factor given simply by , being the total channel length. The first term on the numerator of (16) can be recognized as the drift component of the drain current and the second term as the diffusion component. To be able to calculate the drain current from (16) the quantities on its RHS still need to be evaluated. The surface potential at the source is addressed first. Following Tsividis, and [12], the following relationship is written between the gate to bulk and source to bulk voltages and , respectively, (see (17) at the bottom of the page), where is an effective value of the body-effect coefficient and its relationship to the channel doping and oxide thickness and device geometry is explained in more detail later. is the surface potential at the onset of strong inversion and is given as (18) is the channel doping and is the intrinsic carrier where concentration. For a set of given values of and it is obvious that (17) cannot be solved in closed form for the surface potential . can only be obtained accurately using an iterative numerical approach such as the Newton–Raphson algorithm. This may seem to pose a severe computational burden on this model. However, it has been shown that a good initial guess to the solution of (17) is almost always possible using which the final solution can be obtained by performimg one or two iterations [6]. Overall, it is felt that the added computation time required to solve (17) is well worth the return in accuracy in the final simulated results. Once is determined, several other source side quantities can also be obtained easily. The depletion charge and the normalized inversion charge are obtained, respectively, from the following [12]: (19) (20) and thus obtained are then substituted The values of for and respectively in (10) to yield the vertical electric field at the source. This result is then used in (8) and (9) to calculate the value of the effective mobility at the source end. For convenience this value is denoted by . To evaluate the surface potential and related quantities such as the inversion charge at the drain end of the ohmic
(16)
(17)
JOARDAR et al.: IMPROVED MOSFET MODEL FOR CIRCUIT SIMULATION
channel region , the effective drain voltage at this location must first be determined. If the terminal biases are such that the device operates in the traditional linear region then is essentially equal to the applied voltage , ignoring series resistance effects. In the saturation region is pinned at what is generally known as the saturation voltage . To a first-order of approximation is independent of the applied voltage . To evaluate it is noted that, by definition, represents the electrical boundary between linear and saturation regions and it is the value of at which the mobile carrier velocity is exactly equal to . At this point a brief qualitative discussion of the physics behind the drain saturation voltage is in order. With a fixed gate bias , as the drain voltage is increased the inversion charge density at the drain decreases. As decreases the potential across the channel adjusts to increase the carrier velocity at the drain so that the current flow is maintained. However, there is a limit to how far can decrease because the maximum carrier velocity possible is . Once is large enough that this maximum carrier velocity is reached is pinned at a minimum value. Correspondingly, the surface potential at the drain is pinned at a maximum value . The drain voltage corresponding to this condition is, of course, . As increases beyond the region marked in Fig. 7 begins to form. The excess voltage is dropped across this velocity saturated region. The length of this region increases with , resulting in a finite output resistance. is obtained by equating the carrier velocity at the drain to . The carrier velocity at the drain is given as
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for
. Furthermore, it should be noted that at , and the factor in (16) is exactly equal to one because the length of the velocity saturated region is still zero. Thus, at the onset of saturation the carrier velocity at the drain can be expressed as (see (22) at the bottom of the page) where is the minimum normalized carrier density required at the drain to sustain the current . Just as the inversion charge density at the source was written in terms of the surface potential at that location using (19) and (20), so can be related to as
(23) Inserting (23) in (22) and ignoring the exponential term within the square root gives, after some algebraic rearrangement, a of the form quartic equation for (24) whose coefficients are given by the following system of equations:
(21) where is the drain current, is the channel width, and , as stated earlier, is the normalized inversion charge density at the drain end, . is given by (16). However, the following approximations are necessary to (16) to allow a . (a) Assume that the square closed form evaluation of root term in the denominator of (16) can be taken as unity, implying a truly ohmic channel, and (b) that can be replaced by the effective mobility at the source . These approximations are not expected to cause much error because the potential drop across the ohmic region of the channel is usually not very high. The error was obtained for a few typical cases by iteratively searching for the drain bias at which the carrier velocity exactly reaches at the drain. The results showed less than 1% difference in the final result
Equation (24) can be solved in closed form using standard formulas [13]. Or it may be solved numerically since polynomial forms such as (24) converge very rapidly. Since (24) is a fourth-order equation it will have four roots and it is possible to end up with more than one real root. In that case, the root lying between and should be chosen. It should be noted that the solution for (24) yields only , not the drain saturation voltage . However, using an expression analogous to (17) it is possible to relate to the corresponding drain voltage (see (25) at the bottom of the page) where . By assuming that
(22)
(25)
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and are much larger than the thermal voltage and rearranging (25) can be expressed as
(26) can be readily obtained by adding . The From (26) assumption that is much larger than may not be satisfied in weak inversion. However, in this case can be obtained very simply by noting two points. First, for , (where the drain current is given not only by but also by [12]. Second, the ratio is given as [12]. Using these relations it is easy to see that is simply equal to from which can be obtained by adding . In the actual software implementation of the model the switch from (26) to this simplified form of is done when . At this point no discernible discontinuity in or its derivatives has been noticed. Once the saturation voltage is determined, the effective drain voltage can be formulated. It is known from the previous discussion that approaches the applied drain voltage for and approaches for . This kind of behavior can be modeled using the following smoothing function: (27) where is an empirical fitting parameter that can take integer values only. The larger the value of the more abrupt is the transition of from to . The most important characteristic of (27) is that its derivative is exactly equal to unity at (i.e., at ). Existing models such as BSIM3v3, MM9, EKV, and PCIM use other types of smoothing functions to make go from at low biases to at high drain biases. For example, the following expression is used in BSIM3v3:
(28) where is a fitting parameter that is used to adjust the curvature of the transition from linear to satruration region. It is easy to see that this function has a non unity value for the derivative at . The same problem exists with the log-exponential smoothing function used in models such as PCIM and SSIM. This deficiency is another reason for the discontinuity seen in existing models at the forward/reverse operation boundary. It should be noted that (27) was not obtained from any physical principles. Rather it
is an empirical function that satisfies the necessary smoothness criteria. In the MISNAN model, which is also surface potential based, the saturation drain voltage is computed using empirical formulations [6]. The authors of this model have noted that this approach can lead to discontinuities in the output conductance at . The surface potential based model developed by Miura-Mattausch does not compute a value for , relying as is increased instead on the natural saturation of [7]. However, this implicitly assumes that the carriers at the drain end can attain unlimited velocity, which of course is unrealistic. Furthermore, this causes nonmonotonic drain current behavior as a function of as has been recognized by some authors [3], [6]. Once is determined all other drain side quantities can be found in a manner analogous to the source side. For completeness it is noted that the drain end surface potential is obtained by solving (29) shown at the bottom of the page which is analogous to (17) and where is equal to . The drain end depletion charge is obtained from (30) and the normalized drain end inversion charge density from (31) is then calculated The effective mobility at the drain end by substituting and for and respectively in (8), (9) and (10). is given simply as . The only remaining term in (16) that still needs to be determined is the channel length reduction factor . The length of the saturated portion of the channel is obtained from a pseudo-two-dimensional analysis of this region as shown by El-Mansy [14]. Following [14], the solution of the two-dimensional Poisson equation yields the following expression for the surface potential in the velocity saturated portion: (32) where the definition has been used, and is a characteristic length which approximately represents the depth over which the mobile charge is spread in this region and represents the lateral electric field at the boundary between the ohmic and velocity saturated regions of the channel. should, strictly speaking, be calculated in a self-consistent manner from (7) but for simplicity it is expressed as . Further, since at the drain junction is , (32) can be manipulated to yield (33)
(29)
JOARDAR et al.: IMPROVED MOSFET MODEL FOR CIRCUIT SIMULATION
To ensure proper numerical behavior in all conditions (33) is transformed by replacing the inverse hyperbolic sine function with its logarithmic equivalent and using the approximation for : (34)
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reasonable compromise between complexity and accuracy particularly because parasitic effects such as those arising from the source and drain junction capacitances are often more significant than the intrinsic quantities. From fundamental considerations the gate charge is given as
which can be further reduced to
(37) (35)
. The quantity is where known to be a function of gate oxide thickness, doping densities, the drain junction depth, and applied biases. Qualitatively, the larger the gate field, the more strongly are carriers confined near the surface resulting in a reduction in . This gate bias dependence is seen to be stronger in short-channel devices because is larger for a short-channel device. Based on these arguments is expressed empirically as (36) where (roughly equal to the square of the drain junction depth) and are empirical model parameters. For small geometry devices it is important to model the Drain Induced Barrier Lowering (DIBL) effect [12]. DIBL causes the surface potential at the source to be altered due to its proximity to the drain-substrate junction. Similarly the surface potential at the drain is also affected by the state of the source-substrate junction. In electrical terms DIBL causes the threshold voltage of a MOSFET to decrease as the reverse bias on the drain is increased. This results in an increase in the drain saturation current and a reduction in output resistance as the drain bias is increased. In thresold voltage based models such as BSIM3v3 and PCIM this is accounted for by simply making the threshold voltage a function of . Typically the relation is used, where is the threshold voltage in the absence of DIBL and is a is modulated. parameter that controls the extent to which This approach is yet another reason for the discontinuities these models exhibit at the forward/reverse boundary. A more physical approach would be to alter the surface potentials at the source and drain ends with changes in and , respectively. However, this tends to cause numerical problems. In this model DIBL is included by using an effective gate voltage that is a function of the drain and source biases to compute the surface potentials at the source and drain ends, respectively. In particular the surface potential at the source is computed from (17) but is replaced with . Similarly is computed by solving (29) but is replaced by . is a parameter that is dependent on the effective channel length, as described later. B. Terminal Charge Models Expressions for the four terminal charges that are required for transient mode simulations are developed in this section. The main assumption made in this section is that channel length modulation can be neglected. This is felt to be a
It is more convenient to integrate (37) with respect to the normalized inversion charge density rather than position . To accomplish this several manipulations are necessary. First, it is noted from (14) that (38) Using this relation, (15) is rewritten as (39) where (a) the upper limit of integration is changed to correspond to any arbitrary location , (b) a position independent average value is assumed for the mobility, and (c) (38) is used to replace on the RHS of (15) with . A new variable is now introduced which is related to linearly as (40) Using this new variable, (39) is first integrated from zero to and then integrated again from zero to . The two results are ratioed to yield the following relationship between and (41) and are values of corresponding to where and respectively. Now a change of variable is performed on (37) and it is rewritten as (42) The derivative is readily obtained from (41) and substituted in (42) to give (43) To integrate (43) a relation between and is required. This can be obtained by rearranging (14) and using the definition (40). The result is used in (43) and the integration performed to yield the following expression for :
(44) The drain charge is now evaluated in a similar manner. Using Ward’s charge partitioning scheme is written as [15] (45)
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As before, the variable of integration is changed from to and is replaced with in (45) yielding
(46) , Further, using (42) is expressed as a function of and and the derivative is also evaluated. The results are then substituted in (46) to give
(47) This is integrated in closed form to yield the following : expression for
(48) The total channel inversion charge
is given as
moving at the saturation velocity. To include channel length modulation, the upper limit of integration on the RHS of (37) is first changed to . The subsequent results are then reevaluated. This is accomplished simply by replacing with as necessary in (38)–(50). This will yield the charges associated with the ohmic portion only. The charge in the velocity saturated region must now be added. Since the carriers in this region flow at a constant velocity , the total . instanteneous charge in this region is This component is added to the previoulsy calculated gate charge (44) and drain charge (48), to yield the final result. C. Scaling Models To be able to model the electrical characteristics of MOSFET’s over a wide range of geometries it is necessary to make some of the parameters described earlier dependent on the channel length and width of the device. For example, it is found that the DIBL effect cannot be modeled accurately using a single value for for all values of channel length . DIBL has been studied extensively by several authors and it is generally felt that this effect increases roughly exponentially with decreasing channel length [16]. Based on this understanding is expressed semi-empirically as
(49) This expression can be evaluated using a similar approach to that used for . The resulting expression for is
(50) The source charge
is then given simply as
DIBLL
(54)
where DIBLL and DIBLE are model parameters applicable to any device geometry. In addition to DIBL the body effect term, , and the flatband voltage , are made to depend on device geometry. Arguments similar to those given for DIBL can be made for relating these two quantities to geometry, but are not discussed here for brevity and because they are not the central theme of this work. Instead, the exact dependencies of these terms on and are simply stated below
(51) is derived from charge neutrality Finally, the bulk charge conditions. It is expressed as
(55) VFBO
(52) The transcapacitances can be easily calculated from the charge expressions derived above using the definition (53) where and could represent the drain, gate, source, or body related quantities. The negative sign is used if and the positive sign for . The differentiations required are straightforward and can be performed in closed form, but the results are extremely lengthy and have therefore not been quoted here for brevity. Since the charge expressions are all smooth the transcapacitances derived from them are also well-behaved. Since the effect of channel length modulation was neglected while developing the charge models, a first-order approach to include this effect is now outlined for completeness. In part A of this section the quantity was obtained which represents the fraction of the total channel where carriers are
VFBLL
VFBWL (56)
is a model parameter that represents the long-channel flatband voltage. VFBLL, and VFBLE are the model parameters associated with scaling. The forms of these relations are somewhat empirical but follow the known physics of the respective effects. The smoothing parameter introduced in (27) and the channel length modulation term introduced in (36) are also related to the device geometry as (57) and LCOO LCOL
(58)
where , and are model parameters. These relations are purely empirical. It should be noted that the value of obtained from (57) is rounded to the nearest integer before being used in (27). Finally, the effective channel
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TABLE II MODEL PARAMETER LIST OF NEW COMPACT MODEL
length and width, length and width (
and
, are related to the actual drawn and ) respectively as ODIF
PBIAS
(59)
and ABIAS
(60)
ODIF is a model parameter representing the out-diffusion of the source and drain diffusions into the substrate, and ABIAS and PBIAS are model parameters representing the process bias introduced during active layer and gate poly patterning, respectively. The model described in the above paragraphs pertains only to the intrinsic device. To properly model observed electrical characteristics it is essential to model the extrinsic effects as well. These effects are 1) the source-substrate and drainsubstrate junction diode leakage currents and capacitances, 2) the overlap and fringing capacitances, and 3) series resistance. In addition it is important to model the substrate current due to impact ionization, effects arising from temperature variations, and channel width modulation to be able to scale accurately with channel width [2], [17]. These effects are all included in this model using previously published approaches. Their details are not described here for the sake of conciseness. IV. MEASURED
AND
SIMULATED RESULTS
The new model described in the previous section has been coded and incorporated in MCSPICE, Motorola’s in-house
circuit simulator. Table II shows a summary listing of the model parameters associated with it. The default value of each parameter is also shown in this table. Again, for brevity the parameters associated with extrisic effects such as the current and capacitances of the source/drain junctions, the overlap and fringing capacitance effects have not been included. In the first part of this section the new model described above is subjected to a series of qualitative tests to demonstrate that the fundamental modeling flaws discussed in Section II have been overcome. In the latter part of this section the and model is validated by comparing simulated characteristics with data measured on silicon. As was done earlier with BSIM3v3, the circuit of Fig. 1 is first simulated using the new model. The same model parameters as shown in Table I are used for this purpose. As before, all other parameters assume their default values ratio is 10 m/10 m. Fig. 8 shows a plot of the and the versus being the drain current simuderivative passes through lated by the model. It can be seen that with a zero slope which is the characteristic expected from fundamental physical considerations. Figs. 9–11 show the variation of the derivatives of the terminal charges with . Unlike BSIM3v3 this new model shows no respect to . discontinuities in these characteristics at Another error shown earlier in BSIM3v3 is the nonconverand at . gence of the intrinsic capacitances These two capacitances as simulated by the new model using V, , and the parameters shown in Table II for swept from 0 to 0.1 V. The results are plotted in Fig. 12.
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Fig. 8. Plot of the transconductance dId =dVx for a NMOS device versus Vx as obtained from a simulation using the new model. Unlike BSIM3v3 there is no discontinuity in the second derivative at Vx 0.
=
Fig. 9. Plot of the transcapacitance dQG =dVx for a NMOS device versus Vx as obtained from a simulation using the new model. Unlike BSIM3v3 there is no discontinuity in the derivative at Vx = 0.
Fig. 10. Plot of the transcapacitances dQD =dVx and dQS =dVx for a NMOS device versus Vx as obtained from a simulation using the new model. Unlike BSIM3v3 there are no discontinuities in the derivative at Vx = 0.
It is clear that at is identical to as is expected from fundamental physical considerations. To perform a quantitative validation of the model, a parameter set was first extracted for one of Motorola’s 3.3
Fig. 11. Plot of the transcapacitance dQB =dVx for a NMOS device versus Vx as obtained from a simulation using the new model. Unlike BSIM3v3 there is no discontinuity in the derivative at Vx = 0.
Fig. 12. Plot of the capacitances Cgs and Cgd versus drain bias Vds as obtained from a simulation using the new MOSFET model. The two capacitances have identical values at Vds = 0 as expected from fundamental physical principles.
V CMOS technologies. The model parameters for NMOS devices are listed in Table II and the extraction procedure, briefly stated, is as follows. A series of nonlinear optimizations was used for parameter extraction. Eleven devices having ratios of 25 m/25 m, 25 m/2 m, 25 m/0.65 m, 25 m/0.60 m, 25 m/0.55 m, 25 m/0.50 m, 3 m/25 m, 1.6 m/25 m, 1 m/25 m, 1.6 m/0.50 m, and 1 m/0.50 m were selected for this purpose. The gate oxide thickness TOX was first obtained from gate capacitance (C-V) measurements on the largest sized device. An initial value for the long-channel flatband voltage VFBO was also obtained from this measurement. An initial value for the doping 1 was obtained by doing a regression on threshold voltage versus substrate bias data measured on the largest device. Furthermore a starting value for ODIF is obtained using the Moneda technique [18] and PBIAS is as determined by process engineering. Beginning with these starting values for TOX VFBO, and 1, and default values for the rest of the model parameters, UBREF UBRED EAVF, and EAVEXP were optimized to obtain the best possible fit on a set of
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(a)
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(a)
(b)
(b)
Fig. 13. A comparison of measured and simulated drain current in the linear region for (a) a long-channel NMOS device, and (b) a short-channel NMOS device. The symbols represent measured data while the lines represent data obtained from the new model.
Fig. 14. A comparison of measured and simulated drain current in the linear region for (a) a long-channel NMOS device, and (b) a short-channel NMOS device. The data is plotted on a logarithmic scale to show sub-threshold behavior clearly. The symbols represent measured data while the lines represent data obtained from the new model.
linear region – and – data measured on the largest set at 0.1 V, stepped from 0 to 1 V device with swept from 0 to 3 V. The in 0.1 V increments, and mobility degradation parameters were weighted to optimize characteristics in the high region. Using the fit in versus these parameters the output characteristics ( and ) of the large device are simulated for values of 0.9 value of zero, and swept from 0 V through 3.3 V, a to 3.3 V. The simulated data is compared with measurements , and 2 are adjusted to and, if necessary, match the output conductance variation. All of the parameters optimized up to this point are now frozen except LCOO, and 2. Starting from the previous set of model parameters the error between measured and simulated – and – data taken under the same biases as before but on the next smaller device, 25 m/2 m in this case, is minimized by optimizing the 1 , VFBLL, DIBLL, LCOO, and 2. Note parameters that only those parameters associated with scaling are adjusted 1 are kept at zero. This and the exponents such as procedure is repeated through successively smaller devices until all selected geometries are exhausted. The net result
of this procedure is a sequence of values for the scaling 1 for each geometry. This - data parameters such as set is then optimized to fit the scaling equations such as (56) to yield values for the associated model parameters such as 1 , 1 , 1 , and 1 that are applicable for all geomteries. versus and versus data for a Fig. 13 shows long-channel and a short-channel device in the linear region. Both measured and simulated data are shown. In Fig. 14 the same drain current data is shown on a logarithmic scale to demonstrate the characteristics in the subthreshold region. From both these figures it can be seen that the model tracks the shift in threshold voltage with body bias quite accurately. In Fig. 15 measured and simulated output ( – and - ) characteristics are plotted, again for a long and a short-channel device. The good match between measured and simulated data, particularly the conductance, should be noted. Lastly, in data is Fig. 16 a comparison of measured and simulated shown as a function of the gate voltage for a 2- m long device. 450 identical devices were connected in parallel to boost the measurement sensitivity. Once again a good match is obtained
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(a)
(c)
(b)
(d)
Fig. 15. A comparison of measured and simulated values of (a) drain current, and (b) output conductance of a long-channel NMOS device. The corresponding values for a short-channel NMOS device are shown in (c) and (d), respectively. The symbols represent measured data while the lines represent data obtained from the new model.
between measured and simulated data. The continuity of the simulated drain current, conductances, and capacitances, and their agreement with measured data makes this a good model for analog circuit simulation. Finally, using the extracted parameter set, a few more qualitative tests are performed on the model to demonstrate its ratio soundness. Fig. 17 shows a plot of the simulated as a function of gate voltage for several substrate biases. This is referred to as the Gummel Tree-top Test and from theoretical considerations the peak of these curves should asymptotically as the substrate bias is increased [9]. This increase to expected behavior is evident in Fig. 17. Further, in all cases the data is smooth and shows no glitches or spikes indicating a continuous transition from linear to sub-threshold operation. Fig. 18 shows a log-log plot of the simulated output conducversus drain current . Again the simulation result tance is smooth without any discontinuities. Fig. 19 shows a plot of several transcapacitances simulated as a function of drain bias for a long and a short-channel device. For the long-channel is 4.79 pF device the total gate oxide capacitance and for the short-channel device it is 33.2 fF. As expected from increases physical principles, for the long-channel device to a maximum value of 2. smoothly from
Fig. 16. A comparison of measured and simulated gate capacitances for two NMOS devices of different geometries. The symbols represent measured data while the lines represent data obtained from the new model.
. For the short-channel device, where the fringe ( fF) is an important component of capacitance should increase from a value equal to to a value slightly higher than . As shown
JOARDAR et al.: IMPROVED MOSFET MODEL FOR CIRCUIT SIMULATION
m
Fig. 17. Plot of the ratio g =Id versus gate bias Vgb as obtained from the new model. The data shows a smooth transition from sub-threshold to linear region and the peak value approaches the bipolar limit of q=kT in weak inversion.
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(a)
(b)
Fig. 18. Plot of the output conductance go versus drain current as obtained from the new model. The data shows a smooth transition from linear to saturation region.
Fig. 19. Plots of several transcapacitances as a function of drain bias Vdb for (a) a long-channel NMOS device, and (b) a short-channel NMOS device, as obtained from the new model. All of the capacitances display physically correct behavior.
ACKNOWLEDGMENT in Fig. 19(b) the values simulated from this new model indeed display these characteristics. The capacitance is negative at low and increases to zero as increases past as expected.
The authors are very grateful to D. Newmark and W. Sun of APRDL for supplying the measured data. Thanks are also due to H. Fu, J. Whitfield, and A. Zlotnicka of ACT for their support and help during the development of the model. REFERENCES
V. CONCLUSION An accurate, physically based compact MOSFET model for circuit simulation has been presented. It has been demonstrated that this new model does not have the drawbacks and flaws present in other recently published MOSFET models. In particular, discontinuities in the higher-order derivatives of the current and charges at the electrical boundary between forward and reverse mode operation have been eliminated by a proper choice of velocity-field expression and the application of a better smoothing function at the transition between linear and saturation regions. The model has been validated by comparing simulated and measured and data on a variety of MOSFET’s. The model has also been implemented in Motorola’s in-house circuit simulator MCSPICE and has been in use for several months.
[1] Y. Cheng, M.-C. Jeng, Z. Liu, J. Huang, M. Chan, K. Chen, P. K. Ko, and C. Hu, “A physical and scalable I V model in BSIM3v3 for analog/digital circuit simulation,” IEEE Trans. Electron Devices, vol. 44, pp. 277–287, 1997. Also see BSIM3v3’s internet web page at hhtp://rely.eecs.berkeley.edu:8080. [2] S. Veeraraghavan, “SSIM: A new charge-based MOSFET model,” presented at MCNC Circuit Simulation Workshop, Nov. 1990. [3] C. C. Enz, “MOS transistor modeling dedicated to low-current and lowvoltage analog circuit design and simulation,” presented at 6th Brazilian School of Microelectronics, May 1996. [4] R. M. D. A. Velghe, D. B. M. Klaasen, and F. M. Klaasen, “Unclassified report NL-UR 003/94,” Philips Electronics N.V., 1994. See also H. C. deGraff and F. M. Klaasen, Compact Transistor Modeling for Circuit Design. New York: Springer-Verlag, 1990. [5] N. D. Arora, R. Rios, C. Huang, and K. Raol, “PCIM: A physicallybased continuous short-channel IGFET model for circuit simulation,” IEEE Trans. Electron Devices, vol. 41, pp. 988–997, 1994. [6] A. R. Boothroyd, S. W. Tarasewicz, and C. Slaby, “MISNAN—A physically based continuous MOSFET model for CAD applications,” IEEE Trans. Electron Devices, vol. 10, pp. 1512–1529, 1991.
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[7] M. Miura-Mattausch, W. Feldmann, A. Rahm, M. Bollu, and D. Savignac, “Unified complete MOSFET model for analysis of digital and analog circuits,” IEEE Trans. Computer-Aided Design, vol. 15, pp. 1–7, 1996. [8] Y. P. Tsividis and K. Sumaya, “MOSFET modeling for analog circuit CAD: Problems and prospects,” IEEE J. Solid-State Circuits, vol. 29, pp. 210–216, 1994. [9] SEMATECH, Compact Modeling Workshop, Sunnyvale, CA, 1995. [10] S. M. Sze, Physics of Semiconductor Devices. New York: Wiley, 1991. [11] S. C. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” IEEE J. Solid-State Circuits, vol. 15, pp. 562–572, 1990. [12] Y. P. Tsividis, Operation and Modeling of the MOS Transistor. New York: McGraw-Hill, 1987. [13] W. H. Beyer, Standard Mathematical Tables. Boca Raton, FL: CRC, 1984. [14] Y. A. El-Mansy and A. R. Boothroyd, “A simple two-dimensional model for IGFET operation in the saturation region,” IEEE Trans. Electron Devices, vol. ED-24, pp. 1148–1157, 1977. [15] D. E. Ward and R. W. Dutton, “A charge-oriented model for MOS transistor capacitances,” IEEE J. Solid-State Circuits, vol. SSC-13, pp. 703–710, 1978. [16] Z. Liu, C. Hu, J. Huang, T. Chan, M. Jeng, P. K. Ko, and Y. C. Cheng, “Threshold voltage model for deep-submicrometer MOSFET’s,” IEEE Trans. Electron Devices, vol. 40, pp. 86–95, 1993. [17] J. J. Paulos, “Measurement and modeling of small-geometry MOS transistor capacitances,” Ph.D. dissertation, MIT, Cambridge, MA, Sept. 1984. [18] F. H. Moneda, H. N. Kotecha, and M. Shatzkes, “Measurement of MOSFET constants,” IEEE Electron Device Lett., vol. EDL-3, pp. 10–12, 1982.
Kuntal Joardar received the B.Tech. degree from the Indian Institute of Technology, Madras, India in 1984, and the M.S. and Ph.D. degrees in electrical engineering from the Arizona State University, Tempe, in 1986 and 1989, respectively. Since 1989, he has been with Motorola, Semiconductor Products Sector, in Mesa. His general research interest lies in the modeling and characterization of semiconductor devices and materials. He has been involved in developing compact models, parameter extraction, and statistical circuit design methodologies for Motorola’s advanced CMOS, BiCMOS, and bipolar technologies, as well as investigating techniques for modeling and reducing cross-talk in analog-digital mixed signal integrated circuits. Dr. Joardar is a member of Sigma Xi and served on the technical committee of the IEEE Bipolar Circuits and Technology Meeting. He is listed in Who’s Who in America, Who’s Who in Science and Engineering, and Who’s Who in the World.
Kiran Kumar Gullapalli received the B.Tech degree in electrical engineering from the Indian Institute of Technology, Chennai (formerly Madras), India, in 1989, and the M.S. and Ph.D. degrees in electrical engineering from the University of Texas at Austin, in 1991 and 1994, respectively. Since July 1994 he has been with the RF and Analog simulation group at Motorola, Inc., Austin, TX. His interests inlcude device modeling and circuit simulation. His recent work has been in the area of fast algorithms for RFIC simulation, including harmonic balance. He is currently investigating methods for the simulation of autonomous circuits.
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Colin C. McAndrew (S’82–M’84–SM’90) received the M.A.Sc. and Ph.D. degrees in systems design engineering from the University of Waterloo, Waterloo, Ont., Canada, in 1982 and 1984, and the B.E. degree in electrical engineering from Monash University, Melbourne, Vic., U.K., in 1978. Since 1995, he has been the Manager of the Statistical Modeling and Characterization Laboratory at Motorola, Tempe, AZ. From 1987 to 1995, he was a Member of Technical Staff at AT&T Bell Laboratories, Allentown, PA. From 1984 to 1987 and 1978 to 1980, he was an Engineer at the Herman Research Laboratory of the State Electricity Commission of Victoria. Dr. McAndrew was awarded the Ian Langlands Medal of the I.E Australia for 1978.
Marie Elizabeth Burnham was born in Houston, TX, in 1948. She received the B.A. degree from University of New Mexico, Albequerque, in 1974, and the M.S.E.E. from Arizona State University, Tempe, in 1982. Upon joining Motorola and its Semiconductor Research and Development Laboratory, she worked on material and device properties of TFSOI and thin dielectrics for five years. She has worked in and managed electrical device characterization and modeling for a wide range of analog, digital, mixed, sensor, and rf technologies developed in the laboratories for the past nine years. Her focus has been on MOSFET and BJT device physics, statistical characterization, compact modeling, and design support. Currently, she manages models and libraries for the Wireless Subscriber Systems Group of Motorola, Mesa, AZ.
Andreas Wild received the B.S. and M.S. degrees in electrical engineering from the University Politechnica Bucharest, Romania, and the Ph.D. degree from the Institute for Atomic Physics, Bucharest, Romania. He has worked in different capacities for Motorola in Munich, Germany, and is currently Chief Technologist for Sector Technology in Motorola’s Semiconductor Products Sector, Mesa, AZ.
