An Improved Path Sensitization Method in Test Pattern Generation for Combinational Circuits Chuan-Wang Chang and Shie-Jue Lee Department of Electrical Engineering National Sun Yat-Sen University Kaohsiung, Taiwan 80424, R.O.C. E-mail:
[email protected] Abstract W e p r e s e n t a fast sensitized p a t h decision method f o r t e s t p a t t e r n generairon of combinaiional circutts. This m e f h o d accelerates a n y p a t h senstfzzatton lesi pattern generatron ( A T P G ) algortlhm, such as Dalgorithm, P O D E N , F A N , or SOCRATES. The esscntial idea of o u r m e t h o d i s t o propngate the fault on a stem ( f a n o u t node) t o all i t s f a n o u t - b r a n c h e s a n d t o desensrltie o n e or m o r e i n p u t lines of a reconaergeni g n f e when t h e f a u l t effect can no1 propagate through i h c gate I n t h i s u w y , t h e t i m e f o r selecting p a t h s t o be sensrtzzed c a n be reduced
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Introduction
We are entering the era of ult,ra large scale int.egrat.ed circuit.s (ULSI), which are expected to have more t,han 10 million t,ransistors in a single chip by the end of the century. Due t o the dramatic increase in circuit size and t.he decreasing controllability and observabilit
