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An Optimized Implementation of Phase Locked Loops for Grid Applications Francisco D. Freijedo, Member, IEEE, Alejandro G. Yepes, Student Member, IEEE, Óscar López, Member, IEEE, Pablo Fernández-Comesaña, Student Member, IEEE, and Jesús Doval-Gandoy, Member, IEEE
Abstract—This paper presents an optimized digital implementation of phase locked loops (PLLs) for grid applications suitable for implementation in low-cost industrial devices. A robust PLL is crucial in most of power converter applications, particularly in distorted environments. That is, the phase estimation should not be affected by power quality phenomena, given by Standard EN 50160, such as harmonics, imbalance, line notching, and voltage sags. The PLL dynamics is optimized as follows. A notch filter inside the loop is implemented to enhance the steady-state filtering. The bandwidth is maximized to get a fast postfault retracking (transient response). As justified in this paper, this approach is very suitable for both single- and three-phase PLLs. A lowresource-consuming implementation of the digitally controlled oscillator is provided: A digital model based on an RC electronic oscillator implements the needed trigonometric functions. This reduces the needed digital resources without reducing the performance. The proposed PLLs have been implemented and tested in a fixed-point DSP TI TMS320LF2407. These PLLs have been tested using different distorted inputs. Experimental results show that fast and rippleless phase estimations are achieved by the proposed implementations. Index Terms—AC/DC power conversion, dc/ac power conversion, phase estimation, phase locked loops (PLLs), power electronics converters.
I. I NTRODUCTION
S
YNCHRONIZATION is one of the most important issues in the control of power electronics equipment connected to the grid [1], [2]. Most of the power converter control algorithms use the phase measurement of the grid voltage fundamental component. A quick and accurate phase estimation allows for a good generation of reference signals, so the performance of the power converter is enhanced [3]. Examples of applications where synchronization is necessary are active power filters [4], power factor control [5], grid monitoring in distributed power generation systems [6], flexible ac transmission systems [7], etc.
Manuscript received September 16, 2010; revised November 3, 2010; accepted November 6, 2010. Date of publication March 28, 2011; date of current version August 10, 2011. This work was supported in part by the Spanish Ministry of Science and Innovation and in part by the European Commission (Fonds Européen de Développement Régional) under project number DPI2009-07004. The Associate Editor coordinating the review process for this paper was Dr. Alessandro Ferrero. The authors are with the Department of Electronics Technology, Superior Technical School of Industrial Engineering, University of Vigo, 36310 Vigo, Spain (e-mail:
[email protected];
[email protected];
[email protected];
[email protected];
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIM.2011.2122550
Phase locked loops (PLLs) tracking the phase of the fundamental component of grid voltages are the most widespread synchronization algorithms for both single- and three-phase systems [2], [3], [8]–[11]. PLLs are implemented inside a higher level control; they should be designed with the goals of having a good performance and not being excessively resource consuming. This paper presents a PLL design method for an optimized digital implementation in low-cost industrial devices. This approach is suitable for both single- and three-phase systems. PLLs with a good tradeoff between the transient response and harmonic/noise cancellation are presented. Notch filters inside the loop to cancel second-harmonic components are implemented with this goal. This proposal is very useful for both single- and three-phase PLLs. Single-phase PLLs generate a high second harmonic in the phase-detector (PD) output (e.g., a multiplier) [9], [10]; the notch filter cancels it in an effective way. The problem of second-harmonic generation in threephase PLLs appears when the input voltages are unbalanced [3], [12]. A linear control approach has been carried out to optimize the bandwidth without compromising stability. The major novelty of this paper is the implementation of the digital oscillator to implement trigonometric functions: The input of the digitally controlled oscillator (DCO) is the PLL output frequency, and a digital oscillator is derived from an analog RC one. The oscillation conditions are imposed by means of the Barkhausen criteria [13]. From the point of view of digital implementation in low-cost DSPs and fieldprogrammable gate arrays (FPGAs) (fixed-point devices), this is a very good solution in terms of resource consumption and design simplicity. The performance of the proposed PLLs is proved experimentally. The PLLs have been implemented in a fixed-point DSP. For the experimental tests, different input waves have been programmed using a programmable ac source. Tests include waveforms with grid faults, imbalance, harmonics, and ac-line notching. II. PLL S FOR G RID A PPLICATIONS A PLL is a nonlinear circuit or algorithm which synchronizes its output signal vo with a reference or input signal vi in frequency and phase. In steady state, the mean value of the error signal ve should be zero, which means locked state [14]. In locked state, the input fundamental frequency ωi and phase θi equal the output frequency ωo and phase θo , respectively. The basic PLL scheme is composed of the three basic functional
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is an important advantage over other digital techniques, such as stochastic and finite-impulse response filters [19]. A. State-of-the-Art Review
Fig. 1.
Block diagram of a generic PLL.
blocks shown in Fig. 1: the PD, the loop filter (LF), and the voltage-controlled oscillator (VCO) or DCO. The VCO/DCO generates a signal of frequency ωo from its nominal frequency ωn and a “correction” voltage vc . When a proportional–integral (PI) filter is used as LF, this PLL achieves a zero steadystate error even after a phase jump or a frequency step in the reference input [14]. Focusing on grid-connected power converter applications, the main role of PLLs is to synchronize with the grid voltage fundamental component. Moreover, in detail, an accurate phase-angle estimation is crucial in the control of energy flows and power factor. The main metrological characteristics of grid voltages are available in Standard EN 50160 [15] and summarized as follows. 1) In normal operation conditions, the input voltage magnitude is very limited, e.g., Standard EN 50160 gives acceptable variations of ±10% of the nominal magnitude during 95% of a week. 2) Power frequency is very limited and should not oscillate so much around the nominal value, e.g., Standard EN 50160 limits frequency deviations in 1% of the nominal value (50 or 60 Hz) during 99.5% of a week in an interconnected system. This limit is wider in isolated systems. 3) AC mains may be distorted with voltage harmonics and imbalance. Standard EN 50160 gives acceptable limits for steady-state distortion, e.g., the total harmonic distortion (THD) should be lower than 8%. 4) Occasionally, the grid voltage magnitude can be suddenly reduced below 90% (of nominal magnitude) and recovered after a short period of time. These grid faults are known as sags or dips [15]. Usually, voltage sags are associated with a significant phase jump [16]. PLLs are specially suitable to track grid voltages because of the following facts. 1) PLL algorithms are suitable for both single- and threephase applications. Usually, in three-phase applications, synchronization is made with the fundamental positivesequence component. These PLLs, based on Park’s transformations, are usually known as dq-PLLs [17]. 2) Although PLL dynamics depends on the voltage magnitude, industrial equipment limits normal ranges of operation, e.g., the Spanish Grid Code allows to disconnect a wind farm park from ac mains if the voltage magnitude remains below 80% of the nominal value during more than 1 s [18]. 3) PLLs are able to provide a zero steady-state phase error, defined as θe = θi − θo , in the presence of grid frequency deviations [3], [14]. Good frequency adaptation of PLLs
The state of the art in grid synchronization is wide and increasing nowadays mainly due to the suitability of digital implementation [19]. Focusing on PLLs, quite a lot of schemes have been proposed to optimize their dynamic response. 1) Single-Phase PLLs: The suitability of digital implementation allows to implement PDs better than the first analog charge pumps [20]. From PLL theory [14], the “linear multiplier” PD seems to be the most simple option but generates a high-magnitude second harmonic which should be canceled [1], [9]. Other more complex PDs have been also proposed to avoid this problem [21]–[23]. Another alternative is to adapt a dq-PLL by delaying the input wave 90◦ [2], [24], [25]. Singlephase PLLs have a modest transient response due to the second harmonic generation or the 90◦ delaying filters. Their typical settling times are not lower than one cycle of ωn , which can be checked in the referred works. 2) dq-PLLs: The dq-PLL algorithm is suitable to track the fundamental positive-sequence voltage, instead of individual phase voltages [3], [8], [17]. This is achieved by means of Park’s transformation Tdq vd cos(θo ) sin(θo ) vα = (1) · vq vβ − sin(θo ) cos(θo ) where
vα vβ
2 = 3
1 0
−0.5 √ 3 2
−0.5 √ − 23
va · vb . vc
(2)
The field of application of dq-PLLs is very wide, and hence, its optimization has been approached in several works [1], [3], [11], [26]–[28]. A very interesting feature of the dq-PLL is the absence of second harmonic when there is no fundamental negative sequence (imbalance). Hence, on the contrary to single-phase PLLs, a dq-PLL can be tuned with a very high bandwidth, which implies almost instantaneous retracking (after a transient) [3], [8]. However, in the case of distorted conditions, such as imbalance (second harmonic in vd ) and harmonics, the bandwidth should be reduced drastically [3], [11]. Single-Phase PLLs Against dq-PLLs: Single-phase PLLs synchronize per phase, but dq-PLLs track a positive-sequence vector. Therefore, dq-PLLs are more suitable for applications based on symmetrical components (e.g., power converters implementing dq current controllers [29]), and single-phase PLLs are better for single-phase applications or three-phase applications with a per-phase controller. The key is the ability to provide a zero steady-state phase error in the reference frame of the power converter controller [19]. B. LF Design Although PLLs are nonlinear, their dynamics can be accurately studied by linear models, obtained assuming a
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Fig. 2. PLL linearized model.
quasi-locked state: ωi = ωo and θi ≈ θo . Fig. 2 shows the linear PLL, where H(s) [H(z) for discrete models] means the open loop transfer function, which is useful to set the dynamics [1], [3], [8], [14]. H(z) frequency response diagrams give information about harmonic attenuation, transient response, and stability margins. Assuming that the DCO/VCO behaves as a simple integrator [3], [14], the dynamics mainly depends on the LF. In general, there is a tradeoff between the filtering and transient response: High-bandwidth PLLs are faster, but their outputs are more affected by noise and harmonics. A simple but effective technique includes discrete filtering to enhance harmonic filtering [1]. In this case, the LF H(z) is formed by a term dependent on the input amplitude and PD, a PI controller (lead/lag controllers lose frequency adaptation [3], [19]), a DCO/VCO integrator, and a harmonic filter H(z) =
· C(z) · N (z) K|vif |
amplitude gain PI filter harmonic filter ·
Ts . (3) z−1
DCO integrator
It should be noted that H(z) also depends on the input fundamental magnitude vif , which is an uncontrolled parameter. For this reason, the PLL bandwidth decreases in the presence of voltage sags [1], [9]. Furthermore, the value of K (constant) in (3) depends on the PD, e.g., K = 1/2 in the single-phase PLL with a multiplier PD and K = 1 in the dq-PLL [1]. It is recommended to adapt the acquired input signals to per unit, so vif = 1 p.u. at nominal voltage. This makes easier the LF design [1], [9]. III. D IGITAL I MPLEMENTATION Digital control is a clear trend in power electronics. Vendors have developed specific low-cost DSPs for motor control and other power converter applications, such as the C2000 family of Texas Instruments [30]. Most of these devices, which are equipped with specific blocks such as pulsewidth modulation (PWM) units and A/D converters, have a limited set of instructions and implement fixed-point arithmetic. Hence, implementation techniques which combine structural simplicity, low resource consumption, and good performance are of paramount interest [31]. Focusing on digital PLLs, this paper proposes easy modifications to optimize the digital implementation in low-cost
Fig. 3. Key figures of the implemented DCO. (a) DCO block diagram. (b) Pole/zero map of the DCO (in radians per second) continuous model.
devices, such as fixed-point DSPs and FPGAs. Optimum word length is analyzed by simulation in order to achieve a good tradeoff between transient response and quantification errors, i.e., between speed range and accuracy [32]. It is also shown that good filtering can be achieved with low-order digital filtering (notch filters) and without making complex the PLL structure. A high-performance DCO implementation is provided to compute trigonometric functions in a simple but effective manner. A. DCO Implementation by Means of an Oscillator Model PLLs implement trigonometric functions to generate feedback waves cos(θo ) or sin(θo ). The dq-PLLs require both sin(θo ) and cos(θo ) to generate Park’s matrices. An efficient algorithm is proposed in the following to achieve sin(θo ) and cos(θo ). It is based on a digital implementation of an RC electronic oscillator. Fig. 3(a) shows the model of the proposed digital oscillator. Fig. 3(b) shows the DCO closedloop poles for ωo = ωn = 2π50 rad/s. Following Barkhausen criteria, this system oscillates at ωo and tends to instability since its poles are on the imaginary axis. However, as the integrators are saturated, the signal amplitude can be controlled. A nonzero initial value at the output of one of the integrators (e.g., sin(θo ) = 0 and cos(θo ) = 0.99) is necessary to start the oscillation [13]. The DCO output phase θo is calculated by
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TABLE I O PTIMUM a VALUES AND THD AS F UNCTION OF fs /fo
means of ωo integration. When sin(θo ) crosses zero in the rising edge, θo is reset to zero. The following piece of code stresses the simplicity of the proposed implementation. % wo is the DCO frequency Mysin(n + 1) = Mysin(n) + wo ∗ T s ∗ (Mycos(n)); %(Q15) Mycos(n + 1) = Mycos(n) − wo ∗ T s ∗ (Mysin(n)); %(Q15) % Limit the oscillator integrators Mysin(n + 1) = max([Mysin(n + 1) − 0.99]); Mysin(n + 1) = min([Mysin(n + 1)0.99]); Mycos(n + 1) = max([Mycos(n + 1) − 0.99]); Mycos(n + 1) = min([Mycos(n + 1)0.99]); % Update the output phase (Q12) theta(n + 1) = theta(n) + wo ∗ T s; % Output phase reset condition if Mysin(n) >= 0 && Mysin(n + 1)
