Jun 8, 1998 - Thanks to the EE computer system administrators: Melissa Thrush and Diane Calleson. ...... the standard 74X-series gate-level designs [67], a property that has ...... tors produce a SSL gate level fault coverage of 290/310 = 93.55%. ...... HWH. HS. M â. E 1-1 r-l. H 0*0. w o. H-rt JJ. O (d tf 0) tn. ^.i ffl. - M. -H. H.
Behavioral Fault Modeling in a VHDL Synthesis Environment
A Dissertation Presented to the Faculty of the School of Engineering and Applied Science University of Virginia
In Partial Fulfillment of the Requirements for the Degree Doctor of Philosophy (Electrical Engineering)
by Ronald J. Hayne DISTRIBUTION STATEMENT A Approved for Public Release Distribution Unlimited
DTIC QUALITY INSPECTED"4*
May 1999
19990701 057
Approved for public release; distribution is unlimited.
© Copyright by Ronald J. Hayne All rights reserved May 1999
APPROVAL SHEET This dissertation is submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy (Electrical Engineering)
m^~
Ronald J. Hayne
This dissertation has been read and approved by the Examining Committee:
Barry W. Johnsesr Disserc^on Advisor VcJ-^o kW:
JoanneSBechta Dugan, Committee Uiair
Jojwr'C. Knight, Minor Representative
Stephen G. Wilson
ifcea R. Stan Accepted for the School of Engineering and Applied Science:
Dean, School of Engineering and Applied Science May 1999
Abstract Integrated circuit designs continue to increase in both size and complexity, making fault simulation and testing more difficult and costly. Computer aided design tools and hardware description languages are now commonly used to represent designs at higher levels of abstraction. However, fault simulation and testing of digital circuits have been historically done using fault models at the gate level or below. A design methodology is needed for performing fault simulation throughout the design process, incorporating fault models at higher levels of abstraction. Use of these higher level fault models has the promise of reducing complexity, providing earlier identification of potential problems, and improving integration of fault simulation into the overall design process. Previous behavioral fault models lack a well defined link to the hardware which they attempt to describe. Though some relationships to possible hardware faults are proposed, there is no detailed analysis to justify these assertions. Approaches based on perturbing language constructs, such as ADD to SUB, do not accurately reflect underlying hardware faults. In order to compensate for this "big micro-operation problem," alternate methods such as heuristics are used to supplement test vector sets to increase the equivalent gate level fault coverage. This dissertation proposes a new set of fault models for VHDL behavioral descriptions of combinational logic circuits. These fault models exploit hardware relationships that exist in a design environment which involves synthesis of behavioral descriptions into gate level circuits. A functional analysis technique is used to evaluate the effects of industry standard single-stuck-line (SSL) faults on gate level implementations. The generalized functional faults are then abstracted into the behavioral domain by examining their relationship with the higher level language construct. Test vectors derived from the new behavioral fault models are applied to synthesized gate level realizations of a range of circuits that include typical arithmetic and logic functions. Resulting gate level fault coverage is determined via fault simulation and used as a measure of effectiveness for the new fault models. Because the behavioral faults are derived from a functional analysis of low level faults, they provide improved fault coverage over previous fault models, over a broad range of implementations.
Acknowledgments I would like to thank the United States Army for sponsoring my continuing education. My advisor, Dr. Barry W. Johnson, deserves a special thanks for his encouragement and support. His technical leadership helped shape many of the ideas embodied in this dissertation. Along with Dr. Johnson, I would also like to thank the other members of my advisory committee, Dr. Joanne Bechta Dugan, Dr. John C. Knight, Dr. Stephen G. Wilson, and Dr. Mircea R. Stan. Their guidance and feedback was invaluable throughout my research. My gratitude is extended to Dr. D. Todd Smith and Todd A. DeLong for serving as a sounding board and sanity check for many of my ideas. Thanks also to the United States Air Force Rome Laboratory, specifically Dr. Warren H. Debany Jr. and James R Hanna, for additional comments and perspectives. The interactions of Dr. Robert H. Klenke, Dr. Lori M. Kaufman, Dr. James H. Aylor, and Dr. Ronald D. Williams are also greatly appreciated. I owe a debt of gratitude to the many individuals who have helped me throughout my program. A special thanks is extended to the following individuals: Maximo Salinas, Carl Elks, Dave Garrett, Michael Reynolds, Ryan Baucom, Wes Dungan, and Erik Laurila. Thanks to the EE computer system administrators: Melissa Thrush and Diane Calleson. Thanks also to the secretaries: Lisa Sites, Peggy McCauley, Susan Malone, and Robbie Burton. My family has provided endless love and support. The biggest thanks to my wife, Marva, for always being there for me. Her encouragement and endless optimism helped me deal with the ups and downs of the past few years. Thanks also to my sons, James and Kyle, for trying to understand all the hours spent in the conquest of this goal. My brother, Tomas, has also been a big source of encouragement. Our weekly outings to the gym helped relieve the stress inherent in such an endeavor. Finally, thanks to my parents, Jim and Audrey, for everything. They brought me up to believe that I could achieve anything I put my mind to.
Biography Ronald J. Hayne is a Lieutenant Colonel in the U.S. Army with over 18 years of service in a variety of command and staff positions. He received his B.S. in 1980 from the United Stated Military Academy at West Point and was stationed with the 25th Infantry Division in Hawaii. He received his M.S. in Electrical Engineering in 1987 from the University of Arizona, followed by a teaching assignment with the Department of Electrical Engineering and Computer Science at West Point. LTC Hayne is now a member of the Army Acquisition Corps, responsible for the research and development of new military systems, and has served with the Space and Strategic Defense Command and the Army Research Laboratory. His world travels in the military have taken him to the Republic of Korea, the Republic of the Philippines, Vienna Austria, and Kwajalein Atoll in the Republic of the Marshall Islands.
Publications Hayne, R.J. and B.W. Johnson, "Behavioral Fault Modeling in a VHDL Synthesis Environment," Proceedings VLSI Test Symposium, April 1999. Kaufman, L.M., R. Gretlein, and R.J. Hayne, "A Quantitative Assessment of the Application of Software Reliability to Reusable Code," Proceedings Reliability and Maintainability Symposium, January 1999. Hayne, R.J., P A. Brown, S.G. Hair and J.E. Oristian, "An Innovative Educational Application of the VHSIC Hardware Description Language," Proceedings Frontiers in Education Conference, July 1990.
Table of Contents Table of Contents
i
List of Figures
vii
List of Tables
xii
List of Acronyms and Abbreviations
xvi
Chapter 1: Introduction 1.1 Previous Research 1.2 Behavioral Modeling 1.2.1 VHDL Subset 1.2.2 Hardware Implementation of VHDL Constructs 1.3 Functional Analysis 1.4 Fault Injection Using WAVES 1.5 Comprehensive Examples 1.6 Contributions and Future Work
1 2 4 4 6 7 8 8 9
Chapter 2: Previous Research 2.1 Fault Models 2.1.1 Functional Faults 2.1.2 Physically-Induced Faults 2.1.3 Behavior Faults 2.1.4 Model Perturbation 2.1.5 Other Research 2.1.6 Summary 2.2 Fault Injection Techniques 2.2.1 Instruction Set Architecture 2.2.2 MEFISTO 2.2.3 Hybrid Fault Emulation 2.2.4 Summary 2.3 Test Generation Techniques 2.3.1 S-Algorithm 2.3.2 B-Algorithm 2.3.3 Other Research 2.4 Conclusions
10 10 11 13 15 16 18 22 22 22 23 23 24 24 25 25 26 28
Chapter 3: A New Control Fault Model 3.1 IF-THEN-ELSE 3.1.1 Synthesis of a Simple Example 3.1.2 Functional Analysis 3.1.3 Alternate Implementation 3.1.4 Generalized Functional Fault Model
30 30 30 31 33 35
3.1.5 3.1.6 3.1.7 3.1.8
3.2
3.3
Development of a Behavioral Fault Model Evaluation of the New Behavioral Fault Model Comparison with Previous Behavioral Fault Models Expansion of the Fault Model 3.1.8.1 Functional Analysis 3.1.8.2 Generalized Functional Fault Model 3.1.8.3 Behavioral Fault Model 3.1.8.4 Evaluation of the Behavioral Fault Model Summary
3.1.9 CASE 3.2.1 Application of the Control Fault Model 3.2.2 Evaluation of the Fault Model 3.2.3 Comparison with Previous Behavioral Fault Models Conclusions
35 37 38 40 41 44 45 46 47 48 49 51 53 55
Chapter 4: Relational Operators 4.1 Greater Than (GT) 4.1.1 Generalized Functional Faults 4.1.2 Classification of Functional Faults 4.1.3 Behavioral Fault Model 4.1.4 Adapting the Model for GE, LT, and LE 4.1.5 Summary 4.2 Threshold Detection 4.2.1 Greater Than Signed Threshold 4.2.2 A Quick Example 4.3 Equal (EQ) '. 4.3.1 Functional Faults 4.3.2 Behavioral Fault Model 4.4 Comparison with Previous Fault Models 4.5 Application of the New Fault Models 4.5.1 Faults on Relational Operators 4.5.2 Control Faults 4.5.3 Final Behavioral Test Vector Set 4.6 Evaluation of Behavioral Test Vectors 4.6.1 Gate Level Realizations 4.6.2 Expansion of the Data Path 4.6.3 Expansion of the Control Signals 4.7 Conclusions
56 56 57 58 60 62 63 63 63 64 66 66 67 68 69 69 71 73 74 75 77 79 80
Chapter 5: Arithmetic Operators 5.1 Addition 5.1.1 Ripple Carry Adder 5.1.1.1 Functional Testing 5.1.1.2 Scalability 5.1.1.3 Behavioral Fault Model
82 82 83 84 86 86
Ill
5.1.1.4 Evaluation of the Behavioral Test Vectors 5.1.1.5 Carry-in and Carry-out 5.1.2 Carry Look-Ahead Adder 5.1.2.1 Functional Testing 5.1.2.2 Application of the Behavioral Test Vectors 5.1.2.3 Scalability 5.1.2.4 Optimization of CLA Behavioral Faults 5.1.3 Summary Subtraction 5.2.1 Direct Subtraction 5.2.1.1 Functional Testing 5.2.1.2 Application of the Behavioral Test Vectors 5.2.2 Subtraction Using Addition Circuitry 5.2.3 Summary Constants as Operands 5.3.1 Functional Testing 5.3.2 Generalized Behavioral Fault Model Comparison with Previous Fault Models Conclusions
88 89 91 92 95 95 99 100 101 101 101 102 103 104 104 105 105 106 107
Chapter 6: Other Operators 6.1 Logical Operators 6.1.1 AND/OR 6.1.1.1 Functional Faults 6.1.1.2 Complex Expressions..... 6.1.1.3 Scalability 6.1.1.4 Behavioral Fault Model 6.1.1.5 Application of the New Fault Models 6.1.2 XOR 6.1.2.1 Functional Faults 6.1.2.2 Optimized Test Generation 6.1.2.3 Evaluation of the Generalized Test Vectors 6.1.3 Comparison with Previous Fault Models 6.2 Unary Operators 6.2.1 Absolute Value 6.2.2 Negation 6.2.3 Generalized Functional Faults 6.2.4 Behavioral Fault Model 6.2.5 Evaluation of Behavioral Test Vectors 6.3 Conclusions
109 109 110 110 Ill 113 113 114 118 118 119 122 123 124 124 124 125 126 126 128
Chapter 7: Other Programming Constructs 7.1 Loops 7.1.1 A Simple Example 7.1.2 Comparison with Previous Fault Models
129 129 129 134
5.2
5.3
5.4 5.5
IV
7.2
7.3
Functions and Procedures 7.2.1 Example ADD4fn 7.2.2 Example ADD4pr Conclusions
134 135 136 137
Chapter 8: Comprehensive Examples 8.1 Arithmetic Logic Unit 8.1.1 Example ALU4wc 8.1.1.1 Faults on Logical Operators 8.1.1.2 Faults on Arithmetic Operators 8.1.1.3 Control Faults 8.1.1.4 Final Behavioral Test Vector Set 8.1.2 Evaluation of the Behavioral Test Vectors 8.1.3 Expansion of the Data Path 8.1.4 Summary 8.2 Error Correcting Circuit 8.2.1 Example HAMMING4 8.2.1.1 Faults on XOR-only Expressions 8.2.1.2 Faults on Other Logical Expressions 8.2.1.3 Final Behavioral Test Vector Set 8.2.2 Evaluation of the Behavioral Test Vectors 8.2.3 Expansion of the Data Path 8.2.4 Summary 8.3 Conclusions
138 138 138 141 142 144 149 152 154 155 156 156 156 159 162 163 163 166 166
Chapter 9: Conclusions and Future Work 9.1 Research Contributions 9.1.1. Generalized Functional Faults 9.1.2 New Behavioral Fault Models 9.1.3 Gate Level Fault Coverage of Behavioral Test Vectors 9.1.4 Behavioral Test Generation 9.1.5 Behavioral Fault Simulation 9.2 Future Work 9.2.1 Expansion of Behavioral Fault Models 9.2.2 Tool Development 9.2.3 Higher Levels of Abstraction 9.3 Concluding Remarks
167 167 167 168 168 169 169 170 170 171 171 172
References Appendix A: Additional Examples A.l Array Indexing A.2 Generalization of the Control Fault Model A.3 Signed Comparison A.4 Unsigned Threshold
173 180 180 183 .......185 188
A.5
Adder/Subtractor A.5.1 Faults on Arithmetic Operators A.5.2 Control Faults A.5.3 Evaluation of the Behavioral Test Vectors A.5.4 CLA Implementation A.6 Arithmetic with Constants A.6.1 Example PLUS25 A.6.2 Example MINUS25 A.7 XOR4 A.7.1 Parse Tree Test Vectors A.7.2 Evaluation of Behavioral Test Vectors A.7.3 Optimized Test Vectors A.7.4 Evaluation of Optimized Test Vectors
189 190 190 191 191 193 194 195 195 196 197 198 199
Appendix B: Fault Experiment Results
200
Appendix C: VHDL Behavioral Descriptions C.l Variables and Signals C.2 Expressions C.3 If Statement C.4 Case Statement C.5 Loop Statements C.6 Process Statement C.7 Procedures and Functions
205 205 206 206 207 208 209 210
Appendix D: VHDL Synthesis D.l Level-0 D.2 Mentor Graphics D.3 Synopsys D.4 D3EE Draft Standard
211 211 213 214 216
Appendix E: Hardware Implementation of VHDL Constructs E.l Structured Logic Design E.2 Mentor Graphics
218 218 224
Appendix F: VHDL Source Code F.1 CASE1 F.2 ARRAY4 F.3 SHIFT4U F.4 LESS2 F.5 EQUAL3 F.6 GREATER3 F.7 LE5 : F.8 GE23u F.9 LT12u F.10 GT3n
228 229 230 231 232 233 234 236 237 238 239
VI
F.ll F.12 F.13 F.14 F.15 F.16 F.17 F.18 F.19 F.20 F.21 F.22 F.23 F.24 F.25 F.26 F.27 F.28 F.29 F.30 F.31 F.32 F.33 F.34 F.35 F.36 F.37 F.38 F.39 F.40 F.41
COMPARE COMPARE3 COMPARE4 COMPARE34 ADD4 ADD4wc ADD8 SUB4 ADDSUB4 INC4 INC8 DEC4 ADDINC4 PLUS3 MINUS5 PLUS25 MINUS25 SOP1 SOP4 POS1 GT XOR4 XOR5 ABS4 ABS8 NEG4 NEG8 ALU4wc ALU8wc HAMMING4 HAMMING8
240 242 244 245 246 248 250 252 254 256 257 258 259 260 261 262 263 264 265 266 267 268 270 272 273 274 275 276 278 280 282
List of Figures Chapter 1 Figure 1-1
Design guidelines
5
Chapter 2 Figure 2-1
Three-input majority circuit M
14
Behavioral description for example IF1 Synthesized hardware for example IF1 SOP gate level circuit for MUX21 Karnaugh map for MUX POS gate level MUX Control fault model for if-then-else Behavioral description for example IF2 Synthesized hardware for example IF2 Gate level circuit for example IF2 Control fault model for expanded if-then-else Equivalent if-then-else and case statements Logical adjacencies among clauses WHEN-CORRUPT (AND) faults for example CASE1 Synthesized Structurel for example CASE1 WAVES test vectors for example CASE 1 Synthesized Structure2 for example CASE1 Fault coverage for Structure2 of example CASE1
30 31 31 33 34 37 40 41 41 45 49 50 50 52 52 53 53
Karnaugh map for 2-bit GT function Fault classes for 2-bit GT function Fault classes for 3-bit GT function Fault classes for 2-bit GE function Functional test vectors for signed GT threshold Behavioral description for example LE5 Behavioral test vectors for example LE5 Synthesized circuit for example LE5 Fault classes for 3-bit EQ function Behavioral description for example COMPARE Synthesized Structurel for example COMPARE Alternate set of behavioral test vectors for example COMPARE Synthesized Structure2 for example COMPARE
57 59 60 62 64 65 65 65 66 69 75 76 76
Chapter 3 Figure 3-1 Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Figure 3-6 Figure 3-7 Figure 3-8 Figure 3-9 Figure 3-10 Figure 3-11 Figure 3-12 Figure 3-13 Figure 3-14 Figure 3-15 Figure 3-16 Figure 3-17 Chapter 4 Figure 4-1 Figure 4-2 Figure 4-3 Figure 4-4 Figure 4-5 Figure 4-6 Figure 4-7 Figure 4-8 Figure 4-9 Figure 4-10 Figure 4-11 Figure 4-12 Figure 4-13
Vll
VIII
Figure 4-14 Figure 4-15 Figure 4-16 Figure 4-17 Figure 4-18
Fault coverage for Structure2 of example COMPARE Behavioral test vectors for example COMPARE4 Synthesized Structure for example COMPARE4 Behavioral test vectors for example COMPARE3 Synthesized Structure for example COMPARE3
77 78 78 79 80
Chapter 5 Figure 5-1 Figure 5-2 Figure 5-3 Figure 5-4 Figure 5-5 Figure 5-6 Figure 5-7 Figure 5-8 Figure 5-9 Figure 5-10 Figure 5-11 Figure 5-12 Figure 5-13 Figure 5-14 Figure 5-15
Ripple carry adder Behavioral fault model for ripple carry adder Behavioral description for example ADD4 Synthesized Circuit for example ADD4 NOR-only realization of example ADD4 Behavioral description for example ADD4wc Carry look-ahead adder CLA implementation of example ADD4 Ripple carry implementation of example ADD8 Fault coverage for ripple carry ADD8 Block diagram of modular CLA adder Fault coverage for modular CLA adder Behavioral description for example SUB4 Synthesized circuit for example SUB4 Subtractor implemented with full adders
83 87 88 88 89 90 92 95 96 96 98 99 102 103 103
Behavioral description for example SOP1 Binary tree representing example SOP1 WAVES test vectors for example SOP4 Behavioral fault model for example SOP1 Behavioral description for example GT Parse tree for example GT Synthesized Structurel for example GT Synthesized Structure2 for example GT Fault coverage for Structure2 of example GT Labeling scheme for Bossen test Structure Cascadel for example XOR5 Structure Cascade2 for example XOR5 Modified Bossen test for Cascade2 Generalized Bossen test vectors for example XOR5 Structure4 for example XOR5 Fault coverage for Structure4 of example XOR5 Behavioral fault model for ABS WAVES test vectors for example ABS8 Synthesized Structurel of example ABS8 Fault coverage for Structurel of example ABS8
Ill Ill 113 114 114 115 117 117 118 119 120 120 121 122 122 123 126 126 127 127
Chapter 6 Figure 6-1 Figure 6-2 Figure 6-3 Figure 6-4 Figure 6-5 Figure 6-6 Figure 6-7 Figure 6-8 Figure 6-9 Figure 6-10 Figure 6-11 Figure 6-12 Figure 6-13 Figure 6-14 Figure 6-15 Figure 6-16 Figure 6-17 Figure 6-18 Figure 6-19 Figure 6-20
IX
Figure 6-21
Synthesized circuit for example NEG8.....
128
Behavioral description for example SHIFT4u Expanded case statement for example SHIFT4u WAVES test vectors for example SfflFT4u Synthesized Structurel for example SHTFT4u Fault coverage for Structurel of example SHib'l4u Behavioral description for example ADD4fn Functions for example ADD4fn Expanded behavioral description for example ADD4fn Behavioral description for example ADD4pr Procedure FA for example ADD4pr
129 130 133 133 134 135 135 136 136 137
Entity description for example ALU4wc Architecture description for example ALU4wc Logical adjacencies among clauses WAVES test vectors for example ALU4wc Synthesized Structurel for example ALU4wc Fault coverage for Structurel of example ALU4wc WAVES test vectors for example ALU8wc Entity description for example HAMMING4 Architecture description for example HAMMING4 Structure Cascadel for 4-input XOR-only expression Structure Cascade2 for 4-input XOR-only expression Parse tree for expression D(l) WAVES test vectors for example HAMMING4 Synthesized Structurel for example HAMMING4 Entity description for example HAMMING8 Architecture description for example HAMMING8 WAVES test vectors for example HAMMING8
138 139 147 151 153 153 154 156 157 157 157 159 162 163 164 164 165
Behavioral description for example ARRAY4 Equivalent case statement for example ARRAY4 Logical adjacencies among clauses WAVES test vectors for example ARRAY4 Synthesized circuit for example ARRAY4 Behavioral description for example CASE2 Behavioral description for example GREATER3
180 180 181 182 182 183 185
Chapter 7 Figure 7-1 Figure 7-2 Figure 7-3 Figure 7-4 Figure 7-5 Figure 7-6 Figure 7-7 Figure 7-8 Figure 7-9 Figure 7-10 Chapter 8 Figure 8-1 Figure 8-2 Figure 8-3 Figure 8-4 Figure 8-5 Figure 8-6 Figure 8-7 Figure 8-8 Figure 8-9 Figure 8-10 Figure 8-11 Figure 8-12 Figure 8-13 Figure 8-14 Figure 8-15 Figure 8-16 Figure 8-17 Chapter 9 Appendix A Figure A-l Figure A-2 Figure A-3 Figure A-4 Figure A-5 Figure A-6 Figure A-7
Figure A-8 Figure A-9 Figure A-10 Figure A-ll Figure A-12 Figure A-13 Figure A-14 Figure A-15 Figure A-16 Figure A-17 Figure A-18 Figure A-19 Figure A-20 Figure A-21 Figure A-22 Figure A-23 Figure A-24 Figure A-25 Figure A-26 Figure A-27 Figure A-28 Figure A-29 Figure A-30
Fault classes for 3-bit signed GT function WAVES test vectors for example GREATER3 Synthesized Structurel for example GREATER3 Synthesized Structure3 for example GREATER3 Behavioral description for example GE23u Behavioral test vectors for example GE23u WAVES test vectors for example GE23u Synthesized circuit for example GE23u Behavioral description for example ADDSUB4 WAVES test vectors for example ADDSUB4 Synthesized circuit for example ADDSUB4 CLA test vectors for example ADDSUB4 CLA implementation of example ADDSUB4 Behavioral test vectors for example PLUS25 Synthesized Structurel for example PLUS25 Parse tree for example XOR4 WAVES test vectors for example XOR4 Structurel for example XOR4 Structure2 for example XOR4 Structure3 for example XOR4 Structure4 for example XOR4 Structure Cascade 1 for example XOR4 Structure Cascade2 for example XOR4
186 186 187 188 188 189 189 189 189 190 191 193 193 194 194 196 197 197 198 198 198 199 199
Process types for Level-0 Design restrictions for Synopsys
213 215
VHDL constructs that map to multiplexer elements Hardware implementation for case statement Hardware implementation for if statement Hardware implementation for vector indexing VHDL description for a ripple carry adder Hardware implementation of ripple carry adder Using functions to represent combinational logic Code example for simple //"statement Code example for if-else statement Synthesized hardware for if-else statement Code example for case statement
219 220 221 221 222 222 223 224 225 225 226
Appendix B Appendix C Appendix D Figure D-l Figure D-2 Appendix E Figure E-l Figure E-2 Figure E-3 Figure E-4 Figure E-5 Figure E-6 Figure E-7 Figure E-8 Figure E-9 Figure E-10 Figure E-l 1
XI
Figure E-12 Figure E-13 Appendix F
Synthesized hardware for case statement Code example for variable index assignment
226 227
List of Tables Chapter 1 Table 1-1 Table 1-2
Levels of detail commonly used in design Predefined VHDL operators
2 5
Chapter 2 Table 2-1 Table 2-2
Minimal SEF test set Micro-operation Faults
14 18
SSL fault table for SOP MUX Fault reductions Reduced fault table for SOP MUX Reduced fault table for POS MUX Generalized functional fault model SSL faults detected by behavioral test vectors Stuck-data and stuck-control behavioral faults Faults detected by test vector Set 1 Fault reductions for example IF2 Covering faults for external control line faults Reduced functional faults for example IF2 Generalized functional faults for example IF2 Behavioral test vectors for example DF2 Behavioral test vectors for example CASE1
32 32 33 34 35 38 39 39 42 42 43 44 47 51
Reduced functional faults for SOP GT Reduced functional faults for POS GT Functional faults for n-bit GT Behavioral faults for 2-bit GT Functional faults for n-bit GE Behavioral faults for 2-bit GE Functional faults for n-bit EQ Behavioral faults for 2-bit EQ Micro-operation Faults Test vectors for behavioral faults for A > B Test vectors for behavioral faults for A < B Test vectors for THEN-CORRUPT faults Test vectors for ELSIF-CORRUPT and ELSE-CORRUPT faults Final behavioral test vector set for example COMPARE
57 58 60 61 62 63 67 67 68 70 71 72 73 74
Chapter 3 Table 3-1 Table 3-2 Table 3-3 Table 3-4 Table 3-5 Table 3-6 Table 3-7 Table 3-8 Table 3-9 Table 3-10 Table 3-11 Table 3-12 Table 3-13 Table 3-14 Chapter 4 Table 4-1 Table 4-2 Table 4-3 Table 4-4 Table 4-5 Table 4-6 Table 4-7 Table 4-8 Table 4-9 Table 4-10 Table 4-11 Table 4-12 Table 4-13 Table 4-14
Xll
Xlll
Chapter 5 Table 5-1 Table 5-2 Table 5-3 Table 5-4 Table 5-5 Table 5-6 Table 5-7 Table 5-8 Table 5-9 Table 5-10 Table 5-11 Table 5-12 Table 5-13 Table 5-14 Table 5-15 Table 5-16 Table 5-17 Table 5-18 Table 5-19 Table 5-20
Truth table for full adder Phase I functional tests Phase II functional tests Phase III functional tests Functional tests for 4-bit ripple carry adder Functional tests for example ADD4wc Carries for 4-bit CLA adder Missing carry faults Extra carry faults Additional behavioral test vectors for CLA adder Behavioral test vectors for extra carry faults Behavioral test vectors for missing carry faults Optimized test vectors for missing carry faults Optimized test vectors for extra carry faults Truth table for full subtractor Functional tests for 4-bit direct subtraction Functional tests for adder by subtraction test vectors Functional tests for 4-bit increment function Functional tests for 6-bit function Z OZ YIO SELO Figure 3-2 Synthesized hardware for example IF1. The synthesized hardware implementing example IF1 has the two inputs, YO and Yl, connected to inputs A and B respectively of a 2-to-l multiplexer, MUX21. In subsequent discussions, these will be referred to as the channels of the multiplexer, Channel A (CHA) and Channel B(CHB).
3.1.2 Functional Analysis In order to perform a functional analysis similar to the method used by Hansen and Hayes [29] in their work on physically-induced faults, a gate level design of the multiplexer architecture is needed. To make the resulting models independent of any specific implementation, several different gate level realizations will be examined and compared. The first gate level multiplexer was obtained by expanding the functional element MUX21 one level lower in the design hierarchy. The resulting gate level circuit is recognized as a sum-of-products (SOP) implementation shown in Figure 3-3. YOO
YIO SEL Figure 3-3 SOP gate level circuit for MUX21. To analyze the gate level circuit, the effect of single-stuck-line (SSL) gate level faults will be examined. This analysis will determine a set of functional faults which are induced by the lower level SSL faults. Testing for these functional faults will then ensure complete testing for the original gate level faults. The gate level circuit contains 10 logical lines. Applying the SSL fault model where each line can be either stuck-at-0 or stuck-at-1, there are a total of 20 gate level SSL faults
32
in the circuit. The line labeled A being stuck-at-0 and stuck-at-1 will be indicated as A-0 and A-i respectively. By activating each SSL fault individually in the gate level circuit and evaluating the resulting output response to changing inputs, a fault table is obtained. In Table 3-1 the fault free behavior of the circuit is shown in column Z. For simplicity, only outputs due to a SSL fault that differ from the fault free behavior of the circuit are shown.
%
o1 1 o1 1 o1 N < < PQ ffl u
1—1
co
1
u
o
1
1
Q Q
o
o
i
1
i
W
o i
Ü
o 1 o Ü X X CO I
0
0
0
0
0
1
1
0
1
0
0
0
1
1
1
1
0
0
0
1
1
0
1
0
1
1
1
0
1
0
1
1
1
1
0
1
1
1
1
1 0
1
1
1
1 1
0
1
1
0
0
0
0
1
1—1
N N 1
0
0
0
0
i
CO
1
1
1
0
©
i
1
1 0
0
0
0
0
0
0
1 0
1 0 0
Table 3-1 SSL fault table for SOP MUX. Faults which cause the same faulty output can be considered functionally equivalent [45]. Such faults can be combined in the fault table, since there is no way to distinguish between these faults by observing the circuit's output behavior. To further reduce the functional faults, consider the concept of dominance of one fault over another. The fault (column) Fl is said to dominate the fault (column) F2 if Fl has a faulty output in at least every row in which F2 has a faulty output [45]. The dominating fault (column) Fl may be removed from the fault table, since any test which detects fault F2 will also detect fault Fl. Fault reductions due to functional equivalence and dominance are shown in Table 3-2. Faults
Remarks
Faults
Remarks
A-1,E-0,H-1,S-1,Z-1
Dominate G-l
C-0, D-0
Equivalent to A-0
B-l,D-l,E-l,S-0
Dominate C-l
F-0
Equivalent to G-l
Z-0
Dominate B-0
F-l, G-0, H-0
Equivalent to B-0
Table 3-2 Fault reductions.
33
Only four functional faults remain after applying the indicated fault reductions. Testing for this reduced set of faults will ensure complete coverage of all 20 original SSL gate level faults. The reduced fault table and appropriate test vectors are shown in Table 3-3. The two test vectors labeled mandatory are the only ones that cover a specific fault. For the other faults two options are available; selecting one test vector from each group will provide coverage for the faults in question. Test Vector
I—I
o
o
1
1
o 1
N < Ü PQ
00
>*
0
0
0
0
Option 1
0
0
1
1
Mandatory
0
1
0
0
Option 1
0
1
1
1
1
0
0
0
Mandatory
1
0
1
0
Option 2
1
1
0
1
0
Option 2
1
1
1
1
0
t
u
0 1 0
1
Table 3-3 Reduced fault table for SOP MUX.
3.1.3 Alternate Implementation In order to investigate an alternate gate level implementation of the multiplexer architecture, consider the Karnaugh map for the output function Z, shown in Figure 3-4. The groupings of minterms (l's), indicated by the dashed lines, produce an SOP representation consistent with the gate level circuit previously analyzed from Figure 3-3. \SELY1 Y0\ 00 0 (• 1 V
01
0
ii
10
u
tt (*) i i i i i
Figure 3-4 Karnaugh map for MUX.
34'
To obtain a product-of-sums (POS) implementation of the multiplexer, the maxterms (O's) are grouped, as indicated with the solid lines. The resulting function for the output is: Z = (SEL + YO) ■ (SEL +Y1). A gate level realization is shown in Figure 3-5. YOO
-A
Y1D— SELO-S-
B\
D
CHA
CHB ,GJ
Figure 3-5 POS gate level MUX. A functional analysis can now be performed on the SSL gate level faults for this circuit. After appropriate reductions for functional equivalence and fault dominance, the resulting fault table is shown in Table 3-4. Test Vector
1—I 1
o
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0
0
0
0
Mandatory
0
0
1
1
Option 1
0
1
0
0
0
1
1
1
Option 2
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0
0
0
1
Option 2
1
0
1
0
1
Mandatory
1
1
0
1
1
1
1
1
o 1
u
1 0 1
0
Table 3-4 Reduced fault table for POS MUX. It should be noted here that a NAND-NAND realization of the SOP circuit and a NOR-NOR realization of the POS circuit produce the same reduced fault tables shown in Table 3-3 and Table 3-4, respectively. The reduced set of functional faults only affect the controlling inputs to the multiplexer channels, which remain unchanged due to conversions to NAND-only or NOR-only circuits using DeMorgan's theorem [41].
35
3.1.4 Generalized Functional Fault Model Comparison of the reduced fault tables for both the SOP and POS implementations of the multiplexer can now yield a generalized functional fault model, not tied to a specific realization. There are no contradictions among the test vectors indicated in the two fault tables. Selection of the mandatory test vectors from each table provides complete coverage of the functional faults from both tables. A generalized functional fault model is, therefore, presented in Table 3-5. The functional faults have been renamed SOP_A, SOP_B, POS_A, and POS_B to indicate the origin of their mandatory test vector and the channel of the multiplexer which they corrupt. Testing based on the indicated vectors should provide complete coverage of gate level SSL faults for multiple multiplexer implementations.
Test Vector
" operator can fault to "=" (Class I) or "—' f-P~p
a(1:0)O
H> gOOglO-
Figure 4-11 Synthesized Structural for example COMPARE. According to MIL-STD 883D, Structurel contains 74 unique gate level SSL faults. Fault simulations were performed using the behavioral test vectors from Table 4-14. The behavioral test vector set detected 73 of the 74 SSL gate level faults, resulting in a fault coverage of 98.65%. The undetected fault was on input B to NAND gate zg3 shown in Figure 4-11. Exhaustive testing of the circuit Structurel reveals that this fault is, in fact, undetectable by any test vector due to redundant logic produced by the synthesis tool. In this case, an alternate measure of effectiveness can also be used to account for redundant logic. The fault efficiency is defined as the ratio of detected faults to detectable faults. For this example the fault efficiency is 73/73 = 100%. An alternate test vector set was formed by reversing the order of the Z = 0, Z = 1 pattern in Table 4-14. Application of this alternate set of behavioral test vectors, shown in Figure 4-12, to the circuit Structurel produced an identical fault coverage of 98.65%. Either set of test vectors developed from the behavioral fault models, therefore, achieved a fault efficiency of 100%.
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% AB Y2 Yl YO Z % Group I 500 0000 010 1 500 0101 101 0 500 1010 010 1 1111 101 0 500 Group II 500 0100 011 0 500 1001 100 1 500 1001 011 0 500 1110 100 1 % Group III 500 0001 110 0 1 500 0110 001 500 0110 110 0 1 500 1011 001
time ns ns ns ns ns ns ns ns ns ns ns ns
Figure 4-12 Alternate set of behavioral test vectors for example COMPARE. A second gate level implementation of example COMPARE was produced by allowing AutoLogic II to perform logic optimizations. Using these optimizations in a synthesis environment allows a designer to remove redundancies and reduce the number of undetectable faults. The resulting Structure2 is shown in Figure 4-13.
UlO
Figure 4-13 Synthesized Structure2 for example COMPARE. Structure2 contains 72 unique SSL gate level faults. Fault simulations using the original and alternate behavioral test vectors from Table 4-14 and Figure 4-12 both result in a fault coverage of 72/72 = 100%. The fault coverage as a function of the alternate behavioral test vectors is shown in Figure 4-14. When redundancies are not present in the gate level circuit, the test vector sets developed using the behavioral fault models achieve a gate level SSL fault coverage of 100%.
77
Coverage (%) 100
-,
i—'—r 1
2
~i—■—r 6
7
10
Number of Test Vectors
Figure 4-14 Fault coverage for Structure2 of example COMPARE. These results help validate the new behavioral fault models through practical application. The effects on fault coverage due to expansion of the control signals and data path will now be investigated.
4.6.2 Expansion of the Data Path In the VHDL behavioral description for example COMPARE, the input signals (Y2, Yl, Y0) and the output signal (Z) are each only a single bit wide. To demonstrate the effects of a wider data path on the new behavioral fault models, example COMPARE4 was created by changing the above signals to four bits wide, BIT_VECTOR(3 downto 0). For this example, the control signals A and B remained two bits each. The faults on the relational operators are unchanged due to the widening of the data path. Hence, the values of the control signals A and B are the same as those given in Table 4-14. The only change to the test vectors is the widening of the 1-bit signals to four bits. This is done by replication of the appropriate signal values, since the wider data path simply represents multiple copies of the 1-bit case implemented in parallel. The control faults on adjacent clauses developed in Section 4.5.2 are, likewise, unaffected by the widening of the data path. The only modifications necessary to the test vec-
78
tors is again replication of the appropriate signal values. Hence, the behavioral test vectors for example COMPARE4 are presented in Figure 4-15.
% AB Y2 Yl % Group I 0000 1111 0000 0101 0000 1111 1010 1111 0000 1111 0000 1111 % Group II 0100 1111 0000 1001 0000 1111 1001 1111 0000 1110 0000 1111 % Group III 0001 0000 0000 0110 1111 1111 0110 0000 0000
time
Y0 1111 0000 1111 0000
0000 1111 0000 1111
500 500 500 500
ns ns ns ns
0000 1111 0000 1111
1111 0000 1111 0000
500 500 500 500
ns ns ns ns
1111 0000 1111 1011 1111 1111 0000
1111 0000 1111 0000
500 500 500 500
ns ns ns ns
Figure 4-15 Behavioral test vectors for example COMPARE4. Example COMPARE4 was synthesized and optimized with AutoLogic II to produce the gate level Structure shown in Figure 4-16. Fault simulations were performed using the test vectors derived from the behavioral fault models. The results show a fault coverage of 150/150 = 100%; all SSL gate level faults are detected.
H> Figure 4-16 Synthesized Structure for example COMPARE4.
79
As was done previously, an alternate test vector set was formed for example COMPARE4 by reversing the order of the Z = 0, Z = 1 pattern in Figure 4-15. Fault simulation using these alternate behavioral test vectors again resulted in gate level fault coverage of 100%. Though the number of unique gate level faults more than doubled, the same number of test vectors, 12, were able to provide complete SSL fault coverage.
4.6.3 Expansion of the Control Signals Example COMPARE was next modified by increasing the width of the control signals A and B from two bits to three bits each. The change in size of the control signals does affect the behavioral faults for the relational operators. Recall the number of faults on a comparison is related to the number of bits being compared. The increase from two bits to three bits causes the number of Group I faults from Table 4-14 to increase from 22 = 4 to 23 = 8. The number of Group II and Group III faults likewise increases to 23 -1 = 7. In contrast to the faults on relational operators, the control faults are affected only by adjacency among clauses. Recall from Table 4-13 that the ELSIF-CORRUPT (by THEN) faults corresponded to the A > B Class II faults. In the 2-bit case, only a single combination of A and B produced the proper adjacency, forcing the selection of both test vector options to cover both the Clause-CORRUPT (OR) and Clause-CORRUPT (AND)i'faults. In the 3 bit case, there are now 23"1 -1 = 3 different combinations of A and B that produce the proper adjacency between clauses (see Figure 4-3). Through proper selection of test vectors from the faults on relational operators, it is possible to provide coverage for all control faults without replication of values for A and B. A final set of behavioral test vectors for example COMPARE3 is, hence, presented in Figure 4-17. % A B Y2Y1Y0 Z % Group I 000 000 101 0 001 001 101 0 010 010 010 1 011 011 010 1 100 100 101 0 101 101 101 0 110 110 010 1 111 111 010 1
time ; 500 500 500 500 500 500 500 500
ns ns ns ns ns ns ns ns
Figure 4-17 Behavioral test vectors for example COMPARE3.
80
% Group 001 000 010 001 Oil 010 100 Oil 101 100 110 101 111 110 % Group 000 001 001 010 010 Oil 011 100 100 101 101 110 110 111
II Oil Oil 100 100 Oil Oil 100 III 110 110 001 001 110 110 001
0 0 1 1 0 0 1
500 500 500 500 500 500 500
ns ns ns ns ns ns ns
0 0 1 1 0 0 1
500 500 500 500 500 500 500
ns ns ns ns ns ns ns
Figure 4-17 Behavioral test vectors for example COMPARE3. Example COMPARE3 was then synthesized and optimized by AutoLogic II to produce the gate level implementation shown in Figure 4-18.
Figure 4-18 Synthesized Structure for example COMPARE3. Fault simulations were conducted on the gate level Structure for example COMPARE3 using the derived set of behavioral test vectors. A SSL gate level fault coverage of 92/92 = 100% was achieved. As in previous examples, fault simulation with an alternate set of behavioral test vectors again resulted in complete gate level fault coverage.
4.7 Conclusions New behavioral fault models have been developed for the predefined VHDL relational operators from Table 1-2. These fault models are based on a functional analysis of the comparison functions GT and EQ. The symmetry of these comparison functions allowed the resulting generalized functional faults to be easily adapted for all the relational operators.
81
The new behavioral fault models developed for relational operators are based on the size of the hardware implementation and, therefore, eliminate the need to supplement test vector sets via methods such as heuristics. While the new fault models are more complex than previous ones, this is because they more accurately reflect the underlying complexity of the hardware faults which they attempt to model. A simple example was presented to demonstrate the application of the new fault models. Test vector sets were formed based on behavioral faults to the relational operators and the control construct if-then-else. These behavioral test vectors were then applied to synthesized gate level realizations. Gate level fault coverage was used to evaluate the effectiveness of the new behavioral fault models. When redundancies were not present in the synthesized gate level circuits, both the primary and alternate test vector sets developed using the behavioral fault models'produced a gate level SSL fault coverage of 100%. Even with undetectable faults, the behavioral test vectors were able to achieve a. fault efficiency of 100%.
Chapter 5 Arithmetic Operators Like the relational operators, arithmetic operators also generate large blocks of combinational logic. The predefined VHDL operators ADD (+) and SUB (-) are normally implemented by synthesis tools with standard library modules. Optimizations for speed or chip area may modify these building blocks, however, the basic function of the arithmetic operators remains unchanged. A fault modeling technique is proposed here based on complete functional testing of the arithmetic building blocks. By concentrating on functional testing, complete gate level SSL fault coverage should be obtained over a broad range of hardware implementations. Previous behavioral modeling approaches, based on perturbing language constructs such as ADD to SUB, do not accurately reflect underlying hardware faults. In order to compensate for this "big micro-operation problem," alternate methods such as heuristics were used to supplement test vector sets to increase the equivalent gate level fault coverage. The new modeling technique presented in this chapter increases the complexity of the fault models for the arithmetic operators, providing a better representation of the faults which occur in actual hardware.
5.1 Addition The ADD operation has several basic forms which will be investigated in succession. A two-level network would be the fastest, however, this circuit would require a large number of gates and gate inputs. It would be necessary to have 22n NAND gates of 2n + 1 inputs and one NAND gate of 22n inputs to add two n-bit numbers [41]. This number of gates and inputs is quite significant for even small values of n. In contrast to this direct approach, adders are most commonly implemented by the interconnection of smaller functional building blocks. In its simplest from, a half adder (HA) is a multiple output combinational circuit which adds two bits to produce a sum and a carry-out. A full adder (FA) adds two binary digits and a carry-in from a previous stage. To speed up the combinational addition process, by reducing the rippling of carries between stages, methods such as carry look-ahead (CLA) are used.
82
83
5.1.1 Ripple Carry Adder Behavioral modeling of the ADD operation has two basic forms, depending on the presence of an overall carry-in and carry-out for the resulting adder circuit. In its simplest form, the addition of two n-bit binary numbers can be represented as: S D—M/**
O^ Figure 5-5 NOR-only realization of example ADD4. 5.1.1.5
Carry-in and Carry-out
The more complex form of behavioral addition includes a carry-in and/or a carry-out. Since the predefined VHDL ADD operator combines two n-bit operands to form an «-bit result, some additional manipulation is required to deal with the extra carries. The carryout is produced by simply extending the ADD operation to n+1 bits and extracting the most significant bit of the result. The carry-in can be modeled by an extra addition of a single bit. Example ADD4wc, in Figure 5-6, demonstrates the behavioral description of a 4-bit addition with carries.
90
entity add4wc port(A, B D CIN COUT end add4wc;
is in out in out
std_logic_vector(3 downto 0); std_logic_vector(3 downto 0); std_logic; std_logic);
architecture behave of add4wc is begin process (A, B, CIN). variable opl,op2,sum: std_logic_vector(4 downto 0); variable carry_in : std_logic_vector(1 downto 0); begin opl := x0' & A; op2 := '0' & B; carry_in := x0' & CIN; sum := opl + op2 + carry_in; D when 3 => end case;
Z Z Z Z
B then GT -
it> -O-f
^z^^>-
^r^^E>^ Figure A-22 Synthesized Structural for example PLUS25. Fault simulations using the behavioral test vectors from Figure A-21 resulted in a SSL gate level fault coverage of 114/115 = 99.13%. The functional testing approach is still
195
able to achieve near complete fault coverage. An alternate synthesis tool and target architecture was next used to produce Structure2 for example PLUS25. Fault simulations using the behavioral test vectors from Figure A-21 resulted in a SSL gate level fault coverage of 190/190 = 100%.
A.6.2 Example MINUS25 Example MINUS25 performs the arithmetic operation Z perform_add; when X"01" => perform_subtract; when others => signal_illegal_opcode; end case; case element_color is when red => statements for red; when green | blue => statements for green or blue when orange to turquoise => statements for these colors; end case;
C.5 Loop Statements VHDL has a basic loop statement, which can be augmented to form the usual while and for loops seen in other programming languages. The while iteration scheme allows a test condition to be evaluated before each iteration. The iteration only proceeds if the test evaluates to true. If the test is false, the loop statement terminates. An example [11]:
while index < length loop index := index + 1; end loop; The for iteration scheme allows a specified number of iterations. The loop parameter specification declares an object which takes on successive values from the given range for each iteration of the loop. Within the statements enclosed in the loop, the object is treated as a constant, and so may not be assigned to. An example [11]:
for item in 1 to last_itern loop table(item) := 0; end loop; There are two additional statements which can be used inside a loop to modify the basic pattern of iteration. The next statement terminates execution of the current iteration
209
and starts the subsequent iteration. The exit statement terminates execution of the current iteration and terminates the loop. The syntax of these statements is:
next_statement : := next [ loop_label ] [ when condition ] ; exit_statement : := exit [ loop_label ] [ when condition ] ; If the loop label is omitted, the statement applies to the inner-most enclosing loop, otherwise it applies to the named loop. If the when clause is present but the condition is false, the iteration continues normally.
C.6 Process Statement The primary unit of behavioral description in VHDL is the process. A process is a sequential body of code which can be activated in response to changes in state specified by a sensitivity list or a wait statement. When more than one process is activated at the same time, they execute concurrently. An example of a process statement with a sensitivity list [11]:
process (reset, clock) variable state : bit := false; begin if reset then state := false; elsif clock = true then state := not state; end if; q tf E •
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