Charge-Based Modeling of Junctionless Double-Gate Field-Effect ...

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ANEW concept of junctionless field-effect transistor (FET) consisting in a triple-gate architecture has been recently simulated in [1] and validated in [2]. Similarly ...
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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011

Charge-Based Modeling of Junctionless Double-Gate Field-Effect Transistors Jean-Michel Sallese, Nicolas Chevillon, Christophe Lallement, Member, IEEE, Benjamin Iñiguez, Senior Member, IEEE, and Fabien Prégaldiny

Abstract—We derived an analytical model for the junctionless double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) device, the principle of which has been recently demonstrated. Despite some similarities with classical junction-based DG MOSFETs, the charge–potential relationships are quite different and cannot be merely mapped on existing multigate formalisms. This is particularly true for the technological parameters of interest where reported doping densities exceed 1019 cm−3 for 10- and 20-nm silicon channel thicknesses. Assessment of the model with numerical simulations confirms its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. Index Terms—FETs, MOS devices, semiconductor device modeling, silicon devices, transistors.

I. I NTRODUCTION

A

NEW concept of junctionless field-effect transistor (FET) consisting in a triple-gate architecture has been recently simulated in [1] and validated in [2]. Similarly, other topologies have been also proposed in [3] and [4], which are known as “vertical-slit FET” devices. In an attempt to develop a generic core model for this family of emerging devices, we focused our research on a symmetric double-gate (DG) structure, the potential distribution of which is sketched in Fig. 1. This consists in a uniformly n-type doped silicon layer of a few dozens of nanometers thick squeezed between two gates, just as for a DG metal–oxide–semiconductor FET (MOSFET) but where the source and the drain have the same doping type as the channel. A major difference with

Manuscript received March 1, 2011; revised April 12, 2011 and May 6, 2011; accepted May 9, 2011. Date of publication June 9, 2011; date of current version July 22, 2011. This work was supported in part by the framework of Swiss National Science Foundation under SNF Project 200021-132319; by research projects European Union (EU) COmpact MOdeling Network (COMON) Industry Academia Partnerships and Pathways under Project FP7IAPP-218255, EU Silicon Quantum Wire Transistors (SQWIRE) under Project FP7-ICT-STREP 257111, and EU NANOSIL Network of Excellence under Project FP7-NOE-216171; by the Spanish Government under Grant TEC200806758-C02-02; by the Institució Catalana de Recerca i Estudis Avançats Award; and by the PGIR/15 Grant from the Universitat Rovira i Virgili. The review of this paper was arranged by Editor H. Jaouen. J.-M. Sallese is with the Ecole Polytechnique Fédérale de Lausanne, 1015 Lausanne, Switzerland. N. Chevillon, C. Lallement, and F. Prégaldiny are with the Institut d’Électronique du Solide et des Systèmes, Centre National de la Recherche Scientifique, Université de Strasbourg, Parc d’innovation, 67412 Illkirch, France. B. Iñiguez is with the Departament de Énginyeria Electronica, Eléctrica, i Automatica, Universitat Rovira i Virgili, 43007 Tarragona, Spain. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2011.2156413

Fig. 1. Sketch of the energy diagram for the junctionless doped DG MOSFET.

respect to DG MOSFETs is that only majority carriers carry the current, in contrast with the inverted channel of a DG MOSFET. This junctionless technology presents many advantages [1], [3] such as lack of abrupt junctions that can be hardly controlled at the nanometer scale, simpler fabrication process, lesser variability, and volume conduction implying that surface roughness scattering and flicker noise are expected to be minimized. It has been reported that thin-film DG devices in the accumulation mode (AM) have better short-channel effects and related drain-induced barrier lowering (DIBL) than normal inverted channel multigate FETs [4]. High Ion /Ioff ratios and ideal subthreshold slope have been also simulated [1] and measured. Although modeling has been done for the AM SOI MOSFET [5], [6], there is still no analytical model for ultrathin DG junctionless devices. In order to estimate whether we can rely on a chargebased model for undoped DG MOSFETs [7] or on the related equivalent-silicon-thickness concept valid in its doped version [8], we propose to estimate the limit of the validity of such an approach when applied to junctionless DG MOSFETs. After bringing evidence that a new model is indeed needed, we will propose analytical solutions to calculate charges and currents in junctionless DG MOSFETs. II. E LECTROSTATICS IN J UNCTIONLESS DG MOSFET S Without loss of generality, we consider a junctionless DG MOSFET having a semiconductor thickness TSC and a density of donor ND . A cross section of this structure in terms of potentials is shown in Fig. 1.

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SALLESE et al.: CHARGE-BASED MODELING OF JUNCTIONLESS DG FETs

A. Limitations of Junction-Based DG MOSFET Models to Simulate Junctionless Devices

B. Approximate Solution to the Poisson Equation

Although junction-based and junctionless architectures are very similar, the principle of operation of junctionless devices is quite different from that of standard DG MOSFETs. In a junctionless DG MOSFET, the effect of the gate is to deplete or accumulate majority carriers from the doped silicon layer and not to create an inverted layer at the semiconductor–insulator interface. Therefore, even at high gate voltages, majority carriers essentially flow in the volume of the semiconductor. Recalling basic relationships for the doped DG MOSFET: Likewise, for the doped junction-based DG MOSFET [8], merging the Poisson relationship with the nondegenerate Boltzmann statistics leads to a relationship between the surface electric field and the surface potential, the source being used as reference for the potentials (only the sign has been changed with respect to [8] when considering ionized donor atoms). Then, we get  ψ−V q  d2 ψ UT n = · e − N i D dx2 εSi

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(1)

This differential equation has no analytical solution. Once integrating [8], we obtain  2 QSC ES2 = 2 · εSi  ψ −V   ψ0 −V S 2 · q · ni · UT ND (ψS − ψ0 ) UT UT = −e e − εSi ni UT (2) where QSC is the charge density in the semiconductor, V and ψS = ψ(TSC /2) are the quasi Fermi potential for electrons and the surface potential, respectively, ni is the intrinsic carrier concentration, and ψ0 = ψ(0) is the potential at the center of the semiconductor. However, except the sign of the ionized donor charge density, the differential equation governing the charge distribution [see relationship (1)] is apparently the same as that in [8] where we found that the doping density in a DG MOSFET could be accounted for in the definition of an equivalent semiconductor thickness. Since accurate results have been obtained, we can wonder if this definition is still a good concept for junctionless devices, keeping in mind that the principle of operation is totally different. Adopting the definition of the equivalent semiconductor thickness Teq for ntype doped silicon layers [8] gives ⎡ ⎤−1 0 −q·ND 2 q · ND · TSC ⎢ ⎥ ·x2 =⎣ e 2·εSi ·UT dx⎦ − (3) Teq 2 · εSi · UT −TSC /2

From (3), we find that, in junctionless architectures, Teq can take a negative value for relatively high doping concentrations, hence generating unphysical imaginary charge densities [8]. As it will be confirmed along this paper, although this definition is linked to a particular model, it still reveals that these devices require different modeling approaches. This is developed in next sections.

Considering an n-type doped semiconductor, we focus our analysis on the depletion and accumulation modes or the AM, which are relevant for junctionless MOSFETs. As already mentioned, neglecting hole density and assuming a nondegenerate semiconductor, the Poisson equation leads to the differential equation (1), which, to our knowledge, has no exact solution. Before going one step further, it is worth evaluating the limit of the validity of the Boltzmann statistic adopted in (1), since quite high doping concentrations will be investigated. Ideally, the Boltzmann statistics should not be used when the free-carrier density exceeds the effective density of states. Concerning electrons in silicon, this would correspond to about 3 × 1019 cm−3 at room temperature. However, as we will see, we found no evidence that relying on the Boltzmann statistics introduces any substantial error with doping levels as high as 5 × 1019 cm−3 (note that this is also the case in the channel of MOSFETs where the charge sheet density can go beyond that limit). Here, we propose to seek for an approximate solution to (1) by relying on a coarse “finite-difference” method. Adopting the discrete values represented in Fig. 1, the second derivative of the potential can be then expressed as       ψ −T2SC − ψ(0) ψ(0) − ψ TSC 1 d2 ψ  2 = − · TSC  T T 2 SC SC dx x=0 2 2 2 (4) In addition, under symmetrical operation, the electric field at the center is zero, which gives      ψ TSC − ψ −T2SC dψ  2 = =0 (5) dx x=0 TSC Finally, merging (1), (4), and (5) leads to   2 ψ0 −V q · TSC UT (ψS − ψ0 ) = − ND ni · e 8 · εSi

(6)

where ψS = ψ(TSC /2) and ψ0 = ψ(0) are the potentials at the surface and at the center of the layer, respectively. Since (6) links the surface potential to the potential at the center of the semiconductor, once ψ0 is given, ψS can be calculated. Here, we can already make some remarks. When the discretization step reverts to the spatial coordinate x, (6) can be considered as a generalization of the well-known depletion approximation that has been also used in [8]. Indeed, when the mobile charge density is negligible with respect to the fixed charge density, this relationship reverts to the exact solution of the Poisson equation in totally depleted semiconductors. Similarly, when mobile charges cannot be neglected, we still end up with a parabolic dependence of the semiconductor potential with x. However, it is worth noticing that this parabolic “shape” is not a priori imposed but results from the discretization of the Poisson equation on three points only. Yet, we will see that the total mobile charge density will not be obtained by integrating the carrier density over this parabola but will rely on a more elaborate approach that will somehow relax this approximation.

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In addition, the thinner the semiconductor, the more valid this approximation will be, since the discretization step will become smaller. Nonparabolicity is also more pronounced when the device operates in accumulation rather than in depletion. However, since working devices are expected to be highly doped in order to achieve high performances [1], these will be hardly biased in strong accumulation but most likely in depletion (the on-current at flat band is still high). Therefore, we expect that this approach will be still accurate enough to predict highly doped device characteristics for practical applications. From (2), the charge density in the semiconductor is expressed as a function of the potential at the center of the film and of the Fermi potential, i.e.,  QSC = 2 · sign (ψ0 − ψS ) · 2 · q · ni · εSi · UT   ψS −V ψ0 −V ND (ψS − ψ0 ) · (7) e UT − e UT − ni UT where the sign function is consistent with the semiconductor charge density. Indeed, contrary with the classical DG MOSFET, QSC can be either positive or negative, depending whether the potential at the surface is lower or higher than the one at the center. Therefore, a critical condition may happen at the flat band. From (1), semiconductor neutrality is achieved when d2 ψ/dx2 = 0, which happens when   ND ψ0 = ψ0FB = V + UT · ln (8) ni Here, ψ0FB refers to the flat-band center potential. When ψ0 = ψ0FB , relationship (1) imposes ψ(x) = ψ0FB for all values of x, i.e., neutrality “locally” takes place and the potential is constant across the whole semiconductor layer (ψS = ψ0 ). C. General Approach to the Mobile Charge Calculation The total charge is composed of mobile Qm and fixed charges densities, the latter holding for the ionized donor atoms, i.e., QSC = Qm + qND TSC

(9)

On the other hand, the semiconductor charge density is also related to the potential drop across gate insulators, i.e., (VG − Δφ − ψS ) · 2 · Cox = −QSC

(10)

According to (10), relationship (7) can be written as (VG − Δφ − ψS ) · 2 · Cox

 = −2 · sign(ψ0 − ψS ) · 2 · q · ni · εSi · UT   ψS −V ψ0 −V ND (ψS − ψ0 ) · e UT − e UT − ni UT

(11)

Combining (6) with (11) and defining C = e(ψ0 −V /UT ) and 2 )/(8 · UT · εSi ), the mobile charge density is K = (q · ni · TSC

obtained through the evaluation of C after solving the general equation, i.e., VG − V − Δφ

  ND = UT · ln(C) + K · UT · C − ni √ 2 · q · ni · εSi · UT − sign(ψ0 − ψS ) · Cox ·       2  ND ND ND · C · exp K C − · K −1 + ·K − ni ni ni (12)

For given gate and channel potentials, variable C can be numerically solved with standard routines. The charge density is readily obtained from (6) and (10), i.e.,  ND QSC = −2 · Cox · VG − V − Δφ + K · UT · ni  − K · UT · C − UT · ln(C) (13) Here, it is worth noticing that the parabolic shape of the potential was merely used to link the potential at the surface to its value at the center, hence getting (12) from (11). However, (11) has been obtained from an exact integration of (1). As discussed before, this is a major difference with respect to a finite-difference approach that would impose a given potential shape to calculate the charge density across the semiconductor. Although we are not yet at the point where we get an explicit expression, this still represents an interesting formulation that prevents solving the nonlinear second-order differential equation including the constrain arising from the gate voltage [cf. (1) and (10)]. Without entering into the details, we checked that (12) and (13) also apply to almost undoped devices, i.e., for silicon doping densities of about 1015 cm−3 , as well as to junction-based DG MOSFETs provided that −NA is used instead of ND . However, we will see that this formulation still requires some simplifications in order to express the current in an analytical form. Therefore, starting from (12), we propose to derive new expressions for the charge–potential dependence that will lead to more explicit formulations. D. Approximate Expressions for Charges Depending on the ratio between mobile and fixed charge densities, simplified expressions for the charge–potential dependence are developed in the following sections. Junctionless DG MOSFET in Accumulation: Numerically solving the differential equation (1), it comes out that the central potential reaches an asymptote as the transistor enters the AM, i.e., when ψ0 increases above ψ0FB . Concerning undoped DG MOSFETs, an upper limit was indeed predicted from the exact solution [9] (which does not exist for the doped case). From a physical point of view, this can be interpreted as the screening of the electric field from the high mobile carrier density in the semiconductor. Therefore, we found that the central potential remains very close to the value it gets under flat-band

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From (16), the flat-band condition (QSC = 0) corresponds to VG − V − Δφ = UT · ln(ND /ni ), which is the expected result. Junctionless DG MOSFET in Depletion: In the case of depletion, the potential at the center becomes higher than the surface potential, and the semiconductor becomes positively charged, i.e., QSC ≥ 0, implying that the exponential is lower than unity in (12). This allows further simplifications. For instance, accurate results have been obtained by assuming C = ND /ni in the exponential term of (12), which is a kind of flatband condition, leading to the following relationship:     dep ND ND QSC ≈ 2 · 2 · q · ni · εSi · UT · K · · −C ni ni (17) Fig. 2. Semiconductor charge density as a function of the potential at the center in a 20-nm silicon layer of a junctionless DG MOSFET with various doping concentrations. (Arrows) Surface potential corresponding to flat-band conditions.

conditions, i.e., ψ0 ≈ ψ0FB , which is even more valid as the doping is increased. Fig. 2 shows how the central potential varies with respect to the mobile charge density for different doping concentrations. For instance, considering a silicon layer of 20 nm doped up to 5 × 1018 cm−3 , the upper limit for ψ0 is found to be 0.508 V, which is almost ψ0FB . This vertical asymptote is more pronounced when the doping concentration increases, as suggested from the graph. This is a quite interesting result that will help us in deriving an approximate expression for above flat-band conditions. Replacing ψ0 by ψ0FB in (7) leads to (in accumulation ψS − ψ0 ≥ 0)  acc QSC ≈ −2 · 2 · q · ni · εSi · UT       ψS −V ND ND ψS −V ND · − ln e UT − − ni ni UT ni (14) Noting that the ratio between the left- and right-hand-side (LHS and RHS) terms in the square root is always larger than unity for above flat-band conditions (and becomes unity at the flat band), we propose to omit the RHS member in the square root. In accumulation, (14) simplifies into   ψS −V  acc ND UT − QSC ≈ −2 · 2 · q · ni · εSi · UT · e ni (15) From (15), when ψS = ψ0 , the semiconductor still satisfies the neutrality condition. Replacing ψS − V obtained from (15) in (10), after some manipulation, we get   ND VG − V − Δφ − UT · ln ni   acc −QSC Q2SC ≈ + UT · ln 1 + (16) 2 · Cox 8 · q · ND · εSi · UT

Expressing parameter C as a function of the total charge in the semiconductor, we get   2  dep ND QSC C ≈ (18) · 1− ni q · ND · TSC Replacing (18) in (12) and rearranging the terms yield a chargebased relationship valid in the depletion mode, i.e.,   ND VG − V − Δφ − UT · ln ni   2 dep QSC Q2SC QSC ≈ − − + UT · ln 1− 8 · q · ND · εSi 2 · Cox q · ND · TSC (19) Likewise, for accumulation, (19) predicts that the gate voltage will indeed satisfy VG − V − Δφ = UT · ln(ND /ni ) under flat-band conditions, i.e., QSC = 0. This point is very important since it ensures that continuity is satisfied at the transition between depletion and accumulation. Equations (16) and (19) are then compatible. These “regional” approximations are evaluated with respect to the “exact” solution given by (12) with (13). Results of these calculations are displayed in Fig. 3, where circles indicate the transition between the AM and the depletion mode used to rely either on (16) or (19), respectively. It comes out that the approximations proposed so far are quite accurate and well sounded. Assessment of the Mobile Charge Density: In order to check the validity of the former approach, we ran technologycomputer-aided-design (TCAD) numerical simulation (Silvaco). The electron mobility was set to 0.1 m2 /Vs (constant mobility), the channel length and the width of the device were 1 μm to avoid short- and narrow-channel effects, and the oxide thickness was 1.5 nm. We also ignored channel quantization, which is a good approximation for silicon layers thicker than 10 nm. Finally, the same set of parameters was used for TCAD simulations and for the model without introducing any empirical parameter. The mobile charge density evaluated from (16) and (19) was compared with the TCAD simulations for different silicon thicknesses and doping densities of junctionless DG

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Fig. 3. Comparison of the mobile charge density in a 20-nm junctionless DG MOSFET obtained (dashed lines) from (12) and (13), and (solid lines) from “regional” approximations given by (16) and (19). (Open circles) Flat-band conditions that set the limit of validity for the approximated relationships. The numbers indicate the values of VFB − ΔΦ.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011

Fig. 5. Mobile charge density versus gate voltage for a 20-nm-siliconthickness junctionless DG MOSFET for different doping concentrations. (Solid lines) Model. (Dashed lines) TCAD simulations.

Fig. 6. Mobile charge density versus gate voltage for a 40-nm-siliconthickness junctionless DG MOSFET for different doping concentrations. (Solid lines) Model. (Dashed lines) TCAD simulations. Fig. 4. Mobile charge density versus gate voltage for a 10-nm-siliconthickness junctionless DG MOSFET for different doping concentrations. (Solid lines) Model. (Dashed lines) TCAD simulations.

MOSFETs, imposing the quasi Fermi potential of the channel to 0 V (see Figs. 4–6, respectively) for 10-, 20-, and 40-nm silicon thicknesses. For both linear and logarithmic scales, the agreement between the model and the TCAD simulations is good. In particular, the knee that appears below flat-band conditions is well tracked by the model. The slope of the charge versus the potential dependence does not match the gate oxide capacitance Cox any longer, although the device is biased well above threshold (we will define threshold conditions later on). This deviation from the junction-based DG MOSFET is one of the major peculiarities of junctionless DG MOSFETs, which cannot be tracked by the model in [8] and neither by other junction-based approaches. Nevertheless, we can mention that this effect is less pronounced for thinner silicon thicknesses and/or lower doping densities. Therefore, it could be that a junction-based DG

MOSFET model could also fit electrical characteristics of lowdoped junctionless devices (we indeed checked that this happens), but such a model is not predictive with respect to the technological parameters. In deep depletion, the mobile charge density varies with a slope of 60 mV/dec at room temperature, just as for a junctionbased DG MOSFET operating in weak inversion. Concerning the 20- and 40-nm layers, we observe that there is an upper limit for the doping concentration that prevents the full depletion in the silicon slab and therefore impedes switching off the device. Under equilibrium conditions, this comes from inversion layers (holes in our case) that build up at the Si/SiO2 interfaces. For instance, this happens around (VG − ΔΦ ∼ −2 V) in the 20-nm devices doped at 2 × 1019 cm−3 and close to (VG − ΔΦ ∼ −1 V) in the 40-nm doped at 5 × 1018 cm−3 . This behavior, which is not predicted by the model that still suggests that full depletion can be reached for even lower gate voltages, represents an intrinsic limit that must be kept in mind when moving to large/highly doped junctionless devices.

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drops for doping densities exceeding some 1018 cm−3 . This unusual behavior of the nonmonotonic variation of the threshold voltage with doping is quite interesting and can be used to find the best thickness versus doping combination for a given VT , which has no counterpart in junction-based MOSFETs (note that, for a given silicon thickness, there is a doping level that leads to the same threshold voltage as for the undoped device). III. D ERIVATION OF THE C URRENT As in [8], we assume that the current density can be calculated, adopting the drift and diffusion model. In this case, the current is given by I = −W · μ · Qm · Fig. 7. Threshold-voltage contributions as a function of the doping concentration in junctionless DG MOSFET for (full circles) 10-, (open circles) 20-, and (triangles) 40-nm silicon thicknesses. (Solid lines) VT − ΔΦ. (Dashed lines with symbols) Electrostatic contribution [RHS in (20)]. (Dashed line without symbols) Center potential [LHS in (18), independent of TSC ].

E. Threshold Voltage in Junctionless FETs Conversely, to the DG MOSFET, the notion of threshold voltage is much less obvious in the case of junctionless devices. Indeed, extrapolating the mobile charge density from the almost-linear strong inversion asymptote is no longer valid when high doping concentration and/or thick layers are concerned. For instance, when considering a 20-nm junctionless DG MOSFET, Figs. 3 and Fig. 5 evidence two slopes in the Q−V dependence, still below flat-band conditions delimited by open circles. This unusual characteristic for junctionless DG MOSFETs comes from the square term in (19) when the device operates in depletion (which must happen before switching off the channel). However, we can still define a threshold voltage as being the gate potential that cancels the mobile charge density when the logarithmic term is neglected, meaning that we simply ignore deep depletion where the mobile charge density exponentially varies with respect to the gate voltage. It is worth noticing that this reverts to the definition that we used when considering junction-based DG MOSFETs [8]. Adopting this definition and setting Qm = 0 in (9), from (19), we get   ND VT = Δφ + UT · ln ni   1 1 −q · ND · TSC · + (20) 2 · Cox 8 · CSC From (20), the threshold voltage exhibits both linear and logarithmic dependences upon the doping density. Fig. 7 reveals that these contributions vary in the opposite way and only the “electrostatic” term varies with the silicon thickness, the “semiconductor” one being independent of the technological parameters. As far as the doping density remains below to 1018 cm−3 , the threshold voltage is first slightly increasing before it rapidly

dV dx

(21)

where μ is the carrier mobility (assumed constant along the channel), Qm is the local mobile charge density, and V is the Fermi potential. Introducing the silicon charge density in (21) and integrating from the source to the drain, we obtain the following general relationship: W ·μ· I= L

D (qND TSC − QSC ) · dV S

W W · μ · q · ND · TSC · VDS − ·μ· = L L

D QSC · dV (22) S

Unfortunately, the quite complex relationship between the charge density and potential V as obtained from the general charge–potential dependence (12) does not lead to any analytical expression for the current. On the other hand, based on approximate expressions developed for the AM and the depletion mode, we propose to derive a complete analytical expression for the current valid in all regions of operation. A. Current in Accumulation Following the previous approach, we can now use (16) to calculate the current in accumulation. Differentiating (16) with respect to QSC gives the differential term inside the integral of (22), i.e., Q2SC ·dQSC

QSC dQSC 4·q·ND ·εSi QSC dV ≈ − Q2 2 · Cox 1 + 8·q·NDSC ·εSi ·UT acc

(23)

After integration, we obtain   D  D 1 QSC · dV  = · Q2SC S − 2 · UT 4 · COX  S acc   · QSC − 8 · q · ND · εSi · UT  · arctg

QSC √ 8 · q · ND · εSi · UT

 D    S

(24)

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Next, inserting this expression in (22), the current in accumulation can be calculated from the values of the charge densities (mobile and fixed) evaluated from (16) at the source and the drain.

plying that VG − VD − Δφ ≤ UT · ln(ND /ni ). The current becomes I=

W · μ · q · ND · TSC · VDS L

B. Current in Depletion −

Similarly, we rely on (19) to evaluate the integral term of (22), leading to dep

QSC dV ≈

Q2SC dQSC QSC dQSC + 4 · q · ND · εSi 2 · Cox + UT ·

2·Q2SC dQSC (q·ND ·TSC )2

1−



QSC q·ND ·TSC

2

(25)

As for accumulation, the following analytical expression exists after integration:   D  QSC · dV   S

dep

D D 1 1 = · Q3SC S + · Q2SC S 12 · q · ND · εSi 4 · Cox − 2 · UT · QSC |D S + UT · (q · ND · TSC )     D QSC QSC · ln 1 + − ln 1 − q · ND · TSC q · ND · TSC S (26)

Inserting this expression in (22) and evaluating the charges at the source and the drain from (19), the current can be calculated in depletion. C. General Treatment of the Current in Junctionless DG MOSFETs

W · μ · q · ND · TSC · VDS L  ⎛ D   W · μ · ⎝ QSC · dV  − L  S

W ⎜ ·μ·⎝ L

D S

   QSC · dV  

⎞ ⎟ ⎠

(28)

dep

“Hybrid” Channel: In between these asymptotes is the most important case where a part of the channel is in accumulation, i.e., from the source to some flat-band position along the channel, and the rest is in depletion, i.e., from the flat-band coordinate up to the drain node. This special case occurs when VG − VS − Δφ ≥ UT · ln(ND /ni ) and VG − VD − Δφ ≤ UT · ln(ND /ni ). The former condition expresses that the semiconductor is accumulated near the source, whereas the latter says that the semiconductor is depleted near the drain. Therefore, the integral in (22) must be split in two distinct parts, and the total current has to be written as the sum of two distinct components, each being evaluated either by (24) or (26). This leads to I=

W · μ · q · ND · TSC · VDS L ⎛     FB D   W ⎜  · μ · ⎝ QSC · dV  + − QSC · dV  L   S

acc

FB

⎞ ⎟ ⎠

(29)

dep

Note that the charge density evaluated at VFB gives, by definition, QSC = 0 and does not therefore require any extra calculation. D. Comparison With Numerical Simulation

In the last subsections, we have been able to derive the current in a uniformly accumulated or depleted silicon channel. However, depending of the potentials applied to the device, a section of the channel can be in accumulation (close to the source), whereas the other can be in depletion (close to the drain). This kind of “hybrid” channel state requires special treatment. Considering that the transition must occur at the flatband voltage, we can identify three different situations (still assuming VDS > 0). Whole Channel in Accumulation: When the whole channel is in accumulation, we must satisfy the following inequality VG − VD − Δφ ≥ UT · ln(ND /ni ), also implying that VG − VS − Δφ ≥ UT · ln(ND /ni ) since VD > VS . Then, we have I=



⎞ ⎠

(27)

acc

Whole Channel in Depletion: Similarly, in depletion, we must satisfy that VG − VS − Δφ ≤ UT · ln(ND /ni ), also im-

Fig. 8 shows the current versus the gate voltage at low (VD = 0.1 V) and high (VD = 1 V) drain potentials for a 20-nm-silicon-thickness devices doped up to 1019 cm−3 . The concordance is quite good from deep depletion up to accumulation. In this case, the channel happens to be partly in depletion and partly in accumulation, depending on the value of VG . However, since the charge density was correctly predicted at the flat band, there is no discontinuity when crossing the depletion mode or the AM. Similarly, Fig. 9 confirms that we obtain good results for the 10-nm-silicon-thickness device despite the very high doping concentration of 5 × 1019 cm−3 , which is close the value reported in [2]. While, in accumulation, the agreement is very nice, we note that the model always overestimates the current in depletion, although the charge densities were shown to be quite accurate with respect to the TCAD numerical simulations. We can hardly attribute this effect to some DIBL since we are dealing with quite long channels and, above all, this seems to be insensitive to the drain potential. Neither can it be attributed to the depletion/accumulation approximations since (not shown here)

SALLESE et al.: CHARGE-BASED MODELING OF JUNCTIONLESS DG FETs

Fig. 8. Drain current versus gate voltage in linear and saturated regimes in a 20-nm-silicon-thickness junctionless DG MOSFET doped at 1 × 1019 cm−3 . (Solid lines) Model. (Dashed lines) TCAD simulations.

Fig. 9. Drain current versus gate voltage in linear and saturated regimes in a 10-nm-silicon-thickness junctionless DG MOSFET doped at 5 × 1019 cm−3 . (Solid lines) Model. (Dashed lines) TCAD simulations.

the current evaluation by means of the numerical integration of (21) with (12) and (13) gives the same results. This point will require further investigations. The current versus the drain voltage has been also investigated in Figs. 10 and 11 for 20- and 10-nm silicon thicknesses, respectively. Compared with ID versus VG characteristics, we observe some discrepancy between the model and the TCAD simulations that are not expected for the same reasons as before, i.e., charge densities were shown to be accurately predicted. Similarly, this mismatch still exists when the current is evaluated by numerical integration, which rules out any inconsistency with the approximated relationships. Small-signal characteristics have been also simulated. Fig. 12 depicts the gate transconductance gm for a 10-nm silicon thickness with different doping densities, i.e., 1019 , 3 × 1019 , and 5 × 1019 cm−3 . The drain potential was set to 1 V, allowing observing the transition from saturated to linear modes. The curves represent the gate-transconductance characteristics derived from TCAD simulations (dots), from the current obtained

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Fig. 10. Drain current versus drain voltage for various gate potentials in a 20-nm-silicon-thickness junctionless DG MOSFET doped at 1019 cm−3 . (Solid lines) Model. (Dashed lines) TCAD simulations.

Fig. 11. Drain current versus drain voltage for various gate potentials in a 10-nm-silicon-thickness junctionless DG MOSFET doped at 5 × 1019 cm−3 . (Solid lines) Model. (Dashed lines) TCAD simulations.

from (21) (dotted line), and from the current derived from (29), i.e., the hybrid model (line). Some discrepancy appears between the TCAD simulations and the bare model, i.e., without relying on the regional approximations. However, considering that these are derivatives that magnify small variations and that we did not introduce any unphysical parameter, this confirms that the coarse finite-difference approach is well sounded. Next, concerning the current calculated from the regional approximation, there is still good concordance with the TCAD simulations. Moreover, no discontinuity is observed in gm , meaning that not only the mobile charge densities converge to the same values at the flat band but also their first-order derivatives. These gate transconductances are also instructive to highlight how different the transfer characteristics between junctionless and junction-based DG MOSFETs are. The different slopes in ID –VG characteristics are clearly evidenced through the gate transconductance. This observation is peculiar to junctionless devices and cannot be simulated with a standard DG MOSFET model.

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IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011

major difference with respect to junction-based DG MOSFETs. The model presented in this paper can thus serve as a basis for further developments that should include, among other relevant phenomena, short-channel effects, channel quantization, and field-dependent mobility. R EFERENCES

Fig. 12. Gate transconductance versus gate voltage at VD = 1 V in a 10-nmsilicon-thickness junctionless DG MOSFET for different doping concentrations (1019 , 3 × 1019 , and 5 × 1019 cm−3 ). (Dots) TCAD simulations. (Solid lines) Analytical model relying on (29) combined with (24) and (26). (Dashed lines) Based on the numerical integration of (21).

Fig. 13. Drain transconductance versus drain voltage for different gate potentials in a 20-nm-silicon-thickness junctionless DG MOSFET doped at 1019 cm−3 . (Dots) TCAD simulations. (Solid lines) Analytical model relying on relation (29) combined with (24) and (26).

Concerning the output conductance gds , we found that the agreement between the “hybrid” model and the TCAD simulations was fairly good, as shown in Fig. 13. In that case, we only included simulations obtained from the regional approximation (29) since there was almost no difference with the evaluation of gds through the numerical integration of (21).

[1] C. W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, “Junction-less multigate field-effect transistor,” Appl. Phys. Lett., vol. 94, no. 5, p. 053511, Feb. 2009. [2] J. P. Colinge, C.-W. Lee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, P. Razavi, B. O’Neill, A. Blake, M. White, A.-M. Kelleher, B. McCarthy, and R. Murphy, “Nanowire transistors without junctions,” Nat. Nanotechnol., vol. 5, no. 3, pp. 225–229, Mar. 2010. [3] A. Pfitzner, M. Staniewski, and M. Strzyga, “DC characteristics of junction vertical slit field-effect transistor (JVeSFET),” in Proc. 16th Int. Conf. MIXDES, Lodz, Poland, Jun. 25–27, 2009, pp. 420–423. [4] M. Weis, A. Pfitzner, K. Kasprowicz, Y.-W. Lin, T. Fischer, R. Emling, M. Marek-Sadowska, D. Schmitt-Landsiedel, and W. Maly, “Low power SRAM cell using vertical slit field effect transistor (VeSFET),” in Proc. ESSCIRC Fringe P6, 2008. [5] E. Rauly, B. Iñiguez, and D. Flandre, “Investigation of deep submicron single and double gate SOI MOSFETs in accumulation mode for enhanced performance,” Electrochem. Solid-State Lett., vol. 4, no. 3, pp. G28–G30, Mar. 2001. [6] B. Iñíguez, B. Gentinne, V. Dessard, and D. Flandre, “A physically-based continuous model for accumulation-mode SOI pMOSFETs,” IEEE Trans. Electron Devices, vol. 46, no. 12, pp. 2295–2303, Dec. 1999. [7] J.-M. Sallese, F. Krummenacher, F. Prégaldiny, C. Lallement, A. Roy, and C. Enz, “A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalism,” Solid State Electron., vol. 49, no. 3, pp. 485–489, Mar. 2005. [8] J.-M. Sallese, N. Chevillon, F. Prégaldiny, C. Lallement, and B. Iñiguez, “The equivalent-thickness concept for doped symmetric DG MOSFETs,” IEEE Trans. Electron Devices, vol. 57, no. 11, pp. 2917–2924, Nov. 2010. [9] Y. Taur, “Analytic solutions of charge and capacitance in symmetric and asymmetric double-gate MOSFETs,” IEEE Trans. Electron Devices, vol. 48, no. 12, pp. 2861–2869, Dec. 2001.

Jean-Michel Sallese (Maître d’Enseignement et de Recherche) received the M.Sc. degree from the Institut National des Sciences Appliquées, Toulouse, France, and the Ph.D. degree in physics from the University of Nice-Sophia Antipolis, Nice, France, where he worked on deep-level characterization in semiconductors. Since 1991, he has been with the Swiss Federal Institute of Technology in Lausanne (EPFL), Lausanne, Switzerland, where he has been working on semiconductor laser diode characterization and modeling. He gives lectures on advanced semiconductor devices, and his current research activities are oriented toward compact modeling of multigate metal–oxide–semiconductor field-effect transistors (FETs) and organic FETs, as well as modeling microelectromechanical systems.

IV. C ONCLUSION We have proposed an analytical model to calculate the charge density and the current in the junctionless symmetric DG FETs. The model is valid in all regions of operation, from deep depletion to accumulation and from linear to saturated regimes, as confirmed from a detailed comparison with the TCAD numerical simulations. No empirical parameters have been used, confirming the safe physical roots of the core model. In particular, the occurrence of two distinct slopes in the charge-voltage dependence has been very well predicted, which constitutes a

Nicolas Chevillon was born in Dijon, France, in 1982. He received the M.S. degree in micro- and nanoelectronics in 2008 from the University of Strasbourg, Strasbourg, France, where he is currently working toward the Ph.D. degree in the Institut d’Electronique du Solide et des Systèmes, Centre National de la Recherche Scientifique. His current research interests include fin-shaped field-effect transistor compact modeling, 3-D simulations, and parameter extraction.

SALLESE et al.: CHARGE-BASED MODELING OF JUNCTIONLESS DG FETs

Christophe Lallement (M’96) received the M.S. degree in engineering from the Science University of Nancy I, Nancy, France, and the Ph.D. degree in engineering from the École Nationale Supérieure des Télecommunications, Paris, France. From November 1994 to September 1997, he was a Postdoctoral Research Scientist with the Laboratory of Electronics, Swiss Federal Institute of Technology, Lausanne, Switzerland, working on the characterization and the modeling of the metal–oxide–semiconductor field-effect transistor (MOS) in the development team of the Enz-Krummenacher-Vittoz (EKV) MOS transistor model. In September 1997, he was with the University of Strasbourg, Strasbourg, France, as an Associate Professor and with the Centre National de la Recherche Scientifique Laboratory for Physics and Applications of Semiconductors. Since September 2003, he has been Professor with the École Nationale Supérieure de Physique de Strasbourg, Illkirch, France. His current research works, currently with the Institut d’Électronique du Solide et des Systèmes (InESS), focus on the study and the modeling of advanced devices, mixed-signal systems with VHDL-AMS, and biosynthetic systems. He is the responsible for the group “Integrated instrumental systems” at the InESS.

Benjamin Iñíguez (M’96–SM’03) received the B.S., M.S., and Ph.D. degrees in physics from the University of the Balearic Islands, Palma, Spain, in 1989, 1992, and 1996, respectively. His doctoral research focused on the development of computer-aided design models for short-channel bulk-Si and silicon-on-insulator metal–oxide– semiconductor field-effect transistors (SOI MOSFETs). From February 1997 to September 1998, he was a Postdoctoral Research Scientist with the Department of Electrical, Computer, and Systems Engineering, Rensselaer Polytechnic Institute, Troy, NY, where he studied advanced devices, such as short-channel a-Si and poly-Si thin-film transistors (TFTs), GaN heterostructure FETs, and heterodimensional metal– semiconductor FETs. From September 1998 to February 2001, he was a Research Scientist (Postdoctoral Marie Curie Grant Holder) with the Microelectronics Laboratory, Université Catholique de Louvain, Louvain, Belgium, working on the characterization and the modeling of thin-film and ultrathinfilm SOI MOSFETs from direct-current to radio-frequency conditions. Since February 2001, he has been a Titular Professor with the Departament d’Enginyeria Electrònica, Elèctrica, i Automàtica, Universitat Rovira i Virgili, Tarragona, Spain. His current research interests are characterization and modeling of advanced electron devices, particularly nanoscale multiplegate MOSFETs and organic and polymer TFTs. Dr. Iñíguez was the recipient of the Distinction of the Catalan Government for the Promotion of University Research in 2004. In 2007, he obtained the Institution of Engineering and Technology Premium Award for a paper about charge transport in organic TFTs.

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Fabien Prégaldiny was born in France in 1977. He received the M.S. and Ph.D. degrees in microelectronics from the University of Strasbourg (UdS), Strasbourg, France, in 2001 and 2003, respectively. His doctoral research pertained to the modeling and the simulation of deep-submicrometer metal– oxide–semiconductor field-effect transistors (MOSFETs). Since 2004, he has been an Associate Professor with the École Nationale Supérieure de Physique de Strasbourg, Illkirch, France, and the UdS, where he has also been with the Institut d’Électronique du Solide et des Systèmes since 2005. His research interests focus on compact modeling and simulation of double-gate MOSFET, finshaped FET, and carbon-nanotube FET. He is also interested in the use of the VHDL-AMS hardware description language in compact modeling.

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