Vol. 35, No. 1
Journal of Semiconductors
January 2014
P-type double gate junctionless tunnel field effect transistor M. W. Akram1; , Bahniman Ghosh1; 2 , Punyasloka Bal1 , and Partha Mondal1 1 Department
of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur, Uttar Pradesh, 208016, India Research Center, 10100 Burnet Road, Bldg. 160, University of Texas at Austin, Austin, TX, 78758, USA
2 Microelectronics
Abstract: We have investigated the 20 nm p-type double gate junctionless tunnel field effect transistor (PDGJLTFET) and the impact of variation of different device parameters on the performance parameters of the P-DGJLTFET is discussed. We achieved excellent results of different performance parameters by taking the optimized device parameters of the P-DGJLTFET. Together with a high-k dielectric material (TiO2 / of 20 nm gate length, the simulation results of the P-DGJLTFET show excellent characteristics with a high ION of 0.3 mA/m, a low IOFF of 30 fA/m, a high ION =IOFF ratio of 1 1010 , a subthreshold slope (SS) point of 23 mV/decade, and an average SS of 49 mV/decade at a supply voltage of –1 V and at room temperature, which indicates that PDGJLTFET is a promising candidate for sub-22 nm technology nodes in the implementation of integrated circuits.
Key words: junctionless field effect transistor; tunnel field effect transistor; subthreshold slope DOI: 10.1088/1674-4926/35/1/014002 PACC: 7340Q; 7280C; 7340L
1. Introduction In the last few decades, dimensions of the metal oxide semiconductor field effect transistors (MOSFETs) have continually been scaled down in size such that the effective channel length is approaching less than 22 nm. The formation of ultrasharp source and drain junctions in these very small dimension devices enforces a large variation in doping concentration over a distance of a few nanometers. So careful fabrication of these junctions is necessary to achieve a low thermal budgetŒ1 . The MOSFETs will soon reach fundamental limits, because of such stringent demands of scaling. Based on Lilienfeld’s first transistor architectureŒ2 , recently, a new transistor has been proposed and successfully fabricated called the junctionless field effect transistor (JLFET)Œ3; 4 , which does not possess any metallurgical junction. Without the requirement for a metallurgical junction, the fabrication process would be very simple, have better electrical properties, and less variability than MOSFETsŒ3 9 . Although the JLFET shows better electrical properties and less variability than MOSFETs, its subthreshold slope (SS) is still limited as in MOSFETsŒ3; 4 . The most promising alternative transistor proposed to achieve lower SS (< 60 mV/decade at room temperature) is the tunnel field effect transistor (TFET)Œ10 12 ; however it also suffers from a low ON current. Although, to improve the ION and SS, a number of TFET structures have been reported in Refs. [13–15]. The ON-currents reported in these works are much lower than that of CMOS and exhibit threshold voltages higher than 0.4 V. Furthermore, for proper operation, the reported p-type TFETs usually require higher gate voltages than the power supply voltageŒ16 19 , thus making it difficult for them to be integrated in digital circuits. Very recently, we proposed a new transistor called an n-type double gate junctionless tunnel field effect transistor (N-DGJLTFET)Œ20 , which gives the combined advantages of
JLFETs and TFETs. The N-DGJLTFET with 20 nm of channel length, a high-k dielectric material as a TiO2 , and an isolation thickness of 2 nm has offered ION of 1 mA/m, a SS point of 33 mV/decade, and an average SS of 34 mV/decade at supply voltage of 1 V and at room temperature. To make the junctionless tunnel field effect transistor implementable in integrated circuits, in this work, for the first time, we have shown the performance of a 20 nm p-type double gate junctionless tunnel field effect transistor (P-DGJLTFET). The PDGJLTFET is made along the same lines as that of the n-type double gate junctionless tunnel field effect transistorŒ20 . Taking the optimized device parameters for the P-DGJLTFET, we achieve excellent results of different performance parameters. The rest of the paper is organized as follows. Section 2 presents the device structure and operation of the PDGJLTFET. The inclusion of different device models and simulation results of the P-DGJLTFET is presented in Section 3. The impact of variation of device parameters on the performance parameters of the P-DGJLTFET is discussed in the sub-section of Section 3. Finally, the paper is concluded in Section 4.
2. Device structure and its working principle The device structure of a P-DGJLTFET is shown in Fig. 1. The simulated P-DGJLTFET is a heavily p-type doped (1 1019 cm 3 / Si-channel JLFET with 20 nm gate length, 5 nm of silicon film thickness, gate oxide thickness of 2 nm, and 2 nm of isolation in between middle gate (MG) and side gate (SG) electrode, which works as an isolation between the gates and also as a spacer. To provide better controllability over the channel, double-gate technology is used. The simulated device structure is a lateral p-type JLFET, which uses two isolated gates (MG and SG) of two different metal work-functions, to make the layer beneath the gates in-
† Corresponding author. Email:
[email protected] Received 27 June 2013
© 2014 Chinese Institute of Electronics
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Fig. 1. The simulated p-type double gate junctionless tunnel field effect transistor (P-DGJLTFET). Source, drain, and channel doping concentration: 1 1019 atoms/cm3 p-type. Silicon thickness: 5 nm. Gate/intrinsic region length: 20 nm. High-k gate dielectric material with permittivity D 80 of 2 nm thickness. The width of the device is 1 m. There is 2 nm of isolation between the MG and SG electrodes. Middle gate work function (MGWF) D 5.0 eV, SG work function (SGWF) D 2.6 eV.
trinsic and n-type. We have chosen 5.0 eV and 2.6 eV for the MG and SG electrode, to make the layer beneath the MG and the SG electrode intrinsic and n-type, respectively. Here, the dielectric material TiO2 (dielectric constant value of 80) is taken as a high-k gate dielectric material. The integration of MG and SG together in the fabrication process, whose work functions are different, could be done by using the techniques as reported in Refs. [21–23]. The formation of the isolation layer with thickness of 2 nm could be done either by using a sputtering process or by a modern photolithography process (such as electron beam lithography, X-ray lithography, extreme ultraviolet lithography, and ion projection lithography) after formation of the field oxide by wet oxidation. The basic idea applied here is to convert the (PC –PC –PC / drain, channel and source of the JLFET into a (PC –I–NC / structure without any physical doping. Since this device is based on the principle of a junctionless channel, intrinsically it would be less prone to variability and short channel effects, as compared to the conventional TFET, even with the requirement of an extra gate and an isolation layer, which increases a few fabrication steps.
3. Results and discussions All the simulations are performed by using a 2D device simulator, Silvaco Atlas, version 5.16.3.R. The nonlocal bandto-band tunneling (BTBT) model available in AtlasŒ24 is used to incorporate the inter-band tunneling effect along the lateral direction, which has also been used in other works to predict the performance of TFETsŒ10 . To include the effect of temperature dependent mobility, a concentration dependent mobility model, parallel and perpendicular field dependent mobility, and the CVT (complete mobility model for concentration dependent, parallel electric field dependent, perpendicular electric field dependent, and temperature dependent) modelŒ24 are used. Due to the presence of high doping in the channel, a
Fig. 2. OFF-state (VD D –1 V, VMG D 0 V) and ON-state (VD D – 1 V, VMG D –1 V) electron and hole concentration profile of the PDGJLTFET.
band-gap narrowing (BGN) model is also included. Because of the presence of a high impurity atom in the channel and also in consideration of an interface trap (or defect) effectŒ24; 25 , the Shockley-Read-Hall (SRH) recombination model is also enabled. The interface trap effect on BTBT in TFETs is also enabled, by inclusion of the trap assisted tunneling (TAT) model given by SchenkŒ24; 25 . To include the effect of the quantum tunneling current through an oxide, the direct quantum tunneling model for electrons, holes, and the band-to-band tunneling, QTUNN, model available in SilvacoŒ24 is used. Figure 2 shows the electron and hole concentration profiles in the OFF-state and ON-state for the P-DGJLTFET. From the concentration profile it is observed that the device P-DGJLTFET looks like a PC –I–NC doped device structure in the OFF-state, and this is also observed in the case of a conventional TFET. The device is turned on by applying a gate voltage on the MG electrode, which narrows the barrier between the source and channel of the device. It is observed from the figure that on applying a gate voltage on the MG electrode, the hole concentration of the device layer beneath this gate increases and almost becomes a p-type region. This results in narrowing of the barrier between the channel and the source of the device. The OFF-state and ON-state energy band diagram of the P-DGJLTFET is shown in Fig. 3. From the OFF-state energy band diagram, we observe that the probability of tunneling of electrons is negligible, because of a large tunneling barrier in between the source and channel region. Hence, the OFF-state current flows only because of PC –I–NC diode leakage. For a TFET, it is found that ON-current (ION / increases exponentially with a decrease in tunneling barrier widthŒ10 . In the ONstate energy band diagram of P-DGJLTFET, we observe that the tunneling barrier between the source and channel of the device has lowered significantly, so there is a high probability of tunneling of electrons from the valence band of the channel to the conduction band of the source. Hence a significant amount of current flows because of the quantum tunneling mechanism. Like in a TFET, we apply gate voltage only on the MG electrode (the gate above the intrinsic region of the device) to turn on the device. The voltage of the MG electrode is varied from
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Fig. 3. Energy band diagram of the P-DGJLTFET in the OFF-state (VD D –1 V, VMG D 0 V) and ON-state (VD D –1 V, VMG D –1 V) condition.
0 to –1 V for turning the device ON. When either in OFF-state or ON-state, the SG terminal is kept at zero bias. Figure 4 shows the electric field profile in the OFF-state and the ON-state. In the OFF-state, because of the PC –I– NC structure, we find two electric field peaks at the drain-tochannel and the channel-to-source junction. However, in the ON-state, because of the application of gate voltage, the structure becomes PC –P–NC , so we find only one strong electric field peak at the junction between the channel and source region, the strong electric field peak at the junction between the channel and source region signifies that tunneling is taking place in that region because of the quantum tunneling phenomenon. At the source contact side, it is also seen that there is a high electric field peak region; this peak is because of forward biased P–N junction formation near the interface of the source region, since near the interface of the source region holes do not get completely depleted and because of this the interface near the source and source contact region is still a p-type region. On the other hand the source region except the region of the interface near the source and source contact region is an n-type region because of application of the work function difference in between the side gate metal and the channel. The P–N junction can also be seen in Fig. 2 by looking at the electron and hole concentration profiles near the interface between the source and source contact region. Here, the P–N junction formation is advantageous, since the junction is in the forward biased condition and forward current flows. Since the forward current is in the same direction as that of the tunneling current, the currents add up and the value of current increases because of two current flow mechanisms. The leakage current (OFF-current) effect of TiO2 gate oxide with or without the direct quantum tunneling model is shown in Fig. 5. From the figure we observe that the inclusion of the direct quantum tunneling model (QTUNN) does not affect the OFF-current much more, since an increase in leakage current due to the inclusion of the trap assisted tunneling (TAT) model is much higher than the inclusion of the direct quantum tunneling model (QTUNN) alone. The ON-current (ION / and OFF-current (IOFF / are measured at the supply voltages of (VD
Fig. 4. Electric field profile of the P-DGJLTFET in the OFF-state (VD D –1 V, VMG D 0 V) and ON-state (VD D –1 V, VMG D –1 V) condition.
Fig. 5. Drain current (ID / versus middle gate voltage (VMG / of the P-DGJLTFET with or without the direct quantum tunneling model. Drain voltage (VD / D –1 V.
D –1 V, VMG D –1 V) and (VD D –1 V, VMG D 0 V), respectively. In the subsequent simulation results, the direct quantum tunneling model (QTUNN) is not included, since OFF-current does not change considerably as compared with the inclusion of the trap assisted tunneling (TAT) model alone. Figure 6 shows the input characteristics (ID versus VMG characteristics) of the P-DGJLTFET using a high-k dielectric material of TiO2 (dielectric constant D 80) for different drain voltage (VD / values from –50 mV to –2 V. As the drain voltage increases from –50 mV to –1 V, the tunneling current also increases, since in TFET tunneling current not only depends upon the gate voltage but also on the drain voltage. A further increase in drain voltage does not provide much improvement in the ION , since the effectiveness of the short channel effect (such as velocity saturation and pinch-off mechanism) comes into play. The continuous increase in VD also increases the OFF-current by reasonable amount due to the DIBL effect. Figure 7 shows the output characteristics (ID versus VD characteristics) of the P-DGJLTFET when using a high-k dielectric material of TiO2 (dielectric constant D 80) for differ-
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Fig. 6. Drain current (ID / versus middle gate voltage (VMG / of the P-DGJLTFET using a high-k dielectric material of TiO2 (dielectric constant = 80) for different drain voltage (VD / values from 50 mV to 2 V.
Fig. 8. ID versus VMG of the P-DGJLTFET for different dielectric constant values ("r /, 25, 30, and 80 at VD D 1 V.
3.1. Effect of high-k dielectric gate material on different performance parameters
Fig. 7. ID versus VD of the P-DGJLTFET using a high-k dielectric material of TiO2 (dielectric constant D 80) for different VMG values from 500 mV to 2 V.
ent MG voltage (VMG / values from 500 mV to 2 V. From the figure we observe that when 500 mV is applied at the VMG terminal, the ON-current is much less as compared to when a voltage of 2 V is applied, since the tunneling barrier in the case of 500 mV at the VMG terminal is still high enough and hence the probability of tunneling of charge carriers would be very less. On applying gate voltage on the MG from 500 mV to 2 V, continuous improvements in ION are observed, this is because of a continuous reduction in the tunneling barrier width, which in turn increases the probability of tunneling of more and more charge carriers and hence a continuous increase in ON-current is observed with the gate voltage sweeping from 500 mV to 2 V. The SS point is measured as the inverse of the maximum slope of the log of the drain current versus gate voltageŒ2; 10 . The average SS is measured as used in Ref. [10]. The next sub-section discusses the effect of variation of different device parameters on performance parameters (such as SS, threshold voltage (VTH /, and ION /IOFF ratio) of the PDGJLTFET.
The subthreshold characteristic (ID versus VMG characteristics) of the P-DGJLTFET with high-k dielectric materials is shown in Fig. 8. Here, we have considered different dielectric materials (such as TiO2 ("r D 80), La2 O3 ("r D 30), and HfO2 ("r D 25)) for the optimization of different performance parameters of the P-DGJLTFET, the dielectric constant of different materials are taken from Ref. [26]. Figure 9 shows the effect of dielectric constant value on the different performance parameters (such as SS, threshold voltage (VTH /, and ION /IOFF ratio) of the P-DGJLTFET. From the figure, it can be seen that with the higher value of dielectric constant, higher ON-current, improved SS, and higher ION /IOFF ratio are observed, which is because of the higher gate coupling offered by a high-k dielectric gate material with a higher dielectric constant value ranging from 25 to 80, keeping the physical thickness of gate oxide fixed and equal to 2 nm. As the dielectric constant value increases from 25 to 80, a reduction in threshold voltage is observed. Using a high-k dielectric material such as TiO2 , the ON-current of 0.3 mA/m and OFF-current of 3 10 14 A/m are achieved. 3.2. Effect of work function engineering on different performance parameters In order to achieve the maximum ON-current, low OFFcurrent, and also low SS, the p-type doping levels of 1 1019 atoms/cm3 are taken for the drain, intrinsic, and source regions, and the metal work function of the MG and the SG electrodes was varied from 4.4 to 5.0 eV and 2.6 to 3.5 eV, respectively. Figure 10 shows the ID versus VMG characteristics of the different metal work function from 4.4 to 5.0 eV for the MG electrode. From the figure, we observe that the work function of 5.0 eV for the MG electrode gives the best result in terms of ION , point SS and ION /IOFF ratio. The effect of middle gate work function (MGWF) on the SS point, threshold voltage (VTH /, and ION /IOFF ratio for the P-DGJLTFET is shown in Fig. 11. From the figure, it is observed that the SS point is almost insensitive to the variation in the middle gate work func-
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Fig. 9. Subthreshold slope (SS) point, threshold voltage (VTH /, and ION /IOFF ratio of the P-DGJLTFET for different dielectric constant values ("r /, 25, 30, and 80 at VD D 1 V.
Fig. 10. ID versus VMG of the P-DGJLTFET for different middle gate work functions (MGWFs) at VD D 1 V.
tion (MGWF). However, threshold voltage (VTH /, and ION /IOFF ratio are much more sensitive to the variation in the middle gate work function (MGWF), the increase in MGWF reduces the VTH , and ION /IOFF ratio increases with increase of MGWF. A further increase in the MGWF value would result in a drastic increase in the OFF-current. The subthreshold characteristics curve of the different metal work function from 2.6 to 3.5 eV for the SG electrode is shown in Fig. 12. From the figure, we observe that the work function of 2.6 eV for the SG electrode gives the best result in terms of ION , point SS and ION /IOFF ratio, and also the equitable IOFF . Figure 13 shows the effect of side gate work function (SGWF) on the SS point, threshold voltage (VTH /, and ION /IOFF ratio for the P-DGJLTFET. From the figure, it is observed that the SS point is not very sensitive to the variation in the SGWF. However, VTH and ION /IOFF ratio are much more sensitive to the variation in the SGWF; the increase in SGWF reduces the VTH , and ION /IOFF ratio decreases with an increase of SGWF. A further decrease in the SGWF value increases the ON-current, however, a metal work function lower than 2.6 eV is not feasible from a fabrication point of view. A low work function metal is lithium (work function, 2.3 eV), but it has a
Fig. 11. Subthreshold slope (SS) point, threshold voltage (VTH /, and ION /IOFF ratio of the P-DGJLTFET for different middle gate work functions (MGWFs) at VD D 1 V.
Fig. 12. ID versus VMG of the P-DGJLTFET for different side gate work functions (SGWFs) at VD D 1 V.
Fig. 13. Subthreshold slope (SS) point, threshold voltage (VTH /, and ION /IOFF ratio of the P-DGJLTFET for different side gate work functions (SGWFs) at VD D 1 V.
low melting point of 180 ıC, which is not acceptable in the high temperature processing of the semiconductor devices.
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4. Conclusion
Fig. 14. ID versus VMG of the P-DGJLTFET for different channel doping concentrations (NA / at VD D 1 V.
Fig. 15. Subthreshold slope (SS) point, threshold voltage (VTH /, and ION /IOFF ratio of the P-DGJLTFET for different channel doping concentrations (NA / at VD D 1 V.
3.3. Effect of doping concentration variation on different performance parameters The ID versus VMG characteristics for different channel doping concentrations (NA / is shown in Fig. 14. From the figure, we observe that with the increase in doping concentration from 5 1018 to 5 1019 cm 3 , ION does not improve much, however at the same time IOFF degrades significantly. Figure 15 shows the impact of variation of channel doping concentration on the SS point, threshold voltage (VTH /, and ION /IOFF ratio for the P-DGJLTFET. From the figure, we observe that as the concentration decreases, improvements in the SS point and ION /IOFF ratio are observed. However, the reduced value of doping concentration (5 1018 cm 3 /, also degrades the ION as we observe from Fig. 13, so to achieve reasonable amount of ION , point SS, and ION /IOFF ratio, we have chosen 1 1019 cm 3 as an optimized doping concentration in the proposed simulated device structure. The simulation results for the optimized device structure for a P-DGJLTFET show excellent characteristics with a high ION of 0.3 mA/m, a low IOFF of 30 fA/m, a high ION =IOFF ratio of 1 1010 , a SS point of 23 mV/decade, and an average SS of 49 mV/decade at supply voltage of –1 V and at room temperature, which indicates that P-DGJLTFET
In this work, we investigated the performance of a newly proposed device, called a p-type double gate junctionless tunnel field effect transistor (P-DGJLTFET). We achieved excellent results for different performance parameters with the use of optimized device structure parameters, identified by the simulation studies of the impact of variations of different device parameters on the performance parameters of the P-DGJLTFET. Simulation results show that the P-DGJLTFET would be a strong candidate to complement or replace MOSFET technology as it delivers high ION , low IOFF , high ION /IOFF ratio, and a low subthreshold slope. It seems to be a prospective device for sub-22 nm technology nodes.
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