IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—II: ANALOG AND DIGITAL SIGNAL PROCESSING, VOL. 50, NO. 8, AUGUST 2003
[14] A. Avizienis, “A Study of Redundant Number Representation for Parallel Digital Computers,” Ph.D dissertation, Univ. of Illinois Press, Urbana, May 1960. [15] L. S. Reed, “VLSI implementation of GSC architecture with a new ripple carry adder,” in Proc. ’88 Int. Conf. Computer Design (ICCD), 1988, pp. 520–523. [16] S. J. Piestrak, “Design of high-speed residue-to-binary number system converter based on the Chinese Remainder Theorem,” in Proc. ’94 Int. Conf. Computer Design (ICCD), Cambridge, MA, Oct. 1994, pp. 508–511. [17] S. Andraos and H. Ahmed, “A new efficient memoryless residue to binary converter,” IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1441–1444, Nov. 1988. [18] K. M. Ibrahim and S. N. Saloum, “An efficient residue to binary converter design,” IEEE Trans. Circuits Syst., vol. CAS-35, pp. 1156–1158, Sept. 1988. [19] R. Conway and J. Nelson, “Fast converter for 3 moduli RNS using new property of CRT,” IEEE Trans. Comput., vol. 48, pp. 852–860, Aug. 1999. [20] W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, “A high-speed 2 1) residue-to-binary converter for three-moduli (2 2 RNS and a scheme for its VLSI implementation,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 1576–1581, Dec. 2000. [21] A. A. Hiasat and H. S. Abdel-Aty-Zohdy, “Residue-to-binary arithmetic 1 2 1),” IEEE Trans. converter for the moduli set (2 2 Circuits Syst. II, vol. 45, pp. 204–209, Feb. 1998. [22] A. B. Premkumar, “An RNS to binary converter in a three moduli set with common factors,” IEEE Trans. Circuits Syst. II, vol. 42, pp. 298–301, Apr. 1995. [23] M. Bhardwaj, T. Srikanthan, and C. T. Clarke, “A reverse converter for the 4-moduli superset 2 2 2 2 + 1 ,” in Proc. 14th IEEE Computer Arithmetic Symp., Adelaide, Australia, Apr. 14–16, 1999. [24] F. Pourbigharaz and H. M. Yassine, “A signed-digit architecture for residue to binary transformation,” IEEE Trans. Comput., vol. 46, pp. 1146–1150, Oct. 1997.
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Comments on “2-D FIR Filters Design Using Least Square Error With Scaling-Free McClellan Transformation” Sunder S. Kidambi
Index Terms—Least-squares, McClellan transformation, two-dimensional (2–D) finite-impulse response (FIR).
The idea of formulating the least-squares error along the desired contour in a quadratic form in the design of two-dimensional (2-D) zero-phase nonrecursive filters has been presented earlier in [1]. Explicit formulas for the design of 2-D fan filters with prescribed inclination have also been presented. As claimed in [2], it has been shown in [1] that the error depends upon the value of the cut-off frequency of the prototype one-dimensional (1-D) filter and is lowest for a particular value of the 1-D filter cutoff frequency. In fact, the values of t(1; 1) and t(0; 1) presented in [2] is, for all practical purposes, the same as those presented in [1, Table 1]. This method has also been extended to the design of circularly-symmetric filters in [1], which the authors of [2] have done as well. The application of the least-squares method in the design of elliptic filters is fairly straightforward, as has been indicated in the conclusion of [1]. REFERENCES [1] S. S. Kidambi, “Design of two-dimensional nonrecursive filters based on frequency transformations,” IEEE Trans. Signal Processing, vol. 43, pp. 3025–3029, Dec. 1995. [2] H.-C. Lu and K.-H. Yeh, “2-D FIR filters design using least square error with scaling-free McClellan transformation,” IEEE Trans. Circuits Syst. II, vol. 47, pp. 1104–1107, Oct. 2000. Manuscript received January 3, 2000; revised April 11, 2003. This paper was recommended by Associate Editor D. Mandic. The author is with the Analog Devices Inc., Ray Stata Technology Center, Wilmington, MA 01887 USA (e-mail:
[email protected]). Digital Object Identifier 10.1109/TCSII.2003.814810
1057-7130/03$17.00 © 2003 IEEE
