IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
1907
Design and Modeling of Line-Tunneling Field-Effect Transistors Using Low-Bandgap Semiconductors Chun-Hsing Shih and Nguyen Dang Chien
Abstract— The low-bandgap engineering and line-tunneling architecture are the two major techniques to resolve the ON -current issues of tunnel field-effect transistors (TFETs). This paper elucidates the design and modeling of line-tunneling TFETs using low-bandgap materials. Three semiconductors, Ge, InAs, and InSb, are considered as examples to explore their physical operations and analytical models. 2-D device simulations were performed to examine the ON/ OFF characteristics. The appropriate operational voltages depend on the associated bandgap of semiconductors. The gate voltage should be larger than the bandgap voltage (E g /q) to ensure high ON-currents, whereas the drain voltage must be less than the bandgap voltage to control OFF -leakages. Because the minimum tunnel path has a key function in determining the tunneling in line-tunneling TFETs, the tunneling current is reformulated in terms of the minimum tunnel path with friendly compact forms. Two prime design factors, the source concentration and gate-insulator thickness, are examined both analytically and numerically, showing the minimum tunnel path can serve as a useful indicator for low-bandgap line-tunneling TFETs. Index Terms— Line-tunneling, low-bandgap semiconductors, tunnel field-effect transistors (TFETs).
I. I NTRODUCTION
T
UNNEL field-effect transistor (TFET) has demonstrated the potentiality to serve as an attracting candidate for energy-efficient applications [1]–[3]. A small subthreshold swing with a high ON-current and low OFF-current is the key requirement for the TFET devices. Barrier engineering has been used to enhance the TFET performance [4]–[7]. However, the silicon-based TFETs suffer from a low ON-current because of relatively high bandgap [5]. Increasing the ON-current of TFETs has become a considerable challenge. Because TFET conduction is governed by the band-to-band tunneling (BTBT), TFET performance depends on the associated bandgap [1]. Therefore, the low-bandgap engineering is one of the most effective techniques to promote the ON-current [4], [6], [7]. Alternatively, previous studies proposed the line-tunneling approach as an applausive architecture to increase the ON -current [8], [9]. The BTBT generation of line-tunneling TFETs is produced vertically in the gate-overlapped source,
Manuscript received November 17, 2013; revised March 11, 2014 and March 26, 2014; accepted March 26, 2014. Date of publication May 6, 2014; date of current version May 16, 2014. This work was supported by the Ministry of Science and Technology of Taiwan. The review of this paper was arranged by Editor M. J. Kumar. The authors are with the Department of Electrical Engineering, National Chi Nan University, Nantou 54561, Taiwan (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2014.2316217
whereas the current is conducted laterally along the gatecontrolled surface channel. Because the BTBT generation occurs at the heavy source, the ON-state tunnel path is reduced to produce a considerable tunneling current. Without the limitation of point-tunneling, the line-tunneling area can be extended by the gate-source overlap length to increase the ON -current. The combination of the line-tunneling structure with low-bandgap materials further provides an impressive approach to maximize the ON-currents. Based on the Kane’s models derived in a uniform field [10], analytical models were developed for Si-based line-tunneling TFETs [8], [11]. However, if in a nonuniform field, an alternative nonlocal field is required to estimate the tunneling generation [12], [13]. Because the formulations are focused on Si-based TFETs and expressed either in sophisticated forms [11] or near the onset of tunneling [8], it is challenging to apply them in practical design of low-bandgap line-tunneling TFETs. In this paper, the physical operations and device modeling of low-bandgap line-tunneling TFETs are studied in depth. 2-D device simulations [14] were performed to examine the ON / OFF characteristics. The effects of low-bandgap materials on the line-tunneling are elucidated. Based on the physical mechanisms of low-bandgap line-tunneling, we reformulate the tunneling current models into friendly forms. Using the minimum tunnel path, the key design factors are discussed both analytically and numerically to provide a sound understanding of the tunneling currents in low-bandgap line-tunneling TFETs. Section II describes the structures and parameters used in simulations and discusses the applications of low-bandgap materials in line-tunneling TFETs. Section III details the formulations of analytical models and their approximations. Results of analytical models were confirmed with experimental and simulated data. Section IV investigates the two prime device factors, the gate-insulator thickness and source concentration, in terms of the minimum tunnel path. II. L OW-BANDGAP L INE -T UNNELING TFETs A. Structures and Parameters Fig. 1 shows the schematic sketches of line-tunneling and point-tunneling, TFETs used in investigation. Direct bandgap of 0.17-eV InSb and 0.37-eV InAs were typified as lowbandgap semiconductors, whereas direct bandgap of 0.8-eV Ge [15] was employed as a relatively high-bandgap material for comparisons. This paper employed a channel length of 50-nm bulk TFET with a gate workfunction of 4.05 eV and
0018-9383 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1908
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
Fig. 1. Schematic structures of (a) line-tunneling and (b) point-tunneling, TFETs. Arrows indicated the directions of lateral and vertical tunneling.
a gate-source overlap length of 100 nm. A heavily doped n+ drain of 1019 cm−3 was utilized with an n-type channel body of 1016 cm−3 . A 2-nm HfO2 gate-insulator and a p+ doped source of 5 × 1018 cm−3 were utilized with a gate-channel overlap length (L gc ) of 50 nm, unless otherwise specified. To investigate the TFET characteristics, device simulations were performed with the direct BTBT Kane’s models using the nonlocal approach [10], [14]. To avoid the ambiguity of defining the bandgap in the analysis, the heavy-doping bandgap narrowing was neglected. To reduce the mathematical formulations and numerical simulations into manageable levels, the semiclassical approach was employed in studying the low-bandgap line-tunneling TFETs. Because the designed source concentration was ranging from 1018 to 1019 cm−3 , the variations in the tunneling currents caused by the heavy-doping and quantum confinement will be relatively limited [16]. Because the trap charges and associated trap-assisted tunneling are process sensitive, arbitrary assumption is beyond the scope of this simulation-based study. Previous researchers have showed that the trap-assisted tunneling becomes less important when the bandgap is decreased [17]–[20]. Therefore, defectfree TFETs were employed in subsequent investigation. B. Operations and Mechanisms Fig. 2 presents the simulated contours of ON-state BTBT generation in point- and line-tunneling InAs TFETs. The point-tunneling occurs laterally at the source–channel interface, whereas the line-tunneling generates vertically in the gate-overlapped source. Fig. 3 shows the drain currents of point- and line-tunneling TFETs using Ge, InAs, and InSb. Both the gate-to-source voltage (Vgs ) and the drain-to-source voltage (Vds ) are specified in term of the energy bandgap (E g ) to reflect the use of various bandgap materials. Normally, the line-tunneling TFET generates a higher ON-current and smaller subthreshold swing than the point-tunneling counterpart. The benefits of the line-tunneling TFETs are mainly attributed to the vertical BTBT generation occurred at the heavily doped gate-overlapped source. The ON-state tunnel path is reduced to produce significant BTBT generation.
Fig. 2.
Simulated contours of ON-state BTBT generation in InAs TFETs.
In the line-tunneling TFETs, the OFF-state lateral tunneling initiates at a relatively small Vgs before the vertical tunneling does because of the p+ /n source/channel junction. The lateral tunneling becomes mitigated at a larger Vgs due to an increased gate-coupled field. Therefore, at the beginning of the subthreshold conditions, the drain current of line-tunneling TFETs is triggered by the lateral tunneling. After the Vgs approaching the threshold voltage, the vertical tunneling dominates to contribute the drain current with a small swing. As the Vgs goes beyond the threshold voltage, the ON-state line-tunneling current depends on the overlapped L gc . The fully overlapped TFETs exhibit the largest ON-currents, while the nonoverlapped devices produce the smallest ones. Fig. 3(d) displays the ON-state band diagrams of fully overlapped and nonoverlapped InAs TFETs. The nonoverlapped TFET suffers from the presence of additional channel potential barriers [21]. The variations of ON-currents for the three types of linetunneling TFETs in Fig. 3 are caused by the additional potential barriers. A suitably gate-coupled field is required to suppress the potential barrier, ensuring a favorable ON-current. Nevertheless, the lateral tunneling might be considerably triggered to degrade the subthreshold swing. In subsequent investigation, we employed the fully overlapped TFETs to maximize the ON-state currents. The current–voltage curves of line-tunneling TFETs depend strongly on the Vds as well as the Vgs . Fig. 4 plots the simulated drain currents of line-tunneling TFETs with various Vds . Both the Vgs and Vds are specified in term of the E g . The ON -currents are mildly enhanced with increasing Vds , whereas the OFF-leakages are significantly increased correspondingly. For a small Vds , such as 0.5 E g /q, the OFF-current is reduced to the Shockley–Read–Hall (SRH) generation–recombination. The SRH and ambipolar currents are relatively pronounced in the InSb TFETs because of the ultralow bandgap. The OFF-current becomes considerable when the Vds is comparable with the bandgap voltage (E g /q). As the Vds is
SHIH AND CHIEN: DESIGN AND MODELING OF LINE-TUNNELING FIELD-EFFECT TRANSISTORS
Fig. 3. Drain currents of point- and line-tunneling TFETs using (a) Ge, (b) InAs, and (c) InSb. (d) ON-state energy-band diagrams of line-tunneling InAs TFETs with fully (L gc = 50 nm) and nonoverlapped (L gc = 0 nm) regions.
1909
Fig. 4. Current-voltage curves of (a) Ge, (b) InAs, and (c) InSb, TFETs at various Vds voltages. (d) OFF-state band diagrams of InAs TFETs with two Vds .
higher than the E g /q, the tunnel barrier at the drain junction is sufficiently thin to cause a substantial OFF-current. Fig. 4(d) shows the effects of the Vds on the OFF-state barriers in InAs TFETs. Because the ON-currents are mildly increased with the raised Vds , the applied Vds must be no larger than the bandgap voltage to avoid problematic OFF-leakages in low-bandgap line-tunneling TFETs.
III. A NALYTICAL M ODELS OF L OW-BANDGAP TFETs A. Generation Rate and Tunneling Current Fig. 5 shows the structures and parameters used in derivations. This paper assumed that no significant inversion charges exist at the source surface, and the source potential is identical along the lateral direction. Based on the direct BTBT Kane’s models, the generation rate G tun (x) applicable to low- and high-bandgap materials is
Fig. 5.
Schematic structures and parameters used in analytical derivations.
expressed as [22] G tun (x) = A
ξ(x) · ξ¯ (x) 1/2
Eg
3/2
Eg · exp − B ξ¯ (x)
(1)
1910
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
where ξ(x) is the local electric field at tunneling position x and ξ¯ (x) is the nonlocal electric field which is the average of local electric field over tunnel path. A decoupled local electric field is specified in the preexponential factor, which involved in the tunneling-electron numbers [12], [22], [23]. √ √ A = q 2 m r 18π h¯ 2 and B = π m r 2h¯ q; m r is the reduced mass; q is the electron charge; h¯ is the reduced Plank’s constant. The associated tunneling current Itun is given by x max
Itun = q
A x min
ξ(x) · ξ¯ (x) 1/2
Eg
3/2 Eg · exp − B dx ξ¯ (x)
(2)
where x min and x max are the minimum and maximum locations to tunneling, respectively. Equations (1) and (2) can be expressed in term of the tunnel path (ltun ) [11], respectively, as 1/2 ANa E g l4 1/2 · 1 − max G(ltun ) = · exp − Bq E g ltun (3) 4 4ε ltun lmax 1/2 ANa E g l4 Itun = q · 1 − max 4 4ε ltun lmin
1/2 · exp − Bq E g ltun dltun
(4)
where ε is the dielectric permittivity of materials and Na is the source concentration. The maximum tunnel path lmax is given as
lmax =
2ε E g q 2 Na
and the minimum tunnel path lmin is written as
qψs qψs − −1 lmin = lmax · Eg Eg
(5)
(6)
where ψ S is the surface potential at the semiconductor– insulator interface. B. Surface Potential and TFET Currents
Fig. 6. (a) Calculated results of surface potentials. (b) Analytical, simulated, and experimental currents of InAs and In0.53 Ga0.47 As tunnel diodes.
on the key device parameters. Alternatively, for a sufficiently small γ , the surface potential is approximately as
ψ S = Vgs − Vfb − γ Vgs − Vfb . (9) As shown in Fig. 2, the BTBT generation along the minimized tunnel path contributes to most of tunneling currents. The ratio lmax /ltun is considerably larger than 1. Therefore, the tunneling current in (4) can be approximated in TFETs as lmax 1/2 4 q ANa E g lmax 1 1/2 ∼ Itun = · · exp − Bq E g ltun dltun . 4 4ε lmin l tun (10) For low-bandgap TFETs, the exponential term in (10) varies slowly than the preexponential factor because of small E g . The TFET current can be simply expressed as 1/2 4 lmax q ANa E g lmax 1 1/2 · 3 · exp − Bq E g ltun . (11) Itun ∼ = lmin 4ε 3ltun
In (5) and (6), the lmax depends on the Na as well the E g , whereas the lmin is related to the surface potential that is associated with the Vgs . In the line-tunneling TFETs, the gate-voltage equation is given by
(7) Vgs = Vfb + ψ S − γ ψ S
By retaining the dominant term of the minimum tunnel path in (11), the low-bandgap TFET current is approximately given by
voltage. γ is the body-effect coeffiwhere Vfb is the flat-band √ cient, where γ = 2εq Na /C g and C g is the gate capacitance. The surface potential can be solved to be written as [11]
ψ S = − (ε/εox )tox q Na /2ε
For high-bandgap TFETs the exponential term in (4) changes quickly than the preexponential factor [8]. The high-bandgap TFET current is written simply as lmax 4 ANa 1/2 ∼ · I = (13) · exp − Bq E g lmin . 4Bε lmin
+
2 [(ε/εox )tox ]2 q Na 2ε + (Vgs − Vfb )
(8)
where tox is the physical oxide thickness and εox is the dielectric permittivity of oxide. Because (8) is rather complicated, it is difficult to disclose the dependence of the surface potential
1/2
Aq Na E g I ∼ = 12ε
·
4 lmax 1/2 · exp − Bq E g lmin . 3 lmin
(12)
C. Results and Discussion Fig. 6(a) shows the calculated results of surface potentials using (8) and (9) in low- and high-bandgap materials. The compact form exhibits great agreements with the
SHIH AND CHIEN: DESIGN AND MODELING OF LINE-TUNNELING FIELD-EFFECT TRANSISTORS
1911
Fig. 7. (a) Analytical and simulated minimum tunnel paths as function of gate voltage in low-bandgap line-tunneling TFETs. (b) Analytical and simulated drain currents of low- and high-bandgap line-tunneling TFETs.
sophisticated. To confirm the validity of the derived BTBT models, analytical calculations and numerical simulations were performed to compare with the experimental low-bandgap InAs (E g = 0.37 eV) and high-bandgap In0.53 Ga0.47 As (E g = 0.76 eV) tunnel diodes [24]. The InAs diode employed a 60-nm n-layer of 3 × 1018 cm−3 , a 3-nm intrinsic layer, and a 300-nm p-layer of 1.8 × 1019 cm−3 . The In0.53 Ga0.47 As diode employed a 60-nm n-layer of 1.6 × 1019 cm−3 , a 3-nm intrinsic layer, and a 300-nm p-layer of 5.7 × 1018 cm−3 . Fig. 6(b) shows the results of the InAs and In0.53Ga0.47 As tunnel diodes. Without fitting factors, good agreements of tunneling currents are confirmed between the calculated and measured data. The variations of BTBT currents at the higher voltages are mainly attributed to the series resistance effect [25]. The overestimation is more pronounced in the low-bandgap InAs because of a larger current level. The minimum tunnel path has a key function in determining the tunneling current. Proper determination of the minimum tunnel path is important in calculating the line-tunneling current. Fig. 7(a) displays the analytical and simulated minimum tunnel paths of line-tunneling TFETs. The modeling results exhibit great agreements with the numerically extracted data. The minimum tunnel paths depend strongly on the E g and Vgs . They are decreased with increasing the Vgs because of an increased surface potential. The low-bandgap materials can effectively suppress the minimum tunnel path, whereas a sufficient Vgs , roughly the bandgap voltage, is required to ensure such a minimized path. Fig. 7(b) shows the analytical and simulated drain currents of line-tunneling TFETs. The modeling curves show good agreements with the simulated ones to provide a sound estimation of line-tunneling currents. The slight deviations between the calculations and simulations are caused in part by mathematical approximations and physical assumptions. When the Vgs is larger than the sum of the threshold voltage and Vds , the variations are coming from the surface potential
Fig. 8. Current–voltage curves of (a) Ge, (b) InAs, and (c) InSb, linetunneling TFETs with various source concentrations. (d) Calculated ON-state minimum tunnel paths against source concentration in Ge, InAs, and InSb TFETs.
pinning [26], which was not considered here. As shown in Fig. 7, the reduced minimum tunnel paths by low-bandgap materials play a key role in generating the high ON-current and small subthreshold swing in line-tunneling TFETs. Because the depletion area is decreased accordingly with the reduced minimum tunnel path, the ON-current enhancement is relatively limited in ultralow-bandgap semiconductors. IV. D ESIGN OF L OW-BANDGAP TFETs To capture the physical insights of low-bandgap linetunneling TFETs, two prime design factors are examined in terms of the minimum tunnel path subsequently. A. Source Concentration Fig. 8(a)–(c) shows the dependence of tunneling currents on the source concentration in line-tunneling TFETs. With increasing the source concentration, the OFF-current
1912
is substantially reduced because of the decreased minority carriers that contribute to the OFF-state drift leakage, and the ON-current is enhanced due to a smaller tunnel path. Therefore, a sufficiently high source concentration is indispensable for the low-bandgap TFETs to ensure the favorable ON -/ OFF -currents. The dependence is relatively pronounced in high-bandgap Ge because the associated minimum tunnel path varies more abruptly. Compared with the point-tunneling Ge TFETs in [4], the source concentration plays a more important role in the line-tunneling TFETs. In subthreshold conditions, the subthreshold swing decreases with increasing the source concentration; however, because of appreciable lateral tunneling, the subthreshold swing degrades at relatively high source concentrations. The amount of lateral and vertical tunneling depends on the source concentration. At the source concentrations of 1–5 × 1018 cm−3 , vertical tunneling dominates the total tunneling current at subthreshold conditions. However, using a heavy source of 1019 cm−3 generates considerable lateral tunneling, thereby degrading the subthreshold swing of the line-tunneling TFETs. Therefore, the tradeoffs inherent to the subthreshold swing and ON-/ OFF-currents necessitate optimizing the source concentration in low-bandgap TFETs [27]. The ON-current enhancement using the heavy source becomes saturated when the source concentration is sufficiently high; thus a source concentration of 5 × 1018 cm−3 was employed to yield favorable switching characteristics. Fig. 8(d) shows the calculated ON-state minimum tunnel paths against the source concentration for line-tunneling TFETs. The minimum tunnel paths are decreased rapidly with raising the source concentration from 1018 cm−3 because of the increased electric field. However, the reduction of minimum tunnel paths is gradually saturated with the increased source concentration. The dependence of the minimum tunnel path on the source concentration results in the observed ON -current characteristics of line-tunneling TFETs. In the subthreshold conditions, the minimum tunnel path is rather comparable with the maximum one, the dependence becomes relatively weak. B. Gate-Insulator Thickness Fig. 9(a)–(c) shows the TFET currents against the equivalent oxide thickness (EOT) of gate-insulators. These plots employed 2-nm gate-insulators with varying dielectric constant to retain the identical fringing field effect [21]. The OFF -current is independent of the EOT because it is governed by the minority drift current. However, a thin EOT is required to ensure a favorable ON-current and subthreshold swing. The stronger gate-controlled field by a thinner EOT can initiate the vertical tunneling at a smaller Vgs and suppress the unwanted lateral tunneling more effectively, producing a more abrupt switching and higher tunneling current. Because the EOT values play a more important role in determining the low-bandgap tunneling currents, a thin EOT is essential for low-bandgap line-tunneling TFETs [27]. Fig. 9(d) plots the calculated ON-state minimum tunnel paths as a function of EOT values. In this plot, the maximum
IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 61, NO. 6, JUNE 2014
Fig. 9. Current–voltage curves of (a) Ge, (b) InAs, and (c) InSb TFETs with various EOT values. (d) Calculated ON-state minimum tunnel paths against EOT values in Ge, InAs, and InSb TFETs.
EOT is limited to less than 0.6 nm to satisfy the approximation using (9). The minimum tunnel path is linearly increased with raising the EOT. Different to the source concentration, the variations of the minimum tunnel paths are similar in different semiconductors, and the reduction of the EOT has a relatively weak function in minimizing the minimum tunnel path. As plotted in Fig. 9, a mild increase of the ON-current is produced in line-tunneling TFETs using the thinner EOT. In summary, the results discussed in this section show that the minimum tunnel paths serve as a good indicator to predict the tunneling current of low-bandgap line-tunneling TFETs. V. C ONCLUSION The design and modeling of low-bandgap line-tunneling TFETs has been elucidated. Applicable in low-bandgap TFETs, friendly forms of line-tunneling currents have been formulated in terms of the minimum tunnel path. The prime design factors have been examined both analytically and
SHIH AND CHIEN: DESIGN AND MODELING OF LINE-TUNNELING FIELD-EFFECT TRANSISTORS
numerically, showing the minimum tunnel path serves as a good indicator to predict the ON-current performance of low-bandgap line-tunneling TFETs. ACKNOWLEDGMENT The authors thank the National Center for Highperformance Computing for computer time and facilities. R EFERENCES [1] A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energyefficient electronic switches,” Nature, vol. 479, pp. 329–337, Nov. 2011. [2] D. E. Nikonov and I. A. Young, “Overview of beyond-CMOS devices and a uniform methodology for their benchmarking,” Proc. IEEE, vol. 101, no. 12, pp. 2498–2533, Dec. 2013. [3] S. Mookerjea et al., “Experimental demonstration of 100 nm channel length In0.53 Ga0.47 As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications,” in IEEE IEDM Tech. Dig., 2009, pp. 949–951. [4] E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, “Device physics and design of germanium tunneling field-effect transistor with source and drain engineering for low power and high performance applications,” J. Appl. Phys., vol. 103, no. 10, pp. 104504-1–104504-5, May 2008. [5] S. J. Koester et al., “Are Si-SiGe tunneling field-effect transistors a good idea?” ECS Trans., vol. 33, no. 6, pp. 357–361, 2010. [6] C.-H. Shih and N. D. Chien, “Sub-10-nm tunnel field-effect transistor with graded Si/Ge heterojunction,” IEEE Electron Device Lett., vol. 32, no. 11, pp. 1498–1500, Nov. 2011. [7] O. M. Nayfeh, J. L. Hoyt, and D. A. Antoniadis, “Strained-Si1−x Gex /Si band-to-band tunneling transistors: Impact of tunnel junction germanium composition and doping concentration on switching behavior,” IEEE Trans. Electron Devices, vol. 56, no. 10, pp. 2264–2269, Oct. 2009. [8] W. G. Vandenberghe, A. S. Verhulst, G. Groeseneken, B. Soree, and W. Magnus, “Analytical model for a tunnel field-effect transistor,” in Proc. IEEE 14th Mediterranean Electrotech. Conf. MELECON, May 2008, pp. 923–928. [9] C. Hu, “Green transistor as a solution to the IC power crisis,” in Proc. 9th ICSICT, 2008, pp. 16–20. [10] E. O. Kane, “Theory of tunneling,” J. Appl. Phys., vol. 32, no. 1, pp. 83–91, Jun. 1961. [11] A. S. Verhulst, D. Leonelli, R. Rooyackers, and G. Groeseneken, “Drain voltage dependent analytical model of tunnel field-effect transistors,” J. Appl. Phys., vol. 110, no. 2, pp. 024510-1–024510-10, Jul. 2011. [12] G. A. M. Hurkx, “On the modeling of tunneling currents in reversebiased p-n junctions,” Solid-State Electron., vol. 32, no. 8, pp. 665–668, Aug. 1989. [13] J. Z. Peng, S. Haddad, J. Hsu, J. Chen, S. Longcor, and C. Chang, “Accurate simulation on band-to-band tunneling induced leakage current using a global non-local model,” in Proc. 4th ICSICT, Oct. 1995, pp. 141–143. [14] Synopsys MEDICI User’s Manual, Synopsys Inc., Mountain View, CA, USA, 2010. [15] K.-H. Kao, A. S. Verhulst, W. G. Vandenberghe, B. Sorée, G. Groeseneken, and K. D. Meyer, “Direct and indirect band-to-band tunneling in germanium-based TFETs,” IEEE Trans. Electron Devices, vol. 59, no. 2, pp. 292–301, Feb. 2012. [16] D. Verreck, A. S. Verhulst, K.-H. Kao, W. G. Vandenberghe, K. D. Meyer, and G. Groeseneken, “Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors,” IEEE Trans. Electron Devices, vol. 60, no. 7, pp. 2128–2134, Jul. 2013.
1913
[17] A. Vandooren et al., “Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs,” Solid-State Electron., vol. 83, pp. 50–55, May 2013. [18] G. B. Beneventi, E. Gnani, A. Gnudi, S. Reggiani, and G. Baccarani, “Can interface traps suppress TFET ambipolarity?” IEEE Electron Device Lett., vol. 34, no. 12, pp. 1557–1559, Dec. 2013. [19] T. Krishnamohan, K. Donghyun, S. Raghunathan, and K. Saraswat, “Double-gate strained-Ge heterostructure tunneling FET (TFET) with record high drive currents and
