Designing from VHDL Behavioral Description to FPGA Implementation

Designing from VHDL Behavioral Description to FPGA Implementation Valentina Salapura, Gunter Waleczek fsalapura,

g

waleczek @vlsivie.tuwien.ac.at

Institut fur Technische Informatik Technische Universitat Wien Treitlstrae 3-182-2 A-1040 Wien AUSTRIA Abstract

In this paper we present the designing process of hardware, starting from a VHDL behavioral description of the design and nishing with the implementation in FPGAs. For logic level synthesis, the Synopsys synthesis tools are used. The possibilities and diculties of the approach are illustrated designing the CRC generator.

Introduction The ability to specify and describe hardware is fundamental to the process of designing digital systems. To verify functional correctness of system before they are manufactured or integrated into more complex system, models of circuits are used. Much of the design process entails modeling hardware on varying levels of detail. At the early design stage, models are used to evaluate the overall system performance and to explore issues such as design styles, resource allocation, data ow and component utilization. This modeling stage can be done using uninterpreted formalisms, such as Statecharts and Petri nets [HAWW89]. [BE93] showed that also the VHDL can be used for completing this task. In subsequent design stages, the model requires a more detailed description. At lower levels of abstraction, such as the behavioral, RTL and gate level, the usage of hardware description languages (HDL) becomes advantageous. From several hundred published HDLs, which are mostly academically used, only VHDL [IEE88] and Verilog [TM91] have become the widely accepted standards. VHDL has emerged as standard language for documentation, simulation and synthesis. It was developed as part of the DARPA-funded Very High Speed IC Initiative (whither its name, 1

VHSIC Hardware Description Language) and is an 'open' speci cation available as IEEE standard 1076.

Levels of abstraction Whereas the VHDL models written for the purpose of simulation can be exchanged between various tools for VHDL simulation, supported by dierent tool vendors, the usage of VHDL models for synthesis purposes is tool dependent. Actually, only a subset of the language is used for writing models for synthesis. As each synthesis system has its own style of modeling, the models being synthesizable with one vendor's synthesis tool can not be transferred to another vendor's synthesis tool without modi cation [SMG93]. Today's synthesis tools convert a description at the register-transfer-level (RTL) into gate level description, whereas the syntheses of a real behavioral description, which contains no information on structure and clock cycle, is still not possible. The levels of abstraction being relevant for synthesis process are shown in Fig. 1. The hardware design usually starts specifying the behavioral. This design should be transformed into an RTL description by adding structural and timing information. There are no tools on the market available which can perform this task. As the manner of writing the synthesizable model depends on synthesis tool used, obtaining the proper RTL description is a dicult task. Dierent constraints required by dierent synthesis tools have to be obeyed to satisfy a speci c modeling style and language subset. Generally, the synthesizable RTL description has to be created manually. After the synthesizable (tool dependent) RTL description of the design is obtained, the synthesis can start generating gate level net list, according to demands of target technology.

Basics of CRC CRC (Cyclic Redundancy Code) is an error detection scheme based on a serial bit stream of information where individual bits are treated as the coecients of binary polynomial. CRCs are widely used in the area of data transmission. For high speed networks, a parallel implementation of the CRC is required. Its structure depends on the polynomial function given and the degree of parallelism chosen. A brief introduction to parallel implementation modes of CRCs can be found in [Gei93]. The possibilities to generate VHDL models for simulation and synthesis purposes of CRCs are explored in [Pre94]. We modeled the CRC generator/checker using VHDL for behavioral description [Sal92] as a part of our model of SONIC [Nat90] which implements an Ethernet network controller and a DMA controller. As the Ethernet controller operates on 10 Mb/s, the speed of the CRC is not critical. For this reason, early in the design phase we chose a serial implementation. A serial CRC is implemented using linear feedback shift registers. 2

VHDL description (behavioral) USER ENTRY VHDL description (high RTL)

VHDL description (synthes. RTL)

VHDL description (gatelevel)

Functional verification

Timing verification

Figure 1: Levels of abstraction in h

XNF netlist

FPGA

Figure 2: The basic structure of a modeling process of a CRC component and the dierent modes of the module. The CRC calculates a 4 byte frame check sequence from incoming data stream and compares it with the last 4 bytes of the received packet (for checking) or appends the additional 4 bytes to the end of the transmitted packet (if generator). The CRC value is calculated as a function of the contents of input data stream using the generating polynomial. We use the following polynomial for the computation the checksum used in the IEEE 802.3 Ethernet [80283]: P (X ) = X 32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8 +X 7 +X 5 +X 4 +X 2 +X +1

VHDL models The VHDL modeling process can be partitioned into several abstraction layers, which are designed in a top-down fashion, as shown in Fig. 2. First, the behavioral VHDL model is developed and simulated to test the functionality and to be integrated into a more complex system (SONIC) for a complete circuit simulation. After the functionality of the circuits is veri ed, the RTL description is written. To ful ll the requirements of the synthesis tool, we had to rewrite our VHDL RTL description drastically.1 The reason for this is that synthesis tools use only a subset of the complete VHDL language, so many language constructs are not synthesizable at all. Examples are signal assignments with an after clause, or constraining of integers such as integer range 0 to 3. Besides, one has to know the proper usage of synthesis constraints provided by synthesis tool to obtain results with respect to given conditions such as optimization for minimum area or minimum delay. Using Synopsys DC V3.0, which performs logical synthesis, a gate level description of the unit under development is generated from the synthesizable RTL description. The export facilities provide the generation of both a VHDL gate level description and a XNF net list. The correct functionality of the gate level VHDL description of the design is veri ed by simulation. For synthesis, we used Synopsys DC V3.0 [SYN92a] and for simulation Synopsys VSS V3.0 [SYN92b]. 1

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Mapping to the technology The target technology was Xilinx FPGA [Xil93]. FPGAs provide short design and veri cation times which result in cost savings. For the generation of an XNF description of our design, we used the export facility of DC V3.0. We tried to use the built-in Xilinx library provided by Synopsys, but the available Xilinx library does not contain all primitives needed. Once we had generated the proper XNF description, the mapping to the technology was straight-forward, using Xilinx-supplied tools for le format conversion. The design was translated to the LCA level, where functions are mapped to particular CLBs. To verify the design on this stage, the whole translating process has to be reversed (from LCA over XNF into WIR-type les) to generate the proper le for simulation. The resulting implementation of the design ts into one XC4002 Xilinx FPGA. The generated report shows high utilization of function generators, whereas most of buses, I/O pins and ip- ops are unused. Preliminary evaluation of your selected part, 4002APC84: 11% utilization of io pins. ( 7 of 61) 70% utilization of function generators. ( 90 of 128) 34% utilization of clb flip-flops. ( 44 of 128) 3% utilization of bus resources. ( 1 of 32) The preliminary checks say the design will fit. PPR will proceed to the next stage. You selected what appears to be the best available part.

Experiments and results The VHDL descriptions of CRC were developed on various levels of abstraction. For each design step a complete simulation of the design is performed, with the same test bench. Some results are shown in table 1. The simulations were performed on SUN SPARC-station 10. Besides the simulation time, the table lists code size as quantitative factor of VHDL descriptions. One can notice that by adding new details on timing and structure in the VHDL description, the code is growing as well as simulation time. Time needed for synthesis of gate level description, the number of gates required for the design and the maximal delay are given in table 2. Here we list only results measured in DC V3.0. For the process of FPGA mapping, Xilinx tools are used for format conversions and mapping.

Conclusion VHDL provides a powerful mechanism for modeling complex designs. We used VHDL for description of the design at various design stages. Finally, the design 5

Abstraction level Simulation time VHDL code size Behavioral High RTL Synthesizable RTL Gate level Test bench le

3 sec. 6 sec. 8 sec. 170 sec. |

84 236 321 727 136

Table 1: The comparison of VHDL descriptions of the design on the dierent abstraction levels. Synthesis[min] 12 Area [gates] 216 Max. Delay [ns] 48,3 Table 2: Some characteristics of synthesis of CRC module. was mapped onto an XC4002 Xilinx FPGA. Each design phase was supported by tools. The translation of les to dierent le formats demanded by particular tools showed the number of interfacing bugs which have to be resolved. To overcome this diculties, we developed a number of programs for le translations. The translation from behavioral into RTL description was not supported by any commercial tool. The proper high level synthesis tool would help, as this step is the most time consuming step in the complete designing process.

Acknowledgment The authors would like to thank Michael K. Gschwind for his support and helpful discussions.

References [80283] [BE93] [Gei93]

ANSI/IEEE Std 802.3. IEEE standars for local area networks: Carrier sense multiple access with collision detection (CSMA/CD) access method and physical layer speci cations. IEEE, Inc, June 1983. Matthias Bauer and Wolfgang Ecker. Communication mechanisms for VHDL speci cation and designstarting at system level. In VHDL Forum for CAD in Europe, pages 95{105, March 1993. Olaf Geisler. VHDL based synthesis of a high speed full parallel 32 bit CRC generator/checker. In VHDL Forum for CAD in Europe, pages 133{137, March 1993. 6

[HAWW89] F. Hady, J. Aylor, R. Williams, and R. Waxman. Uninterpreted modeling using the VHSIC Hardware Description Language (VHDL). In International Conference on Computer Aided Design, pages 172{175, 1989. [IEE88] IEEE, Inc. IEEE Standard VHDL Language Reference Manual, March 1988. [Nat90] National Semiconductor Corporation. DP83932 System Oriented Network Interface Controller, May 1990. [Pre94] Viktor Preis. An approach to complex and self-generating VHDL models for simulation and synthesis. In VHDL Forum for CAD in Europe, pages 39{45, April 1994. [Sal92] Valentina Salpura. VHDL model of DP83932 system oriented network interface controller. Technical report, TU Wien, 1992. [SMG93] Manfred Selz and Klaus-Dieter Muller-Glase. Synthesis with VHDL. In VHDL Forum for CAD in Europe, pages 31{40, March 1993. [SYN92a] SYNOPSYS, Inc. Design Compiler Reference Manual Version 3.0, December 1992. [SYN92b] SYNOPSYS, Inc. System Simulator Reference Manual Version 3.0, December 1992. [TM91] D. E. Thomas and P. R. Moorby. The Verilog Hardware Description Language. Boston, MA, kluwer academic publishers edition, 1991. [Xil93] Xilinx, Inc., San Jose. The Programmable Gate Array Data Book, 1993.

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