A 47-dB Linear CMOS Variable Gain Amplifier using Current Squaring Technique Xin Cheng, Haigang Yang, Tongqiang Gao, Fei Liu Institution of Electronics, Chinese Academy of Science, Beijing 100190, China Graduate University of Chinese Academy of Science, Beijing 100049, China
[email protected] Abstract— In this paper, a CMOS linear-in-dB variable gain amplifier (VGA) is presented. The VGA consists of exponential control block which includes a current squaring circuit, amplifier block and common mode feedback block. Based on the current squaring block which doubles the gain range, a 47dB (–20dB to 27dB) continuous gain range is achieved with a single-stage structure. Simulation results show that the VGA core consumes 3mA of current from a 1.2V supply and has a 3-dB bandwidth greater than 200MHz. The IIP3 and the input referred noise density are within the ranges of 3 to –17dBm and 5 to 68 nV/sqrt(Hz) respectively. Key Words — CMOS, VGA, decibel linear, current squaring.
k (1 ax) 2 f ( x) k (1 ax )2
where k and a are constants and x is the independent variable. For k less than unity, the decibel linear range of (1) extends drastically and reaches its maximum value of 60dB at around k 0.12 with a linearity error of less than ± 0.5dB, which is a significant improvement compared to other pseudo exponential functions used for VGA designs. B. Current Squaring Circuit
I. INTRODUCTION Variable gain amplifiers (VGAs) are indispensable blocks in modern wireless communication systems such as Bluetooth, WLANs, and UWB. The main function of the VGA is to provide a fixed voltage output for different input signal levels, and thus the dynamic range of the overall system is greatly improved. In communication systems, the VGA is normally employed in a feedback loop to implement an automatic gain control (AGC) amplifier. The gain as an exponential function of control voltage, which is not an easily accessible characteristic in CMOS technology, is desirable for minimizing the settling time of the AGC loops[1]. Moreover, the VGA in communication system must demand wide gain range. The specific characteristic reduces the number of required VGAs, leading to lower power consumption, smaller chip area and higher bandwidth. In recent CMOS analog VGA designs, decibel linear gain variation characteristics are realized by the circuit implementations of pseudo-exponential[2-6]. The VGAs that adopt these functions offer less than 30dB of gain variation. To cover a wide dynamic range, conventional CMOS VGAs require at least 2 or 3 gain-varying stages. An effective solution to achieve such end is adopting bipolar transistors[7], but this requires a high amount of power dissipation and is not compatible with standard CMOS technology. This paper reports a new analog VGA that can provide a wide decibel linear range. The paper is outlined as follows. Section Ⅱ introduces the circuit implementation of the proposed VGA. Section Ⅲ describes the simulation results and section Ⅳ draws the conclusion.
Fig. 1. Current squaring circuit
Fig. 1 shows the schematic of the current squaring circuit adopted for the proposed VGA. The gate-source voltages of the two identical MOS transistors M1 and M2 are Va and Vb respectively. The sum of the gate-source voltages is kept constant via a voltage source V 2 . From
I 1 Kn (Va Vtn )2
(2)
I 2 Kn(Vb Vtn )2
(3)
it yields 2
1 I1 I 2 I 1 I 2 Kn(V 2 2Vtn)2 2 2Kn(V 2 2Vtn)2
II. VGA DESIGN
(4)
where V 2 Va Vb . From Fig.1 we have
Ib
1 Kn(V 2 2Vtn) 2 4
(5)
so the output current can be written as
A. Decibel Linear Function The approximated exponential equation used in this paper is given by
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(1)
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Iout I 1 I 2 2 Ib
I1 I 2
2
2 Kn(V 2 2Vtn ) 2
I in2 8 Ib
(6)
which describes a current squaring function. C. Control Circuit Block The circuit[3] for generating the denominator and the numerator of (1) is given in Fig.2, where all transistors operate in saturation mode. The drain currents of transistors Mp and Mn are given as
ID1 K p (V c V DD V tp ) 2
(7)
ID 2 Kn(Vc VSS Vtn)2
(8)
k (1 ax )2 k (1 ax) 2 where
The currents ID1 and ID 2 are added by a bias current I 0 . The resulting currents Ip and In , after some mathematical manipulations, can be given by
Ip Kp (VDD Vtp )2 I0 Vc (1 )2 2 VDD Vtp Kp(VDD Vtp )
I0 Vc (1 )2 2 VDD Vt In K (VDD Vt ) I0 Vc Ip (1 )2 2 VDD Vt K (VDD Vt )
k I 0 K (VDD Vt )2 , a 1 (VDD Vt )
and
x Vc .As can be seen in (11), the current ratio which is a function of the control voltage Vc , is equivalent to (1). In (11), adjusting the bias current I 0 can vary the value of k , resulting in different dB-linear ranges. Considering the case where VDD VSS 0.6V , if we shift all supply voltage nodes by 0.6V, VDD 1.2V , VSS 0 , accordingly the range of the input voltage Vc will vary and the exponential relation shown in (11) is still maintained. According to section B, the currents IC1 and IC 2 are squaring functions of Ip and In respectively, which are given as
(9)
In Kn (VSS Vtn ) 2 I0 Vc (1 )2 2 VSS Vtn Kn(VSS Vtn)
(11)
(10)
IC1 I 2p 8Ib
(12)
IC 2 I n2 8 Ib
(13)
substitution of (11) in (12) and (13) yields
IC 2 I n2 k (1 ax )2 IC1 I 2p k (1 ax) 2
2
(14)
D. Amplifier Block Fig. 3 shows the circuit schematic of the adopted amplifying block, including the common-mode feedback circuit. The amplifier consists of an input source-coupled pair (M3,M4) and diode-connected loads (M5,M6). The two currents IC1 and IC 2 from the control block in Fig. 2 are mirrored to M1 and M2 in Fig. 3. Therefore, the differential gain of the VGA can be expressed as
(a). The control circuit for generating the denominator
Av
gm3, 4 (W L)3, 4 IC 2 gm5, 6 (W L)5, 6 IC 1
(15)
substitution of (14) in (15) yields
Av
gm3, 4 (W L)3, 4 k (1 ax)2 gm5, 6 (W L)5, 6 k (1 ax)2
(16)
As a comparison, from the control current block used in previous papers[3] we have
(b). The control circuit for generating the numerator Fig. 2. The control circuit
Kp Kn K , VDD VSS , and Vtp Vtn Vt , from (9) and (10), the ratio In Ip can be
Assuming given by
IC 2 k (1 ax )2 IC1 k (1 ax) 2
(17)
so the differential gain of the VGA with the same amplifier
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is given as
Av
gm9, 10 (W L)9, 10 k (1 ax)2 (W L)10, 11 k (1 ax )2 gm11, 12
gain range without the penalty of other characteristics such as linearity. To cover a specific gain range, the VGA with the proposed structure needs less stages than other VGAs.
(18)
Fig. 5. Frequency response at highest gain setting Fig. 3. The amplifying stage
From (16) and (18), we can find that the proposed VGA doubles the decibel-linear range compared with previous VGAs, which leads to lower power consumption and smaller chip size. Ⅲ. SIMULATION RESULTS The VGA is designed using Chartered 0.13um CMOS technology with a supply of 1.2V, and is simulated by Cadence Spectre . Extensive simulation has verified its performance. As shown in Fig. 4, the decibel-linear gain varies from –20dB to 27dB when the control voltage varies from 0.47V to 1.05V. Fig. 5 shows the 3-dB bandwidth for the worst case (the highest gain setting) is 200MHz. The maximal input-referred intercept point (IIP3) is 3dBm at Vc of 0.8V and the minimal IIP3 is –17dBm at Vc of 1.05V which Fig. 6 shows. The simulated input-referred noise with frequency is plotted in Fig.7. It shows the input-referred noise is 68nV/sqrt(Hz) under the minimum gain and 5nV/sqrt(Hz) under the maximum gain. The VGA core consumes 3mA of current and for testing purpose, a source follower buffer is employed which consumes 3.5mA. The main performances are compared in Table 1 with some recently published structures. By comparison, we can see the proposed VGA design achieves a wide decibel-linear
(a). The maximal IIP3
(b). The minimal IIP3 Fig. 6. Simulated IIP3 of the proposed VGA
(a). The input-referred noise at lowest gain setting
Fig. 4. Gain versus control voltage
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Design
TABLE I COMPARISON OF MAIN CHARACTERISTICS [2] [3] [5] [6]
This work
Mode setting
continuous
continuous
continuous
discrete
continuous
CMOS process
90nm
0.18μm
0.18μm
0.18μm
0.13μm
Supply voltage(V)
1
1.8
1.8
1.8
1.2
Power(mW)
2.5
3.6
20.5
6.3
3.6
Gain range(dB)
–10~50
27~87
–39~54
12~108
–20~27
Number of stages
4
2
3
5
1
Bandwidth(Hz)
2.2G
16M
900M
300M
200M
IIP3(dBm)
-
–60~–11
-
–5
–17~3
P1dB(dBm)
–55~–13
-
–59.1~–10.8
-
–26.2~ –7.4
17~30dB
13μVrms
6.8dB
23.8~37.2dB
5~68nV/sqrt(Hz)
Noise figure or input referred noise
2008 IEEE Solid-State and Integrated-Circuit Technology, pp. 1669-1675, October 2008. [4] T. Yamaji , Kanou and T. Itakura, “A temperature stable CMOS variable gain amplifier with 80-dB linearly controlled gain range,” IEEE Journal of Solid-State Circuits, vol. 37, no. 5, pp. 553-558, May 2002. [5] H. D. Lee, K. A. Lee, and S. Hong, “A wideband CMOS variable gain amplifier with an exponential gain control,” IEEE Trans. Microwave Theory & Tech., vol. 55, no. 6, pp. 1363-1373, June 2007. [6] D. G. Liang, Q. Ye, “A 96-dB CMOS programmable gain amplifier for Low-IF receiver,” 2008 IEEE Communication, Circuits and Systems, pp. 101-104, May 2008. [7] M. Heping, Y. Fang, “A low power baseband chain for CMMB application,” 2008 IEEE Communication Systems, pp. 1466-1470, November 2008. [8] K. Bult, H. Wallinga, ”A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturation,” IEEE Journal of Solid-State Circuits, vol. 22, no. 3, pp. 357-365, June 1987.
(b). The input-referred noise at highest gain setting Fig.7. The input-referred noise of the proposed VGA
Ⅳ. CONCLUSION This work introduces a single-stage CMOS VGA with continuous exponential tuning characteristics. Based on a current squaring circuit, it proposes a new structure to extend the decibel-linear gain range. The VGA provides 47dB variable gain, a bandwidth of more than 200MHz, an input-referred noise of less than 68nV/sqrt(Hz), and P1dB and IIP3 of –26.2 to –7.4dBm and –17 to 3dBm, respectively. The whole core of the circuit consumes a current of 3mA from a 1.2V supply. REFERENCES [1] J. M. Khoury, “On the design of constant settling time automatic gain control circuits,” IEEE Trans. Circuits Syst. Ⅱ, Analog Digit. Signal Process, vol. 45, no. 3, pp. 283-294, March 1998. [2] Y. J. Wang, B. Afshar, and T. Y. Cheng, ”A 2.5mW inductorless wideband VGA with dual feedback DC-Offset correction in 90nm CMOS technology,” 2008 IEEE Radio Frequency Integrated Circuits Symp. Dig, vol. 1 , pp. 91-94, June 2008. [3] Q. Q. Lei, and Z. M. Chen, “A Low-power CMOS VGA with 60-dB linearly controlled gain range for GPS application,”
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