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Novel Three Dimensional (3D) NAND Flash Memory Array Having Tied Bit-line and Ground Select Transistor (TiGer) Se Hwan Park† Yoon Kim† Wandong Kim† Joo Yun Seo† Jong-Ho Lee† Hyungcheol Shin† and Byung-Gook Park†
† Inter-University Semiconductor Research Center and School of Electrical Engineering and Computer Science, Seoul National University, San 56-1, Sillim-dong, Gwanak-ku, Seoul 151-742, Republic of Korea
E-mail:
†
[email protected]
Abstract In this paper, a three dimensional (3D) NAND flash memory array having Tied Bit-line and Ground Select Transistor (TiGer) is investigated. Bit-lines are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked bit-lines, a novel operation scheme is introduced instead of adding supplementary control gates. The stacked layers are selected by using ground select line (GSL) and common source line (CSL). Device structure and fabrication process are described. Operation scheme and simulation results for program inhibition are also discussed. Keyword 3 dimensional NAND flash memory, operation scheme, program inhibition.
1. Introduction
A. Array Structure and Fabrication Method The STAR (STacked ARray) NAND flash memory with
Due to rapidly growing digital information technology, demands for high density flash memories have been continually increasing. As a breakthrough of the scaling limitations, 3D stacked memory arrays are under development especially in NAND flash memories. Stacking of multi-layers is a solution of increasing memory density without shrinking of device size.[1-4] Mainly, there are two types of 3D NAND flash memory arrays. One is a word-line stacked array and another is a bit-line stacked one. In the word-line stacked type, it is difficult to form single crystal channels because bit-lines are formed after stacking multiple word-lines and dielectric layers. Therefore, performances of each cell are degraded and electrical characteristics among cells are not uniform. In this paper, a bit-line stacked array having single
the TiGer structure is shown in Fig. 1. Basically, its unit cell has the gate-all-around (GAA) structure with a single crystal Si channel[5]. The bit-line and word-line are perpendicularly crossed each other and multiple stacked bit-lines share word-lines. Each stacked layer has an individual common source line (CSL). The main feature of TiGer structure is the connection of bit-line and GSL.
crystal Si channels is investigated. For distinguishing stacked bit-lines, novel array which is Tied bit-line and Ground select transistor (TiGer) structure and operation scheme are introduced.
2. Results and Discussion
Fig. 1.STAR (Stacked ARray) NAND flash memory having TiGer structure
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The single crystal Si bit-lines are epitaxially grown using SiGe/Si layers. After multiple SiGe/Si layers are
B.
Operation
Scheme
and
Simulation
of
Program Inhibition
stacked, only Si layers remain by selective SiGe removal.
In a 3D stacked NAND flash memory, compact array
If the selective etching of SiGe is performed on patterned
with reliable operation scheme is an important element.
bit-lines, the remaining Si layer can be collapsed due to
The TiGer structure is one of the simplest arrays because
its weight. To prevent collapsing of bit-lines, word-lines
no line is added compared with the conventional NAND
are formed by damascene process. First, trenches are
flash memory. As a result, TiGer structure requires a
formed for the damascene gate and the exposed SiGe
novel operation scheme to distinguish the stacked bit-line.
layers are selectively etched. Then, the remaining SiGe
The main difference with the conventional array is the
layers are removed after forming gates so that the gate
direction of pre-charge. In case of the conventional
supports the bit-lines. (Fig. 2)
NAND
flash
memory, charges are injected through
bit-line and GSL turns off in order to block current flow through CSL. Otherwise, in case of TiGer structure, charges flow through CSL and SSL turns off. (Fig. 3)
(a)
(b) (a)
Fig. 3. The pre-charge direction of (a)TiGer structure and (b)conventional array Fig. 4 shows the equivalent circuit of array with the TiGer structure. During program operation, FN tunneling occurs in the selected bit-line. To inhibit program in unselected strings, the channel of unselected bit-lines maintains sufficiently high potential using self-boosting scheme. To distinguish the strings sharing the same bit-line, the CSL bias of selected layer decreases to 0V, while that of unselected layers maintains high voltage. Then, only the channel potential of selected string is low enough to induce FN tunneling. To inhibit the program of the unselected bit-lines, the GSL bias decreases to 0V in order to maintain high channel potential regardless of CSL bias. (Fig. 5).
(b) Fig. 2. (a) Damascene gate and selective SiGe etch process
to
support
nanowires.
(b)
removal after the word-lines formation.
Remaining
SiGe
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no body. The GIDL current near the select gate junction leads to a body potential rise through hole accumulation.
Fig. 4. Equivalent circuit of array with the TiGer structure
(a)
(b)
(c)
(d)
Fig. 6. Channel potential of each string (a) selected string, (b) unselected string sharing bit-line, (c) unselected string sharing CSL, (d) unselected string not sharing both bit-line and CSL
Fig. 5. Timing diagram of pre-charge and program operation The program inhibition is simulated using SILVACO ATLAS. For simulation, a STAR NAND flash memory is designed as follows. The radius of Si nanowire channel and the gate length is 15nm and 150nm. The body doping concentration and O/N/O thickness are 5x10 17 /cm 3 , 3/9/9 nm, respectively. The source/drain region is induced by the gate fringing field. Electrons of 1x10 16 C are injected into nitride trapping layers under SSL and GSL gate in order to prevent leakage through SSL and GSL transistor during program operation. Fig. 6 and 7 show the simulated channel potential of each string during program operation
and
their
I D -V G
characteristic
after
programming. The channel potential of unselected strings is high enough to inhibit FN tunneling so that program is performed in only the selected string. For erase operation, gate induced drain leakage (GIDL) current is used in nanowire NAND flash memory having
Fig.
7.
I D -V G
characteristic
of
each
string
after
programming [program condition: V prog = 9V, t prog = 50 sec]
社団法人 電子情報通信学会 THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS
信学技報 TECHNICAL REPORT OF IEICE
4. Summary The STAR NAND flash memory having Tied Bit-line and Ground select transistor is proposed. Bit-lines are stacked in the vertical direction to increase the memory density without the device size scaling. To distinguish stacked bit-lines, a novel operation scheme is introduced instead of adding supplementary control gates.
5. Acknowledgements This work was supported by the IT R&D program of the Korean Ministry of Knowledge Economy (MKE/KEIT, project no. 10035320, “Development of Novel 3-D Stacked
Device
and
Core
Materials
for
the
Next
Generation Flash Memory”).
References [1] H. Tanaka, et al., “Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory,” VLSI Tech. Dig., pp. 14-15, 2007. [2] Y. Komori, et al., “Disturbless Flash Memory due to High Boost Efficiency on BiCS Structure and Optimal Memory Film Stack for Ultra High Density Storage Device,” IEDM Tech. Dig., pp. 1-4, 2008. [3] S. Lai, “Non-Volatile Memory Technologies: The Quest for Ever Lower Cost,” IEDM Tech. Dig., pp. 1-4, 2008. [4] H. Aochi, “BiCS Flash as a Future 3D Non-volatile Memory Technology for Ultra High Density Storage Devices,” International Memory Workshop, pp. 1-2, 2009. [5] K. H. Yeo, et al., “Gate-all-round Single Silicon Nanowire MOSFET with 7 nm width for SONOS NAND Flash Memory,” VLSI Tech. Dig., pp. 138-139, 2008.
