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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 1, JANUARY 2012
A Compact Three-Phase Single-Input/Dual-Output Matrix Converter Xiong Liu, Student Member, IEEE, Peng Wang, Member, IEEE, Poh Chiang Loh, Member, IEEE, and Frede Blaabjerg, Fellow, IEEE
Abstract—This paper presents a novel matrix converter with one ac input and two ac outputs. The presented topology is based on the traditional indirect matrix converter, but with its rear-end six-switch inverter replaced by a compact nine-switch inverter. With only three extra switches added, the proposed converter can produce two sets of three-phase ac outputs, whose amplitudes, frequencies, and phases can appropriately be regulated. Features such as sinusoidal input and outputs, unity input power factor and minimum commutation count are all retained by the proposed topology, despite having an additional output. Its modulation is realized by the computationally less intensive carrier-based method, whose unique carrier requirements can easily be managed within a programmable logic device. Mathematical proof for validating sinusoidal input and outputs achieved by this modulation technique is also discussed, before being verified in simulation and experimentally, together with other findings. Index Terms—Carrier-based modulation, dual outputs, FPGA, indirect matrix converter (IMC), nine-switch converter.
I. I NTRODUCTION
A
C-AC POWER converters are ubiquitous in practical applications such as adjustable speed motor drives, wind generation systems, electronic transformers, and many others. Among the plentiful ac-ac converter topologies available, the traditional back-to-back converter, comprising a common dclink capacitor and two voltage-source inverters, is frequently used [1]. The main drawback of this topology is its requirement for a bulky electrolytic capacitor at its dc-link for filtering and short-term energy storing purposes. This capacitor has always been the main source of premature failures, affecting converter reliability. Another shortcoming experienced by the back-toback converter is its requirement for two bulky sets of threephase line inductors, whose sizes would limit its compactness, when implemented. Other than the back-to-back topology, different ac-ac matrix converters can be considered [2]–[11], including the direct matrix converter, indirect matrix converter (IMC), sparse matrix converter, ultra-sparse matrix converter, and others. These
Manuscript received September 30, 2010; revised March 6, 2011; accepted April 6, 2011. Date of publication April 21, 2011; date of current version October 4, 2011. X. Liu, P. Wang, and P. C. Loh are with the School of EEE, Nanyang Technological University, Singapore 639798 (e-mail:
[email protected];
[email protected];
[email protected]). F. Blaabjerg is with the Institute of Energy Technology, Aalborg University, 9220 Aalborg East, Denmark (e-mail:
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TIE.2011.2146216
Fig. 1.
Topology of an indirect matrix converter.
matrix converters can convert any three-phase input ac source to an ac output with controllable amplitude, frequency and phase. Without the intermediate dc-link capacitor, matrix converters, being “all-semiconductor,” are more easily packed to a smaller enclosure, which is probably their main attraction. It should however be noted that although matrix converters do not have any dc-link capacitor, the name “dc-link” is still frequently used with the indirect, sparse and ultra-sparse matrix converters. To illustrate why, the IMC shown in Fig. 1 is considered, where a fictitious dc-link is undeniably formed, after cascading the front-end current-source rectifier (CSR) to the rear-end voltage source inverter (VSI). Although many matrix topologies have been proposed, they are mostly of the single-output type, therefore not suitable for applications like electric traction locomotives and elevators, where two (or more) motors need to be driven independently [12]. For the IMC shown in Fig. 1, the most straightforward solution is to use one rear-end inverter for each ac load, which means N inverters with 6N switches for N loads, where N is an integer. The resulting topology might unnecessarily be costly and bulky, since sharing of switches has not yet been properly considered. In fact, for the specific case of N = 2k (or 2k + 1) loads, the total number of switches can be reduced from 12k to 9k (or 9k + 6), based on the nine-switch topological concept proposed in [13], [14], and redrawn in Fig. 2. Conceptually, the nineswitch inverter merges two six-switch inverters together by sharing three switches, therefore also has two three-phase ac outputs and a common dc-link. The shared switches are in fact the middle three switches (ST2 , ST5 , and ST8 ) with them forming the first inverter with the upper three switches (ST1 , ST4 , and ST7 ) and the second inverter with the lower three switches (ST3 , ST6 , and ST9 ). More than two outputs can
0278-0046/$26.00 © 2011 IEEE
LIU et al.: COMPACT THREE-PHASE SINGLE-INPUT/DUAL-OUTPUT MATRIX CONVERTER
Fig. 2.
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Dual output nine-switch inverter. Fig. 3. Topology of proposed matrix converter.
also be catered by paralleling more nine-switch inverters and six-switch inverters with the latter mainly needed only when the number of outputs demanded is odd (2k + 1). However, application of the nine-switch inverter is less than perfect at present due to its higher rated dc-link capacitor, needed to produce the same ac output voltages as per the case of two individual inverters. The reason is mainly linked to the fact that the sum of modulation indices of its two outputs must be lesser or equal to unity when their frequencies are different. [15], [16] advanced the concept by adding a Z-source network to the dc-link of the nine-switch inverter to introduce an additional degree of buck-boost freedom to its dual outputs, but it still requires bulky and higher rated passive components and in fact is worsened since two inductors and two capacitors are now present. Therefore, bulky volume and relatively low reliability are the presently unsolved shortcomings of existing nine-switch inverters. To firmly remove passive components from its dc-link, the idea of applying the indirect “all-semiconductor” matrix conversion concept to the nine-switch inverter is proposed here. The resulting topology still has dual outputs but can better match industrial conditions, where the primary electrical supply is ac and unity power factor operation is commonly sought for. Modulation scheme for the new single-input/dual-output matrix converter would certainly be more complex, particularly if features like sinusoidal input and outputs, unity power factor and minimum commutation count have to be achieved simultaneously. This complexity is resolved in this paper with full mathematical details provided for validation. Hidden conceptual details for easier implementation, while producing the correct modulation state sequences, are also discussed before being verified in simulation and experiment together with other findings. II. S INGLE -I NPUT /D UAL -O UTPUT M ATRIX C ONVERTER AND I TS O PERATIONAL P RINCIPLES A. Topology As mentioned above, the proposed matrix converter is based on the indirect matrix converter shown in Fig. 1 and the nineswitch inverter shown in Fig. 2. If regeneration capability is expected, the front-end CSR of the matrix converter needs 12 switches in total, as illustrated in Fig. 1. For applications where only unidirectional power flow is required, the ultrasparse matrix converter with a three-switch CSR can be used
Fig. 4. Space vector representation of CSR.
instead, which in fact is the topology based upon for the following analysis and verification, because of its simplicity. The concepts presented are certainly applicable to the bidirectional case, too. Upon cascading the mentioned two entities together, Fig. 3 shows the resulting proposed matrix converter without any passive dc-link component. Only 12 switches are needed in total to form one input and two outputs with several operating scenarios possible with its dual outputs, identified as same frequency, same amplitude, different frequencies, different amplitudes or a combination of them. These operating modes must be considered comprehensively, together with their associated fictitious dc-link current values, before a proper modulation strategy can be formulated for achieving sinusoidal input and outputs. Further discussion on it will be presented shortly in the section focusing on modulation theories. B. Operational Principles Because of its direct cascading basis, operational principles of the proposed matrix converter can be analyzed by studying its entities separately, before coordinating them later for optimal performance. Beginning with the front-end CSR then, two of its three switches must alternately be switched on to bring forth one of the nearest two space states surrounding the input current reference phasor, which also is the source voltage phasor for unity power factor operation. To illustrate, the vector diagram and reference phasor in Fig. 4 are drawn, which when transferred to the time domain, gives rise to those variations shown in Fig. 5. The applied dc-link voltage Vdc would then be the vertical length measured between any two waves in Fig. 5,
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TABLE II S WITCHING S TATES FOR N INE -S WITCH I NVERTER
Fig. 5. Six intervals of CSR input voltage waveforms. TABLE I S WITCH C OMBINATIONS AND C ORRESPONDING F ICTITIOUS DC-L INK VOLTAGE FOR E ACH CSR S EXTANT
Fig. 6.
Illustration of current path for a specific converter switching state.
flow path shown for better clarity. This is however only one scenario at an instant in time, whose orientation would change when a new state is entered or when a phase current reverses its direction, as time progresses. III. M ODULATION AND S INUSOIDAL I NPUT /O UTPUT P ROOF depending on which two CSR switches are turned on. Vdc can also be zero, if only one CSR switch is turned on, but this null state is usually not considered since it does not lead to maximal converter output. Vdc will then vary between vab and vac only, when in sextant 1 (−π/6 to π/6) of the vector diagram. The remaining voltages assumed by it are listed in Table I for the other five possible sextants. Putting Fig. 5 and Table I together would then clarifies that the fictitious dc-link voltage applied to the rear-end nineswitch VSI is not constant, but varies across sextants. This is unlike the conventional nine-switch inverter shown in Fig. 2, where a constant source voltage is usually applied. Modulating conditions of the nine-switch VSI here must therefore be modified accordingly to retain its sinusoidal outputs. This will be discussed in a later section focusing on modulation theories. For now, the middle shared switches of the nine-switch VSI are analyzed to check on how they limit the inverter operation. Taking ST2 in Fig. 3 as an example, turning it off would force the other switches in the same phase-leg, ST1 and ST3 , to turn on, so as not to float any output. On the other hand, turning ST2 on would demand that only ST1 or ST3 can be turned on to avoid shorting the dc-link, while yet not float any output. Summarizing these constraints then leads to those three switching states per phase-leg shown in Table II, which together with Table I, governs the switching process of the overall matrix converter. For an illustration of how the states can be combined, Fig. 6 is drawn with only the ON switches and a typical current
Modulation of matrix converter using space vector theory has long been established, and is known to have the advantage of flexible control over all its chosen space vectors, but at the expense of high computational burden and a sizable lookup table [17]–[19]. In contrast, carrier-based modulation introduces simplicity, but has no controllability over its auto-sequencing of states. Its simplicity has recently attracted the attention of some researchers, who have successfully applied carrier-based modulation to matrix converter. Because of this recent interest, analyses presented below are biased toward the carrier-based approach, but would still be valid for a space vector system since they share the same theoretical bases. A. Modulation of CSR As mentioned earlier, the front-end CSR imposes a selected input line voltage across the dc-link of the rear-end nine-switch inverter. When in sextant 1, the imposed line voltage would either be vab or vac , depending on whether the nearest active state SC6 or SC1 is chosen, as reflected in Table I. The nearest two active states are in turn chosen based on which sextant the current reference phasor (or grid voltage phasor for unity power factor operation) is residing. Regardless of which two states are chosen though, their combined effects are to clamp one switch to a dc rail and modulate the other two switches alternately to the other dc rail. For the present two states of SC6 and SC1, the clamped switch to the positive dc rail is Sa, while the modulated switches to the negative dc rail are Sb and Sc. Defining (1) as the input, duty ratios of the modulated switches
LIU et al.: COMPACT THREE-PHASE SINGLE-INPUT/DUAL-OUTPUT MATRIX CONVERTER
Fig. 7.
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Normalized variation of dc-link voltage over a fundamental cycle.
Sb and Sc, labeled as di1 and di2 , respectively, can conveniently be determined as (2) va = Vm cos θia θia = ωi t
vb = Vm cos θib
θib = θia − 2π/3
vc = Vm cos θic
θic = θia + 2π/3
va + vb + vc = 0
(1)
cos θia + cos θib + cos θic = 0 di1 = − cos θib / cos θia
−
cos θib cos θic − =1 cos θia cos θia
di2 = − cos θic / cos θia
(2)
where Vm is the input voltage amplitude, and θia , θib , and θic are the phase angular displacements. From (1) and (2), mathematical expression for computing the average dc-link voltage over a switching cycle Vdc(av) is derived as (3) for sextant 1 only. Generalizing (3) to all sextants then results in (4), where vmax = max(va , vb , vc ) and vmin = min(va , vb , vc ). Equation (4) is no doubt time-varying, whose normalized six-pulse variation is plotted in Fig. 7 over a full fundamental period. This varying dc-link voltage must later be compensated, before sinusoidal dual outputs can be produced by the nine-switch VSI Vdc(av) = di1 vab + di2 vac =
Fig. 8. Modulating references for nine-switch inverter when in (a) CF and (b) DF modes.
3Vm 2 cos θia
−
π π ≤ θia ≤ 6 6 (3)
Vdc(av) =
3Vm2 , 2|vmax |
for positive rail clamping
Vdc(av) =
3Vm2 , 2|vmin |
for negative rail clamping.
(4)
B. Modulation of VSI Carrier-based modulation of a traditional six-switch VSI with a fixed dc-link voltage is well known, and can be done simply by comparing three balanced sinusoids with a common triangular carrier. Applying it to two individual VSIs is straightforward too, since it just means duplicating another set of independent three-phase sinusoids and performing the same carrier comparison. Such independent duplication is however not directly applicable to the nine-switch VSI, because of its constrained phase-leg switching states listed in Table II. To
ensure that only the allowed switching states are produced, modulating references of the upper terminals must always be placed above those of the lower terminals while using just one carrier [13], [14]. Illustrations can be found in Fig. 8 with the two references per phase having either the same common frequency (CF mode) or different frequencies (DF mode). The references are clearly well separated vertically with no point of intersection noted between them, so as to avoid unwanted switching states and their accompanied volt-sec error. For the case of CF mode shown in Fig. 8(a), the criterion of clear separation is more correctly interpreted as a phase-shift constraint, limiting the maximum modulation indices of the references. In general, the following trend is a smaller phase-shift leading to larger modulation indices that can eventually reach a maximum of unity each (or 1.15 if triplen offset is added) when the phase-shift drops to zero. Such phase-shift constraint is, however, not felt during DF mode shown in Fig. 8(b). Rather, a strict amplitude constraint is imposed to the DF mode, which effectively limits its sum of modulation indices for its two references to be lesser or equal to unity (or 1.15) under all circumstances. Upon understanding the constraints and placing the references appropriately, they can next be compared with a single triangular carrier, but unlike traditional VSI control, the carrier for matrix modulation has variable rising and falling slopes. Modulating references are also no longer sinusoidal, after adding appropriate triplen offsets and compensating for dc-link variation. Both modifications are addressed hereon, but before proceeding ahead, it might be helpful to clarify how the references and carrier are related to the switches of the rear-end nine-switch VSI drawn in Fig. 3. For that, the variable-slope triangular carrier shown in Fig. 9, and the first phase-leg in Fig. 3, comprising ST1 to ST3 , are considered as an example. In this example, the references per phase in Fig. 9 are intentionally drawn as horizontal constant lines in the single carrier period considered, which certainly is appropriate because of the usually much higher carrier frequency assumed. Comparing the upper reference with the variable carrier then results in one train of gating signal for ST1 , while doing the same with the lower reference results in another gating signal
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Fig. 10. Switching coordination between CSR and one leg of nine-switch VSI.
Fig. 9. Gating signal generation for one leg of nine-switch VSI.
for ST3 . For better visualization, these described comparisons and gating signals for ST1 and ST3 are shown in the middle of Fig. 9, whose mathematical expressions are written as 1, vA ≥ vtri 1, vR ≤ vtri ST1 = ST3 = (5) 0, vA < vtri 0, vR > vtri where vA and vR are the upper and lower references for the first phase-leg considered, and vtri is the variable-slope triangular carrier. Gating signal for ST2 is then generated by performing logical operation ST2 = ST1 ⊕ ST3 , where ⊕ is the XOR operator. Comprehending the three signals for ST1 , ST2 , and ST3 finally lead to the state sequence shown at the bottom of Fig. 9, which as anticipated, contains only those three allowable states listed in Table II. As for the dc-link variation shown in Fig. 7, its effect is removed from the outputs by simply dividing the modulating references with this variation. The resulting non-sinusoidal references are listed, as follows: vA =
Vo1 · cos(ω1 t + θA ) + Voff1 + Voff _up Vdc(av) /2
Voff1 = − 0.5 (max(vA , vB , vC ) + min(vA , vB , vC )) vR =
(6)
Vo2 · cos(ω2 t + θR ) + Voff2 − Voff _down Vdc(av) /2
Voff2 = − 0.5 (max(vR , vY , vW ) + min(vR , vY , vW )
(7)
where (Vo1 , Vo2 ), (ω1 , ω2 ) and (θA , θR ) represent amplitudes, angular frequencies, and phases of the upper and lower output references, while (Voff1 , Voff2 ) represents triple offsets commonly added to raise the modulation indices by 15% each [20]. To prevent the upper and lower references from crossing each other, offsets Voff _up and Voff _down are also added in (6) and (7) to shift the upper and lower references up toward the carrier peak and down toward the carrier trough, respectively. The same equations are equally applicable to the other two phases, after introducing their respective phase-shifts of 120◦ and −120◦ . The VSI references must next be synchronized with the CSR switching, so as to produce sinusoidal input for the overall
Fig. 11. Three-phase reference-carrier arrangement and state sequence generation for proposed matrix converter.
matrix converter. To realize it, the common triangular carrier for comparing with the upper and lower VSI references must be gradient varying. The main intention here is to force each triangular rising or falling edge to span a complete CSR switching state duration, expressed as di1 Ts and di2 Ts , within the period Ts of the carrier. An example illustrating the coordination process is given in Fig. 10, where a normal triangular carrier is first compared with duty ratio di1 of the CSR to produce the variable-slope carrier for the VSI. The rising edge duration di1 Ts of the modified carrier then spans over state SC6 (Sa, Sb) of the CSR, while the falling edge duration di2 Ts spans over state SC1 (Sa, Sc). Synchronizing in this way ensures that each VSI state is divided proportionally between the two CSR states, while still producing the same VSI states from Table II. The state division also leads to the proportional division of average dc-link current flowing during the two CSR state durations of di1 Ts and di2 Ts . Ratio of the average dc-link currents in the two durations is then di1 /di2 , which according to (2), is equal to the ratio of phase b to phase c currents ib /ic , if operating in sextant 1 with unity power factor. Currents drawn by the CSR would then be threephase sinusoidal, so long as the dc-link current varies according to cos θia , as will be shown in Section III-C. So far, all carrier diagrams shown are for a single phaseleg of the rear-end nine-switch VSI. For completeness, Fig. 11
LIU et al.: COMPACT THREE-PHASE SINGLE-INPUT/DUAL-OUTPUT MATRIX CONVERTER
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only after determining the average dc-link current. Applying KCL at point P in Fig. 3 then leads to Idc = I1 + I2 + I3
Fig. 12. Three possible equivalent circuits for leg 1 of nine-switch VSI.
shows the modulation process and resulting state sequences for the upper and lower terminals, when all six upper and lower references are considered. The state sequences obviously have four distinct switching states each, labeled as N0, A1, A2, and N1, which are no different from those associated with a traditional six-switch VSI. Noting further that the upper three-phase terminals are controlled by switches ST1,4,7 and ST2,5,8 , state A1{1,1,0}, analyzed as an example, would be inserted by simply turning ST1,4,8 ON and ST2,5,7 OFF. The same would apply to the lower three-phase terminals controlled by switches ST2,5,8 and ST3,6,9 , even though an example is not explicitly quoted here, because of close similarity. Combining the upper and lower switching states then results in seven distinct states for the overall nine-switch VSI, shown as a fourth sequence in Fig. 11. Each of the combined states contains status information about the nine switches, which can be analyzed by quoting state 6 as an example. State 6 is formed by the upper A2{1,0,0} and lower N0{0,0,0} states, whose corresponding first numbers state that ST1 = 1, ST3 = 1, and hence ST2 = ST1 ⊕ ST3 = 0. When placed together, state S3 = ST1,2,3 = {1, 0, 1} is formed, which indeed is one of the three allowed states shown in Table II. Switching states for the other two phase-legs are determined in the same manner with the eventual state 6 written as {S3, S2, S2}. State 6 and its other six companions are also noted to divide proportionally according to the ratio of di1 /di2 , which can promptly be confirmed by comparing the hatched triangles ΔABC and Δabc in Fig. 11 and noting that BC/bc = di1 /di2 . Sinusoidal input and output waveforms are therefore guaranteed with negligible CSR commutation losses anticipated. The reason for the latter is easily explained by referring to Fig. 11, where it is shown that the synchronization process causes the CSR to commutate only when in state 7 {S2, S2, S2}, during which no dc-link current flows, and hence no switching losses is produced. C. Mathematical Proof for Sinusoidal Input and Outputs Using the normalized modulating references expressed in (6) and (7), the rear-end VSI would produce sinusoidal outputs for both upper and lower terminals, as mentioned earlier. The remaining feature yet to be proven mathematically is the sinusoidal input currents of the CSR, whose expressions are known
(8)
where i1 , i2 , and i3 are the average currents flowing through the three phase-legs of the nine-switch VSI. Values of these three currents are determined by studying the VSI switching states in Fig. 9 and equivalent circuits in Fig. 12. Taking i1 as an example then, its current expressions are derived as iA + iR , iA and zero when in states S1, S3 and S2, respectively. By noting further that the time durations for states S1 and S3 are (1 − d3 )Ts and (d1 + d3 − 1)Ts , respectively, where d1 and d3 are the duty ratios of switches ST1 and ST3 , i1 is eventually determined as i1 = (1 − d3 ) · (iA + iR ) + (d1 + d3 − 1) · iA = (1 − d3 ) · iR + d1 · iA .
(9)
Following the same approach, currents i2 and i3 are determined as i2 = (1 − d6 ) · iY + d4 · iB
(10)
i3 = (1 − d9 ) · iW + d7 · iC .
(11)
Substituting (9), (10) and (11) into (8) then leads to an expression for Idc , written as Idc = d1 · iA + d4 · iB + d7 · iC + iR + iY + iW − d3 · iR − d6 · iY − d9 · iW .
(12)
Upon substituting iR + iY + iW = 0 for balanced loads, (12) simplifies to idc = d1 · iA + d4 · iB + d7 · iC − d3 · iR − d6 · iY − d9 · iW . (13) Equation (13) can only be solved after finding expressions for the two sets of output currents and modulation ratios. For the former, considering the same example of phase-leg quoted earlier would result in the following two output currents flowing out of the matrix converter: iA = io1 · cos(ω1 t + θA − ϕo1 ) iR = io2 · cos(ω2 t + θR − ϕo2 )
(14)
where (Io1 , Io2 ) and (ϕo1 , ϕo2 ) are amplitudes and power factor angles of the output currents, measured with reference to the normalized modulating voltages given in (6) and (7). Duty ratios d1 and d3 , on the other hand, can be calculated by applying similar triangle relation to Fig. 9. Resulting expressions obtained are summarized as (1 − d1 ) · Ts 1 − vA 1 + vA ⇒ d1 = = Ts 2 2 d3 · T s 1 − vR 1 − vR ⇒ d3 = . = Ts 2 2
(15)
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TABLE III C OMPONENT PARAMETERS U SED W ITH E XPERIMENTAL M ATRIX C ONVERTER
Duty ratios d4,7,6,9 can similarly be derived as d4 =
1 + vB 2
d7 =
1 + vC 2
d6 =
1 − vY 2
d9 =
1 − vW . 2 (16)
Fig. 13. Simulation results in CF mode showing three-phase input currents, fictitious dc-link voltage and current from top to bottom.
Substituting (15) and (16) into (13) then leads to another intermediate expression for Idc in (17), which upon being substituted by (6) and (7) and (14), leads to the final generalized expression for Idc in (18) vA vB vC vR · iA + · iB + · iC + · iR 2 2 2 2 vY vW · iY + · iW + 2 2 3 (Vo1 · Io1 · cos ϕo1 + Vo2 · Io2 · cos ϕo2 ) = · . 2 Vdc(av)
Idc =
Idc
(17) (18)
Considering sextant 1 of the input CSR as an example, Vdc(av) in (3) can be substituted into (18) to give Idc =
(Vo1 · Io1 · cos ϕo1 + Vo2 · Io2 · cos ϕo2 ) · cos θia . Vm (19)
It is timely now to recap that switch Sa is always clamped to the positive dc rail, while switches Sb and Sc are pulsewidth modulated to the negative dc rail with duty ratios of di1 = − cos θib / cos θia and di2 = − cos θic / cos θia , respectively. Based on this operating scenario and (19), input currents of the proposed matrix converter are determined as (20), which indeed are sinusoidal ia = Idc = Iin · cos θia ib = − Idc · di1 = Iin · cos θib ic = − Idc · di2 = Iin · cos θic (Vo1 · Io1 · cos ϕo1 + Vo2 · Io2 · cos ϕo2 ) Iin = . Vm
(20)
IV. S IMULATION AND E XPERIMENTAL R ESULTS The proposed single-input/dual-output matrix converter was preliminary verified in simulation using Matlab/Simulink and the PLECS power electronic libraries. Simulation was planned such that it used the same parameters as the final implemented hardware, whose values are listed in Table III. The experimental load resistances are slightly reduced to cover the inductor losses and switch conduction losses. For comprehensiveness, both CF and DF modes were tested using the carrier-based modulation scheme shown in Fig. 11. Experimentally, the scheme was im-
Fig. 14. Simulation results in CF mode showing modulating references per phase, upper and lower three-phase output currents from top to bottom.
plemented using a combination of dSPACE DS1103 controller card and Xilinx Vertex-II Pro XC2VP30 FPGA evaluation card (FPGA stands for field programmable gate array). The dSPACE card was tasked to synchronize with the three-phase input voltages, and identify the sextant in which the reference CSR phasor was residing. This information was passed on to the Xilinx card, whose external oscillator frequency of 100 MHz was adequate for creating the 5-kHz variable-slope triangular carrier and the final driving signals for the overall matrix converter. A point to note with the experimental setup is that it can be simplified to lower cost. One possible suggestion is to replace the expensive dSPACE card with a lower end 8-bit processor. External logic device is necessary, but rather than FPGA, the cheaper erasable or complex programmable logic devices (EPLD or CPLD) can be used in place. In spite of the options available, the setup assembled here is still considered as the most flexible for rapid high-end control verification, which indeed is the follow-up attempt, after verifying topological and modulation thoughts in this paper. A. CF Mode Figs. 13 and 14 show simulation results obtained under CF mode, during which the upper and lower modulating references
LIU et al.: COMPACT THREE-PHASE SINGLE-INPUT/DUAL-OUTPUT MATRIX CONVERTER
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Fig. 15. Experimental results in CF mode showing input phase voltage, input filtered and unfiltered currents from top to bottom.
Fig. 16. Experimental results in CF mode showing fictitious dc-link voltage and current from top to bottom.
are set indifferently to 50 Hz, while their modulation indices are set to 0.8. The observed input currents in Fig. 13 are undeniably three-phase sinusoidal with an amplitude of 3 A. The fictitious dc-link voltage and current are also observed to vary according to expectation with six pulses per fundamental cycle for the six different sextants (note the difference in time scale between the ac and dc plots in Fig. 13). Fig. 14 follows to show the modified modulating references per phase, sinusoidal upper and lower output currents with peak amplitudes of 3.1 A and 1.6 A, respectively. The second output current is approximately half of the first, which certainly is correct, since the upper and lower modulation indices were set to the same value of 0.8, while the second load was configured to be twice bigger than the first in terms of impedance value. Figs. 15, 16, and 17 show the corresponding experimental results under CF mode with Fig. 15 showing the in-phase input phase voltage and unfiltered current. It is certainly the unity input power factor but no longer so when the filtered input current is considered. The slight phase lead of the filtered input current, when measured with reference to the fundamental component of the unfiltered current, is contributed by the second-order input filter, which has long been associated with
Fig. 17. Experimental results in CF mode showing (a) output line voltage and current of upper terminal, (b) output line voltage and current of lower terminal, and (c) output currents of both terminals.
existing matrix converters. Fig. 16 next shows the experimental fictitious dc-link voltage and current over half a fundamental cycle while Fig. 17 shows the line voltages and currents of the dual VSI outputs with the same current peaks of 3.1 A and 1.6 A observed. In Fig. 17(c), the output currents are redrawn in one plot to show their phase and amplitude relations. The same phase
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Fig. 18. Simulation results in DF mode showing three-phase input currents.
Fig. 19. Simulation results in DF mode showing modulating references per phase, upper and lower three-phase output currents from top to bottom.
Fig. 20. Experimental results in DF mode showing input phase voltage, filtered and unfiltered input currents from top to bottom.
relation is also applicable to the two fundamental output voltages, since the same resistive to inductive load ratio is maintained at both output terminals (see Table III). The second load is, however, twice bigger in impedance values, which when multiplied with its current, would lead to both fundamental output voltages having the same amplitude. B. DF Mode Testing was performed next under DF mode with the upper and lower modulating references set to 50 Hz and 100 Hz at the same modulation index of 0.5. The sum of modulation indices is then at its maximum of unity to avoid reference crossover, while yet utilizing the fictitious dc-link fully. With these parameters introduced, Fig. 18 again shows that the input
Fig. 21. Experimental results in DF mode showing (a) output line voltage and current of upper terminal, (b) output line voltage and current of lower terminal, and (c) output currents of both terminals.
currents are three-phase sinusoidal with an amplitude of 1.4 A. Fig. 19 shows the modified modulating references per phase, three-phase sinusoidal upper and lower output currents with amplitudes of 2 A and 0.9 A, respectively. These results agree well with theories and lead to confidence with the experimental testing, whose results are shown in Figs. 20 and 21. Features noted from these experimental figures are in agreement with those discussed in Section IV-A, except that the outputs here
LIU et al.: COMPACT THREE-PHASE SINGLE-INPUT/DUAL-OUTPUT MATRIX CONVERTER
have different frequencies and lower amplitudes, which are caused by the imposed limit on modulation indices. DF mode of operation is thus also proven.
V. C ONCLUSION This paper presents a compact three-phase single-input/ dual-output matrix converter, whose implementation uses only 12 switches, if only unidirectional power flow is demanded. The converter can be controlled by a variable-slope carrier modulation scheme, whose mathematical formulation has proven sinusoidal input and outputs. Other features like unity input power factor and minimum commutation count are also achievable and have already been proven in simulation and experimentally for both CF and DF modes. R EFERENCES [1] S. Kim, S. K. Sul, and T. A. Lipo, “AC/AC power conversion based on matrix converter topology with unidirectional switches,” IEEE Trans. Ind. Appl., vol. 36, no. 1, pp. 139–145, Jan./Feb. 2000. [2] Y. D. Yoon and S. K. Sul, “Carrier-based modulation technique for matrix converter,” IEEE Trans. Power Electron., vol. 21, no. 6, pp. 1691–1703, Nov. 2006. [3] B. Wang and G. Venkataramanan, “A carrier-based PWM algorithm for indirect matrix converters,” in Proc. IEEE-PESC, 2006, pp. 2780–2787. [4] L. Wei and T. A. Lipo, “A novel matrix converter topology with simple commutation,” in Conf. Rec. IEEE-IAS Annu. Meeting, 2001, pp. 1749–1754. [5] S. L. Arevalo, P. Zanchetta, P. W. Wheeler, A. Trentin, and L. Empringham, “Control and implementation of a matrix-converterbased AC ground power-supply unit for aircraft servicing,” IEEE Trans. Ind. Electron., vol. 57, no. 6, pp. 2076–2084, Jun. 2010. [6] C. Klumpner, F. Blaabjerg, I. Boldea, and P. Nielsen, “New modulation method for matrix converters,” IEEE Trans. Ind. Appl., vol. 42, no. 3, pp. 797–806, May 2006. [7] P. Wheeler, J. Rodriguez, J. Clare, L. Empringham, and A. Weinstein, “Matrix converters: A technology review,” IEEE Trans. Ind. Electron., vol. 49, no. 2, pp. 276–288, Apr. 2002. [8] A. Jahangiri, A. Radan, and M. Haghshenas, “Synchronous control of indirect matrix converter for three-phase power conditioner,” Elect. Power Syst. Res., vol. 80, no. 7, pp. 857–868, Jul. 2010. [9] P. M. Garcia-Vite, F. Mancilla-David, and J. M. Ramirez, “A dynamic voltage restorer based on vector-switching matrix converters,” in Proc. IEEE Int. Conf. Ind. Technol., 2010, pp. 637–642. [10] H. Hojabri, H. Mokhtari, and L. Chang, “A generalized technique of modeling, analysis, and control of a matrix converter using SVD,” IEEE Trans. Ind. Electron., vol. 58, no. 3, pp. 949–959, Mar. 2011. [11] H. M. Nguyen, H. H. Lee, and T. W. Chun, “Input power factor compensation algorithms using a new direct-SVM method for matrix converter,” IEEE Trans. Ind. Electron., vol. 58, no. 1, pp. 232–243, Jan. 2011. [12] E. Reyes, R. Pena, R. Cardenas, J. Clare, and P. Wheeler, “A control scheme for two doubly fed induction machines fed by indirect matrix converter,” in Proc. IEEE ICIT, 2010, pp. 631–636. [13] C. Liu, B. Wu, N. Zargari, and D. Xu, “A novel three-phase three leg AC/AC converter using nine IGBTs,” IEEE Trans. Power Electron., vol. 24, no. 5, pp. 1151–1160, May 2009. [14] C. Liu, B. Wu, N. R. Zargari, and D. Xu, “A novel nine-switch PWM rectifier-inverter topology for three-phase UPS applications,” in Proc. IEEE-EPE, 2007, pp. 1–10. [15] S. M. Dehghan, M. Mohamadian, and A. Yazdian, “Hybrid electric vehicle based on bidirectional Z-source nine-switch inverter,” IEEE Trans. Veh. Technol., vol. 59, no. 6, pp. 2641–2653, Jul. 2010. [16] S. M. Dehghan, M. Mohamadian, A. Yazdian, and F. Ashrafzadeh, “A dual-input-dual-output Z-source inverter,” IEEE Trans. Power Electron., vol. 25, no. 2, pp. 360–368, Feb. 2010. [17] L. Huber and D. Borojevic, “Space vector modulated three-phase to threephase matrix converter with input power factor correction,” IEEE Trans. Ind. Appl., vol. 31, no. 6, pp. 1234–1246, Nov. 1995.
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[18] L. Helle, K. B. Larsen, A. H. Jorgensen, S. Munk-Nielsen, and F. Blaabjerg, “Evaluation of modulation schemes for three-phase to three phase matrix converters,” IEEE Trans. Ind. Electron., vol. 51, no. 1, pp. 158–171, Feb. 2004. [19] R. K. Gupta, A. Somani, K. K. Mohapatra, and N. Mohan, “Space vector PWM for a direct matrix converter based open-end winding AC drives with enhanced capabilities,” in Proc. IEEE APEC, 2010, pp. 901–908. [20] P. C. Loh, F. Blaabjerg, F. Gao, A. Baby, and D. A. C. Tan, “Pulsewidth modulation of neutral-point-clamped indirect matrix converter,” IEEE Trans. Ind. Appl., vol. 44, no. 6, pp. 1805–1814, Nov. 2008.
Xiong Liu (S’09) received the B.E. and M.Sc. degrees in electrical engineering from Huazhong University of Science and Technology, Wuhan, China, in 2006 and 2008, respectively, and is currently working toward the Ph.D. degree in the Department of Power Engineering, Nanyang Technological University, Singapore. From July to November 2008, he was working as a Software Engineer in ShenZhen NanRui Technologies Corporation, ShenZhen, China. His current research interests include power converter topology and control and power electronics interfaces for renewable sources in microgrid and smart grid.
Peng Wang (M’00) received the B.Sc. degree from Xian Jiaotong University, Xian, China, in 1978, the M.Sc. degree from Taiyuan University of Technology, Taiyuan, China, in 1987, and the M.Sc. and Ph.D. degrees from the University of Saskatchewan, Saskatoon, Canada, in 1995 and 1998, respectively. Currently, he is an Associate Professor of the School of Electrical and Electronic Engineering at Nanyang Technology University, Singapore.
Poh Chiang Loh (S’01–M’04) received the B.Eng. (with honors) and M.Eng. degrees in electrical engineering from the National University of Singapore, Singapore, in 1998 and 2000, respectively, and the Ph.D. degree from Monash University, Clayton, Australia, in 2002. From 2003 to 2009, he was an Assistant Professor with Nanyang Technological University, Singapore, where since 2009, he has been an Associate Professor with the School of Electrical and Electronic Engineering. Dr. Loh was the recipient of two third paper prizes from the IEEE Industry Applications Society Industrial Power Converter Committee Prizes in 2003 and 2006. He is currently serving as an Associate Editor of the IEEE Transactions on Power Electronics.
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 59, NO. 1, JANUARY 2012
Frede Blaabjerg (S’86–M’88–SM’97–F’03) received the M.Sc. degree in electrical engineering from Aalborg University, Aalborg, Denmark, in 1987 and the Ph.D. degree from the Institute of Energy Technology, Aalborg University, in 1995. From 1987 to 1988, he was with ABB-Scandia, Randers, Denmark. In 1992, he became an Assistant Professor with Aalborg University, where in 1996, he became an Associate Professor and, in 1998, a Full Professor of power electronics and drives. In the period of 2006 to 2010, he was the Dean of the Faculty of Engineering, Science and Medicine at Aalborg University. During the last years, he has held a number of Chairman positions in research policy and research funding bodies in Denmark. In 2007, he was appointed to the board of the Danish High Technology Foundation. He is the author or coauthor of more than 600 publications in his research fields, including the book Control in Power Electronics (Eds. M. P. Kazmierkowski, R. Krishnan, F. Blaabjerg) (Academic Press, 2002). His research areas are in power electronics, static power converters, ac drives, switched reluctance drives, modeling, characterization of power semiconductor devices and simulation, power quality, wind turbines, custom power systems and green power inverter. Dr. Blaabjerg has been an Associate Editor of the IEEE T RANSACTIONS ON I NDUSTRY APPLICATIONS, IEEE T RANSACTIONS ON P OWER E LECTRON ICS , Journal of Power Electronics, and of the Danish journal Elteknik. In 2006, he was the Editor-in-Chief of the IEEE Transactions on Power Electronics. He was the recipient of the 1995 Angelos Award for his contribution in modulation technique and control of electric drives and an Annual Teacher prize from Aalborg University in 1995. In 1998, he was the recipient of the Outstanding Young Power Electronics Engineer Award from the IEEE Power Electronics Society. He was also the recipient of nine IEEE Prize Paper Awards during the last ten years, the C. Y. O’Connor Fellowship in 2002 from Perth, Australia, the Statoil Prize in 2003 for his contributions in power electronics, and the Grundfos Prize in 2004 for his contributions in power electronics and drives. From 2005 to 2007, he was a Distinguished Lecturer for the IEEE Power Electronics Society. He then was a Distinguished Lecturer for the IEEE Industry Applications Society from 2010 to 2011.
