A Model-based Embedded Control Hardware ...

A Model-based Embedded Control Hardware/Software Co-design Approach for Optimized Sensor Selection of Industrial Systems Kyriakos M. Deliparaschos, Konstantinos Michail, Spyros G. Tzafestas, Argyrios C. Zolotas

23rd Mediterranean Conference on Control and Automation (MED 2015) Torremolinos – SPAIN, 16 – 19 June 2015

Contents •

Introduction and proposed framework

•

Electromagnetic suspension (EMS) test case

•

FIL and FPGA architecture of LQG controller

•

Results

•

Conclusions 2

A model-based embedded control hardware/software co-design approach for optimized sensor selection of industrial systems

Hardware-in-the-loop (HIL)

Kyriakos M. Deliparaschos1 , Konstantinos Michail2 , Spyros G. Tzafestas3 , Argyrios C. Zolotas4 Abstract— In this work, a Field Programmable Gate Array (FPGA)-based embedded software platform coupled with a • plant, HIL widely in developing/testing software-based formingused a Hardware-In-the-Loop (HIL), is used to validate a systematic sensor selection complex real-time controlframework. systems The systematic sensor selection framework combines multi-objective optimization, Linear-Quadratic-Gaussian (LQG) control, and Simulation modelsuspension. of the plant is physical part of the nonlinear• model of a maglev The process that represents the suspension plant is realized in the test platform a high-level system modeling environment, while the LQG controller is implemented on an FPGA. FPGAs allow to • Model-based control hw/sw rapidly evaluate algorithms and embedded test designs under real-world scenarios avoiding heavy time penalty associated with Hardware co-design approach is followed Description Language (HDL) simulators. Moreover, the HIL technique implemented shows a significant speed-up in the • System required execution time when compared theform, software-based is realized in to soft i.e., model. using a high-level language (e.g., Index Terms— Sensor selection, embedded control, FPGA MATLAB/Simulink) design, maglev, electromagnetic suspension, observer-based controller, Hardware-In-the-Loop, FPGA-In-the-Loop.

In embedded control system: the I. of I NTRODUCTION model the plant (realized on sw) interfaces with the actual A vast majority of control systems today controller are embedded (implemented on hw) via a in a sense that they rely on built in special purpose digital communication hardware to close their feedback link loops. Embedded control •

systems are widely used in industrial control, transportation systems, robotics, automotive engineering, and many others. These type of systems interface with the external environment (i.e., sensors and actuators), are real-time critical (i.e., embedded control algorithm must execute in synchrony with the physical system under control, to guarantee performance and safety), and allow for distributed control (i.e., network of embedded controllers). A model-based embedded control software/hardware co-design approach is followed in this

complex real-time control systems by effectively adding the complexity of the plant under control to the test platform [1], [2]. The model of the system is realized in a soft form and usually modeled using a high-level language (e.g., MATLAB) or a graphical model-based design tool (e.g., Simulink). An embedded control system is illustrated in Fig. 1, where the model of the plant (realized on software) interfaces with the actual controller (implemented on hardware) via a communication link. Physical process Software-based plant model

Fig. 1.

FPGA Communication protocol (Ethernet link)

Hardware-based controller

A simplified diagram of an embedded control system.

A typical high integrity system requires both control and reliable operation. Optimized performance, robustness, fault tolerance, and low complexity are the main goals of the designer. Industrial plants require a set of sensor nodes for acquiring measurements of the system. Part of this work is focused on minimizing the number of sensors selected from a large set such that the system is (i) stable, and (ii) 3 satisfies a number of closed-loop performance criteria. The task of sensor set selection in an optimized manner for control design is a non-trivial task to do; especially if there is a large number of sensor candidates to select from. In [3], a framework for control and fault tolerance is proposed, which takes into account the aforementioned requirements for a non-trivial problem: the control of an electromagnetic suspension (EMS) for a maglev train [4].

System-level design •

•

•

Control design Disturbances Uncertainties

Maintain performance in an integrated framework

System

Even if sensors/ actuators given, which may be the “better” set for the above?

Faults

4

Non-linearities Inherently Unstable

Faults

Electromagnetic suspension test case •

EMS serves two purposes:

Controller

Track

K Flux circulation

•

•

Supports the vehicle and passengers

Pole Airgap

Electromagnet

Driving Signal

Current Power Amplifier

Ensures proper ride quality

5

F Mg

Vert. Accleration Vert. Velocity

Suspended mass (m)

onal Symposium on Speed-up, Safety and Service Technology for Railway and Maglev Systems 2009 (STECH’09) 6-19 Niigata JAPAN

rministic Input in deterministic input to the suspension in the direction is due to the transition onto a gradient. work, the deterministic input shown in Fig. 3 is t represents a gradient of 5% at a vehicle speed 2

s , an acceleration of 0.5m / s and a jerk

.

Deterministic input to the suspension with 15m/s onto 5% track gradient

gn Requirements entally there is a trade off between the nistic (track gradient) and the stochastic response ality) of the suspension. For slow speed vehicles, ance requirements are described in [11, 12]. The e is to minimise both the vertical acceleration, prove ride quality) and the excitation of the magnets by minimizing RMS of the current ns (irms ) about the nominal point. Therefore, the ng objective functions are formally written as: (9) = irms , φ2 = &z&rms rking limitations for the MAGLEV suspension d in Table 1. The assigned constraints guarantee MAGLEV suspension is working within safety

real application the sensors add noise to the d quantities. For the MAGLEV suspension, the om sensors can be amplified by the controller and on the control signal (at the driving signal of the on). Particularly, if the controller has high gains, amplitude of the noise can become very large. 4 shows the open-loop frequency response from

Input excitations and performance specs Deterministic Fig. 4 Frequency response from u to i /( zt − z ) Table 1 MAGLEV suspension constraints Constraints Value RMS acceleration (&z&rms ) < 0.5ms-2 RMS gap variation, (( zt − z ) rms )

< 5mm

Control effort, (u rms )

< 300V(3IoRo)

Air gap deviation, (( zt − z ) p )

< 7.5mm < 300V(3IoRo) < 3s =0

Control effort, (up) Settling time, (ts) Steady state error ( ess )

Stochastic

4. SENSOR OPTIMISATION VIA LQG

In this section, the optimised sensor configurations for the MAGLEV suspension are presented. The details of the systematic for approach are discussed in [3]. The overall - aiming minimal set of sensors block diagram of the sensor optimisation via LQG is depicted in Fig. 5. Details for controlling non-linear models via linearised controllers but can be found in [13]. The overall problem is formulated into a multiobjective constraint optimisation with two objective functions in (9) minimised subject to the constraints listed in Table 1. The problem is solved for every possible sensor set and therefore a genetic algorithm [14] approach is employed [3]. The LQG controller tuning is performed according to the separation principle [15]. The first step is to tune the Linear Quadratic Regulator (LQR) and select the ‘ideal’ state feedback gains (− K r ) which represents the desired

Performance specs

6

Test inputs

Design procedure Overall control constraint violation function

•

Initialise Algorithm Select first Sensor set

Optimize closed-loop performance by using Genetic Algorithms Yes

If Ω=0 then performance requirements are satisfied. If Ω≠0 then there is some violation of control constraints

•

Select the ‘‘best’’ controller More sensor sets?

Controller selection criteria


•

No




Select the best sensor set

for final selection of controller 7

Optimized sensor selection for the EMS LQR full state

With LQG

LQR

Test

Similar response maintaining performance 8

FPGA-in-the-loop (FIL) framework for optimized sensor selection •

•

FPGA-targetted HIL technique -> FPGA-inthe-loop (FIL)

Optimised sensor selection

Physical Process (Non-linear MAGLEV suspension model)

FIL schematic for EMS

Network fabric

+ +

•

Out of all available outputs, yf , feed the best sensor set yo into the FIL-based LQG.

+ + +

LQR Software model (MAGLEV)

9

+ + +

KBE Hardware model (LQG Controller)

LQG design architecture be formed, and the number of them can be calculated from Ns = 2ns 1, where Ns is the total number of all sensor sets and ns is the total number of sensors. The • LQG controller combines a Linear Quadratic Regulator (LQR) and a Kalman-Bucy Filter (KBE), hence its tuning is based on the separation principle as described in [5]; the framework algorithm is executed in two steps i.e., (i) In the first step, the LQR controller is optimized using a GA and the Pareto-optimality between the two objective functions, (i.e., 1 = irms and 2 = z¨rms ) is found. The LQR controller state feedback gains (i.e., Klqr = [K•i Kz˙ K(zt z) KR (zt z) ]), deduce the desired closedloop response which is then selected and accounted as the ‘ideal’ 1or reference 2 3response for the next step. (ii) The KBE is tuned for every feasible sensor set in order to achieve the ‘ideal’ closed-loop response. Finally, a table is provided with the optimized sensor sets, where the selection of the ’best’ sensor set is obtained based on the overall control constraint violation function, ⌦. This means that if there is one or more control constraint violations (see Section II-B for the EMS system) they are reflected in the evaluation of ⌦. If all control constraints are 10 satisfied ⌦ = 0, otherwise its value depends on the level of the constraint(s) violation (i.e., the more pronounced the constraint violation is, the higher the value of ⌦). Figure 2 illustrates the FIL applied on the EMS where all five outputs, Yf , out of which only the Yo (i.e., the best sensor set) is fed into the FIL-based KBE.

A detailed LQG core model using explicitly scalar buses

Sensor measurements

K*u

Control input

K*u

K*u

Estimated states

3 sensor measurements (y , y , y )

current gain K*u

velocity gain K*u

airgap gain K*u

fixpt scaling K*u

(a)

Figure 2 illustrates the FIL applied on the EMS where all five outputs, Yf , out of which only the Yo (i.e., the best sensor set) is fed into the FIL-based KBE. (b) Fig. 3. (a) LQG architecture for 3 sensor measurements (y1 , y2 , y3 ), (b) Internal architecture of A3⇥3 block.

been calculated using the discrete time linear model of the EMS with a sampling rate of 10 kHz. Standard discretization procedure is followed here, hence full analysis is omitted. The design architecture of the LQG core implementation and its entity in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) are depicted in Fig. 3a and Listing 1 respectively. The internal architecture of A3⇥3 block is illustrated in Fig. 3b, while a similar design 3⇥ approach is followed for C ↵⇥3 and Klqg blocks.

be formed, and the number of them can be calculated from Ns = 2ns 1, where Ns is the total number of all sensor sets and ns is the total number of sensors. The LQG controller combines a Linear Quadratic Regulator (LQR) and a Kalman-Bucy Filter (KBE), hence its tuning is based on the separation principle as described in [5]; the framework algorithm is executed in two steps i.e., (i) In the first step, the LQR controller is optimized using a • LQG conversion from floating-point GAFig. and the Pareto-optimality between the two objective 2. Optimized sensor selection framework validation using FIL. domain to fixed-point functions, (i.e., ¨rms ) is found. 1 = irms and domain 2 = z The LQR controller state feedback gains (i.e., Klqr = R [KIV. desired closedOF THEthe LQG CONTROLLER i KzFPGA ˙ K(zt ARCHITECTURE z) K (zt z) ]), deduce • loop MathWorks HDL Coder tool used to as response which is then selected and accounted The discrete linear time-invariant KBE has the following automate and speed process the ‘ideal’ reference responseup for the the next step. state space or form, (ii) The is tuned forhigh every level feasiblesimulation sensor set in order ( KBE of translating d d x ˆ˙ (k + 1)the = A‘ideal’ x ˆ(k) +closed-loop Budc uc (k) + Kresponse. C dx ˆ(k)) lqg (y(k) tomodel achieve (3) into equivalent Register d yˆ(k) = C x ˆ(k) Finally, a table is provided with the optimized sensor sets, Transfer Level (RTL) HDL description d wherewhere the selection of the ’best’ x ˆ are the estimated states,sensor Klqg isset theis3 ⇥obtained observer (i.e., VHDL) basedgain on the overall constraint violationthatfunction, matrix ( iscontrol the number of sensors) minimizes d ⌦. This means is one or more control constraint E{[x x ˆ]Tthat [x ifx ˆthere ]} (x represents the actual states). Klqg has violations (see Section II-B for the EMS system) they are • HDL Coder limitations in handling reflected in the evaluation of ⌦. If all control constraints are multi matrices, hence:
 satisfied ⌦ =dimension 0, otherwise its value depends on the level of the 
 constraint(s) violation (i.e., the more pronounced the constraint violationLQG is, the core higher model the value using of ⌦). Detailed Figure 2 illustrates the FIL applied on the EMS where explicitly scalar buses was all five outputs, Yf , out of which only the Yo (i.e., the best to HDL translation sensor developed set) is fed into prior the FIL-based KBE. 3x3

Hardware Description Language (HDL) code generation VHDL entity of the LQG core.

LIBRARY IEEE ; USE IEEE . s t d _ l o g i c _ 1 1 6 4 . ALL ; USE IEEE . numeric_std . ALL ; ENTITY LQG IS PORT( c l k rst clk_en control_in i_input_in b_in a_in ce_out uc_d_op i_op z_dot_op gap_op igap_op ); END LQG;

: : : : : : : : : : : : :

IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT

std_logic ; std_logic ; std_logic ; s t d _ l o g i c _ v e c t o r (25 s t d _ l o g i c _ v e c t o r (31 s t d _ l o g i c _ v e c t o r (31 s t d _ l o g i c _ v e c t o r (31 std_logic ; s t d _ l o g i c _ v e c t o r (34 s t d _ l o g i c _ v e c t o r (35 s t d _ l o g i c _ v e c t o r (35 s t d _ l o g i c _ v e c t o r (34 s t d _ l o g i c _ v e c t o r (35

DOWNTO DOWNTO DOWNTO DOWNTO

0) ; 0) ; 0) ; 0) ;

sfix26_En19 sfix32_En28 sfix32_En35 sfix32_En31

DOWNTO DOWNTO DOWNTO DOWNTO DOWNTO

0) ; 0) ; 0) ; 0) ; 0)

sfix35_En27 sfix36_En24 sfix36_En23 sfix35_En23 sfix36_En23

(a)

A(3,3)

A(2,3)

In3

A(1,3)

A(3,2)

Out3

Out2

sub-block)

A(2,2)

In2

A(1,2)

A(3,1)

A(2,1)

A(1,1)

In1

The MATLAB HDL Coder tool was used in this work to automate and speed up the process of translating the high

Out1

(i.e., architecture of A

Listing 1. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

(b) Fig. 3. (a) LQG architecture for 3 sensor measurements (y1 , y2 , y3 ), (b) Internal architecture of A3⇥3 block.

11

been calculated using the discrete time linear model of the EMS with a sampling rate of 10 kHz. Standard discretization procedure is followed here, hence full analysis is omitted. The design architecture of the LQG core implementation and its entity in Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) are depicted in Fig. 3a and Listing 1 respectively. The internal architecture 3⇥3

level simulation model into an equivalent Register Transfer Level (RTL) HDL description. Due to MATLAB HDL Coder limitations in handling multi dimension matrices, a detailed LQG core model using explicitly scalar buses (see Fig. 3a and Listing 1) was developed prior to HDL translation.

utilizes a Xilinx Virtex-6 device (XC6VLX240T-1FFG1156) [14] in the 1156-pin fine-pitch Ball Grid Array (BGA) package, featuring 37, 680 slices2 and 768 special Digital Signal Processing (DSP) slices (DSP48A1). The LQG and the peripheral cores were synthesized using Xilinx Synthesis Tool (XST). • A Co-simulation model andfor the design top-down manner of [15]RTL has been followed process of the LQG controller (Fig. 4). The process initiates fixed-point Simulink model using with the model specifications and requirements, MathWorks HDL Verifier and Mentoradvances to a high level functional system model (Simulink model) andModelsim continues on simulator converting it to fixed-point prior to FPGA implementation. Co-simulation of the RTL model side-bywith the fixed-point model was •sideCompare system Simulink implemented on performed using MATLAB’s HDL verifier and Mentor’s Modelsim FPGA[16]. chipMoreover (in realthetime) using asystem on the simulator implemented cycle Simulink FPGA chipaccurate was compared in real timemodel using a cycle accurate Simulink model a FIL setup. forming a forming FIL setup

HW/SW co-design FPGA flow

A. •Quantization process Top-down method:

for the design An process algorithm in of a high system modelling environthelevel LQG controller

Model specifications

MATLAB

ment (such as MATLAB/Simulink) is represented in the floating-point domain, where mostly all variables are 64 bit allowing all operations to be performed high precision • Model specifications andin system format with large accuracy. In a digital implementation this requirements -> high level translates to an increased number of flip-flops and combinafunctional system ->that requires a tional logic and inevitably results model on a design large silicon area on the FPGA chip, large path that conversion to fixed-point critical 
 negatively affects speed, plus increased power consumption. (pre- FPGA implementation) To address the aforementioned problem, the algorithm under implementation (LQG in this work) has first undergone a conversion to the fixed-point domain and then modelled usDiscretization ing VHDL. In the fixed-point domain, a pair of Wordlength, WL and Quality Fractional range, QF is considered for each parameter of the algorithm. As a consequence as (WL,QF) is Quantization increased will give a smaller Bit-Error Rate (BER) but larger silicon area, whereas as (WL,QF) is reduced will result to increased BER and smaller silicon area. Several simulations need to run to decide on the number of bits for (WL,QF) and Implementation on FPGA the dynamic range of the parameters (MATLAB fixedpoint FPGA tool), in order to maintain a desired precision which will not compromise the overall system performance (i.e., destabilize the control loop), and maintain a low silicon area. 12 The fixed-point range for a signed number ±a in a 2’s complement form is defined by the minimum and maximum value range a signed integer number type of Quantity Integer range (QI) bits can hold. The latter is best expressed by the inequality, 2QI 1  a  2QI 1 1 and can be rewritten, 2QI

1

 a < 2QI

1

,a 2 Z

From (4) it can be easily shown that, QI|amin

(4)

log2 ( a)+

Algorithmic analysis and implementation in floating point

Testbench

Diff

Model conversion in fixed point

Algorithm Stimuli

+

-

Results RTL design

Integration with peripheral cores (Ethernet MAC, DCM)

Implementation in RTL VHDL

Co-simulation with MATLAB HDL Simulator

Testbench

Diff

Logic synthesis

Algorithm Stimuli

FPGA device configuration

Fig. 4.

Place and Route

ML605 FPGA Board

+

-

Results

Ethernet link

FPGA-in-the-Loop simulation

FPGA hardware/software co-design and implementation flow.

TABLE I O PTIMIZED SENSOR SELECTION SIMULATION RESULTS . id 1 2 3 4 5 6 7 8 9

Sensor Set LQR response ! b (zt z) z¨ i, b i, z¨ i, b, (zt z) i, b, z¨ i, b, z, ˙ z¨ i, b, (zt z), z, ˙ z¨

Deterministic response X X 7 X X X X X X X

TABLE II D ESIGN UTILIZATION SUMMARY ( THREE SENSORS , iba ( ID :7), AND ONE SENSOR , b ( ID :1)).

⌦ Logic utilization

X X 7 X X X X X X X

Slice Registers Slice LUTs Occupied Slices Bonded IOBs Block RAMB36E1 Block RAMB18E1 BUFG DSP48E1s MMCM_ADVs

Used iba (id:7) b (id:1) 2410 2,354 4012 3777 1402 1362 30 30 2 2 1 1 5 4 73 69 1 1

Available 301,440 150,720 37,680 600 416 832 32 768 12

Utilization iba (id:7) b (id:1) 1% 1% 2% 2% 3% 3% 5% 5% 1% 1% 1% 1% 15% 12% 9% 8% 8% 8%

Design utilization results

DSP48E1 0/73 1/50 27/27 14/14 8/8 23/23 DSP48E1 0/69 1/46 27/27 6/6 12/12 23/23

0.04 0.04

0.74

Slice Registers 0.04

D of available

B. Data analysis from FIL simulations 0.03 0.02

0.00 0.00

0.00 0.00

0.00 0.00

0.01 0.01

0.03

Fig. 5.

1.04 1.56

1.82 0.78

0.13 0.13

3.52 3.52

D of available

0.11 0.11

0.15 0.09

0.07 0.02

2.99 2.99

9.51 8.98

0.12 0.12

0.21 0.12

0.19 0.17

0.09 0.02

0.13 0.12

Figure 6 depicts the performance of the EMS using two sensor sets. One with single sensor 0.4 0.02 (id:1) and the the other one with three (id:7). Specifically, Fig. 6a compares the 0.2 0.01 airgap deflection error from simulation-based continuous0KBE with id:1 (top) and time0 LQG and KBE FIL-based discrete-time LQR LQG KBE LQR id:7 (bottom). The performance of the EMS is within the LUTs DSP48E1 performance objectives listed in 12Section II-B. The airgap 0.8 error magnitude between the simulation and FIL is in the 10 4 0.6 of 10 order m which is fairly small. The state estimation 8 of the LQG using id:1 is shown in Fig. 6b. All three states 0.4 6 (i, z˙ and zt z) are accurately estimated using one sensor 4 (b),0.2 which is similar to the state estimation achieved if more sensors were added, i.e., id:72 concluding that the EMS 0 0 performs adequately withLQR fewer sensors. LQG KBE LQG KBE LQR 0.6

0.15 0.15

LQG and the peripheral cores synthesized via Xilinx Synthesis Tool (XST)

LUTs 0/884 170/717 221/221 99/99 227/227 167/167 LUTs 0/696 143/529 220/220 30/30 136/136 167/167

Slices 0.8

0.11 0.10

•

Embedded Development Kit (EDK). According to the device utilization report from the Xilinx map (MAP) tool (see Table III), the LQG core module itself for id:7, occupies 265 slices, 113 slice registers, 884 slice LUTs, and 73 DSP cores (DSP48A1) and similarly for id:1, 205 slices, 111 slice registers, 696 slice LUTs, and 69 DSP48A1. A comparison of the utilized FPGA resources between three sensors, iba (id:7) and one sensor, b (id:1) LQG implementation scenarios, is depicted in Fig. 5, where one can easily see that the overall occupied area for id:1 onto the FPGA chip is significantly smaller when compared to the id:7 one. The implemented 13 design uses one Mixed Mode Clock Manager (MMCM) module [18] that produces the different clocks inside the FPGA chip. The placed and routed FPGA designs (LQG and peripheral cores) for three and one sensor implementations, achieve according to post-place and route timing report a system clock operating frequency of 34.364 ns or 29.1 MHz, and 32.819 ns or 30.5 MHz respectively. The aforementioned

Slice Reg. 0/113 77/77 0/0 0/0 0/0 36/36 Slice Reg. 0/111 75/75 0/0 0/0 0/0 36/36

0.54

FIL implemented on a Xilinx A. FPGA implementation for 2 sensor sets Virtex-6 The ML605 development resources requirements and trial and error quantization procedure are commented in this section. Table II show the board utilizing atheXilinx logic utilization for implemented integrated system on the FPGA device, for three and one sensor. The implemented Virtex-6design device mainly includes the LQG core, ethernet Medium Access Control (MAC) [17] and the clock manager modules. (XC6VLX240T-1FFG1156) The ethernet MAC core is licensed as part of the Xilinx

Slices 0/265 49/221 67/67 30/30 75/75 44/44 Slices 0/205 41/161 69/69 12/12 39/39 44/44

0.59

•

Module(iba) LQG KBE Ad Cd d Klqg LQR Module(b) LQG KBE Ad Cd d Klqg LQR

0.47

FPGA design utilization Summary for the LQG controller with current/flux/ accel and flux modules

TABLE III D ESIGN UTILIZATION SUMMARY FOR THE LQG MODULE WITH iba ( ID :7) AND b ( ID :1)

D of available

•

speeds were obtained with the map and place and route effort set to medium on Xilinx ISE 13.3.

D of available

sets found to give the same closed-loop response as with the LQR one. Some of the corresponding results from the offline framework are presented in Table I. The first column is the sensor set identification number (id), the second column is the corresponding sensor set, and the next two columns show whether the deterministic response is satisfied (X) or not (7). The ⌦ function in the last column similarly indicates whether all control constraints described in Section II-B are fulfilled (X) or not (7). The selection of the best sensor set is done based on ⌦ as described in Section III. From a close inspection on the table, one can easily identify the best sensor set selection i.e., the one with the minimum number of sensor/s which satisfies all control requirements is id:1. In this work, the FIL was implemented for id:1 (single sensor), and is compared with id:7 (three sensors). The LQG implementation flow on the FPGA for other sensor set combinations follows the same approach.

C ONCLUSIONS FPGAVI. resources comparison for id:7 and id:1.

A semi-practical modeling and validation of an embedded control system for sensor optimization on a EMS plant using the FIL concept was presented. The physical process for the EMS is modeled in a high-level MATLAB/Simulink environment and the LQG controller is implemented on an FPGA. A model-based design approach has been followed for the FIL implementation using a fusion of system modeling and hardware/software co-design. The effect of fixed-point

obtained results for the LQG implementation for two sensor sets (id:1 and id:7) were compared. The results clearly show that the LQG implementation in FIL is successful in spite of the complex quantization procedure and that the FIL approach greatly reduces simulation time when compared to the software-based model counterpart. R EFERENCES [1] R. Isermann, J. Schaffnit, and S. Sinsel, “Hardware-in-the-loop simulation for the design and testing of engine-control systems,” Control Engineering Practice, vol. 7, no. 5, pp. 643–653, 1999. [2] B. Lu, X. Wu, H. Figueroa, and A. Monti, “A low-cost real-time hardware-in-the-loop testing approach of power electronics controls,” IEEE Transactions on Industrial Electronics, vol. 54, no. 2, pp. 919– 931, 2007. [3] K. Michail, A. Zolotas, and R. M. Goodall, “Optimised configuration of sensors for fault tolerant control of an electromagnetic suspension system,” International Journal of Systems Science, vol. 43, no. 10, pp. 1785–1804, 2012. [4] K. Michail, “Optimised configuration of sensing elements for control and fault tolerance applied to an electro-magnetic suspension system,” 2009. PhD dissertation, Loughborough University, Department of Electronic and Electrical Engineering. http://hdl.handle.net/2134/5806. [5] S. Skogestad and I. Postlethwaite, Multivariable Feedback Control Analysis and Design. New York: John Wiley & Sons Ltd, 2nd Edition, 2005. [6] A. Konak, D. W. Coit, and A. E. Smith, “Multi-objective optimization using genetic algorithms: A tutorial,” Reliability Engineering and System Safety, vol. 91, no. 9, pp. 992–1007, 2006. [7] Y. Zhang and J. Jiang, “Bibliographical review on reconfigurable faulttolerant control systems,” Annual Reviews in Control, vol. 32, pp. 229– 252, 12 2008. [8] A. Forrai, Embedded Control System Design: A Model Based Approach. Springer Science & Business Media, July 2012. [9] R. Alur, D. Hristu-Varsakelis, K.-E. Arzen, W. Levine, J. Baillieul, and T. A. Henzinger, eds., Handbook of Networked and Embedded

Design speed achievement* •

29.1MHz clock operating freq (current/flux/accel)

•

30.5MHz clock operating freq (flux) •

Map and place and route effort was set to medium


 *according to post-place and route timing report on Xilinx ISE 13.3 14

obtained obtained results resultsfor forthe theLQG LQGimplementation implementationfor fortwo twosensor sensor sets sets (id:1 (id:1 and andid:7) id:7)were werecompared. compared.The Theresults resultsclearly clearlyshow show that that the the LQG LQG implementation implementationininFIL FILisissuccessful successfulininspite spite of of the the complex complex quantization quantization procedure procedure and andthat thatthe theFIL FIL approach approach greatly greatly reduces reduces simulation simulationtime timewhen whencompared compared to the software-based model counterpart. to the software-based model counterpart. R EFERENCES R EFERENCES

EMS performance Fig. 5. FPGA resources comparison for id:7 and id:1. Fig. 5. FPGA resources comparison for id:7 and id:1. x 10

4

6 4 2

•

0

Airgap error with flux and current/flux/accel

x 10

1

2

1

2

3

4

5

6

3

4

5

6

4

6 4 2 0

•

0

State estimation with flux (deterministic input)

0

(a) (a)

Current with LQR Estimated current with FIL

4 2 0

0

1

2

3

0.4

Continuous-time vs. FIL (discrete/quantized)

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Velocity with LQR Estimated velocity with FIL

0.6

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Airgap with LQR Estimated airgap with FIL

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(b)

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Fig. 6. (a) Airgap error with id : 1,(b) id : 7, (b) State estimation with id : 1.

Fig. 6. (a) Airgap error with id : 1, id : 7, (b) State estimation with id : 1.

quantization was analyzed early in the design process and the wordlength was optimized to yield a smaller implementation. quantization was analyzed early in the design process and the System level test benches were used with HDL co-simulation wordlength was optimized to yield a smaller implementation. to verify the HDL implementation, and also FIL simulation System level test benches were used with HDL co-simulation to significantly accelerate the system validation. The FIL to verify the HDL implementation, and also FIL simulation to significantly accelerate the system validation. The FIL

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Conclusions •

Embedded control system for EMS sensor optimization via FIL 

•

Matlab/Simulink hosts the physical process and LQG implemented on FPGA 

•

The design approach followed a fusion of system modeling and hw/sw co-design 

•

Economical FPGA implementation due to early quantization analysis in the design process

•

Results on two sensor set examples and illustration of FIL advances in accelerating system validation 16

A Model-based Embedded Control Hardware/Software Co-design Approach for Optimized Sensor Selection of Industrial Systems Kyriakos M. Deliparaschos, Konstantinos Michail, Spyros G. Tzafestas, Argyrios C. Zolotas

23rd Mediterranean Conference on Control and Automation (MED 2015) Torremolinos – SPAIN, 16 – 19 June 2015