A Resilient 3-D Stacked Multicore Processor Fabricated Using Die-level 3-D Integration and Backside TSV Technologies 1
K-W. Lee, 1H. Hashimoto, 1M. Onishi, 1Y. Sato, 1M. Murugesan, 1J-C Bea, 1T. Fukushima, 2T. Tanaka, 1M. Koyanagi 1 New Industry Creation Hatchery Center (NICHe), Tohoku University, Sendai, Japan 2 Department of Biomedical Engineering, Tohoku University, Sendai, Japan
[email protected], 81-22-795-4119
Abstract A highly dependable 3-D stacked multicore processor with TSV self-test and self-repair functions for highly area-efficient TSV repair has been proposed. The prototype 3-D stacked multicore processor with two layer structure is implemented using die-level 3-D integration and backside Cu TSV technologies. The basic functions of tier boundary scan and self-repair circuits via TSVs between each layer in the 3-D stacked multicore processor are successfully evaluated. X-ray computed tomography (X-ray CT) scanning technology is proposed as a nondestructive failure analysis method to characterize highdensity TSVs integration, and bump joining qualities in the 3-D stacked multicore processor. Introduction Recently, high functionality and availability of LSI becomes increasingly important. However, conventional 2D LSI has serious technical limitation of slowdown device-scaling rate, consequently, increasing chip size and global wire length, and reducing production yield. To solve these problems, a three-dimensional (3-D) integration technology is indispensable [1-7]. Many LSI chips with smaller size are vertically stacked and electrically connected by using high-density and shortlength vertical through silicon vias (TSVs). In a 3-D stacked LSI, smaller chip size improves the production yield and TSV interconnects dramatically reduce the global interconnection length and increase the wiring density. The 3-D LSI technology also allows LSI to adopt redundant or spare modules in order to improve its availability and dependability. Therefore, it will be possible to simultaneously satisfy both high functionality and high availability for realizing 3-D VLSI system with self-restoration function as shown in Fig. 1. To realize such 3-D VLSI system comprising many memories and processor layers, one of the most important matters is to enhance the stacking yield by increasing the connectivity of vertical connection between the stacked layers. To enhance the connectivity, it is indispensable to apply TSV repair circuit or redundant TSVs. Various TSV repair technologies have been proposed [8-9]. However, it has large area penalty issue due to many redundant TSVs. These technologies need huge numbers of redundant TSVs, consequently the area for redundant TSVs are much larger than that for logic gates. Therefore, it is important to reduce the number of redundant TSVs for minimizing the 978-1-4799-2407-3/14/$31.00 ©2014 IEEE
TSV area penalty with keeping its high repairability. In order to meet those requirements, we proposed a highly dependable 3-D stacked multicore processor with TSV self-test and self-repair circuits for highly area-efficient TSV repair to improve the reliability and the yield of 3-D VLSI system [10]. In this study, to evaluate the usability of highly efficient TSV repair technology, the prototype 3-D stacked multicore processor of two tiers structure is implemented using die-level 3-D integration and backside TSV technologies.
Fig. 1. 3-D VLSI system with self-restoration function
A Resilient 3-D Stacked Multicore Processor Fig. 2 shows the block diagram of highly dependable 3D stacked multicore processor with self-test and self-repair functions. To achieve high-performance and highly dependable 3-D multicore processor, several single-core processor chips are vertically stacked and electrically connected by vertical bus using TSVs.
Fig. 2. The block diagram of highly dependable 3-D stacked multicore processor with self-test and self-repair functions
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Processing core Processing core Coordinator (i)
Spare core Faults detected
Spare core
Processing core Processing core Coordinator (ii)
Swap with a spare
In the 3-D stacked multicore processor, processor cores are classified into three types – system coordinator core layer, processing core layer, and spare core layer. The system coordinator core controls the whole system – task scheduling, online hardware self-test scheduling, and selfrepair of the damaged core, etc. Processing core execute the tasks allocated by the system coordinator core. Each spare core is in a cold-standby state. When the damaged core is found in online self-test sequence, the failed core is swapped with one of the spare cores by logical ID reallocation and the system continues to execute tasks in the system as shown in Fig. 3 (failover). Fig. 4. Photograph of fabricated 2-D processor core chip with selftest and self-repair functions
Processing core Damaged core Processing core Coordinator (iii)
Fig. 3. Failover in the resilient 3-D stacked muluticore processor system. (i) shows the initial state of the system with stacked four tiers. If any fault is detected in self-test sequence (ii), the system coordinator core swaps the damaged core with a spare core to keep operations in the system (iii)
To achieve built-in self-test and self-repair circuit for TSVs in the 3-D stacked multicore processor, it is important to simplify the test and the repair method including repair algorithm and circuit, because complex one causes increasing variation of signal delay and the circuit size. The built-in self-test and self-repair circuit for TSVs consists of the test pattern and expectation generator, inter-tier boundary scan test circuit, comparator between test result and expectation, repair circuit to assign signals uniquely to TSVs. Implementation of 3-D Stacked Multicore Processor (A) Design of Processor Core Chip To implement the 3-D stacked multicore processor for highly efficient TSV repair, we designed and fabricated 2D processor core chip with self-test and self-repair functions using 90-nm CMOS technology as shown in Fig. 4. The self-reparable TSVs are implemented for the vertical system bus and the vertical bus for the stacked shared memory in the processor. Each bonding pad has quadruple TSV. Selectors, 16 signals of 20 TSVs, are adopted for the vertical system bus and the stacked shared memory in order to implement the self-repair function. Therefore, the processor chip has totally 1,920 TSVs – 960 TSVs for bonding pads, 540 TSVs for the vertical system bus, and 420 TSVs for the stacked shared memory [11].
(B) Fabrication of 3-D Stacked Multicore Processor using Die-level 3-D Integration Technology The 3-D stacked multicore processor was fabricated using the die-level 3-D integration and backside TSV technologies as shown in Fig. 5 [12-14]. At first, the processor core chip is thinned down to 200um thickness by mechanical grinding following CMP treatment. Cu/Sn bumps are formed on the chip surface in die-level. The processor chip with Cu/Sn bumps is glue-bonded temporally to a supporting wafer with the alignment mark by the high-accuracy bonder and cured in the vacuum chamber. The alignment accuracy within 2-µm is required to avoid the impact of misalignment on the subsequent backside lithography process for via formation. Then, the processor chip is thinned down to around 50-µm thickness by mechanical grinding following chemical mechanical polishing (CMP) treatment. After cleaning on the thinned surface by DI water, plasma-TEOS dielectric layer of 1-µm thickness is deposited on the backside surface as a hard mask. After the backside TSV patterning with high alignment accuracy within 2-µm, via holes of 10-µm diameter are etched from the backside of Si substrate until to exposure metal 1 layer in the processor chip using BOSCH process with SF6 and C4F8 gases. P-TEOS liner of 1-µm thickness is deposited into via holes and the bottom dielectric liner in via hole is contact-etched by dry etching using the dielectric hard mask. Barrier and seed layers of Ta/Cu are carefully deposited into via holes by sputtering. Then, Cu electroplating is used to completely fill via holes. Cu/Sn bumps are formed on by electroplating as electrodes and Cu RDL (re-distribution line) is formed by wet etching patterning. All processes to form TSVs and Cu/Sn bumps are performed in die-level. The first-layer processor chip is face-up thermomechanically bonded to Si interposer with high alignment accuracy within 2-µm and electrically connected via Cu TSVs and micro bump-joining. After open/short and simple functional test to confirm the joining quality between the processor chip and Si interposer, the stacked sample is dipped into a stripper and the supporting wafer is easily de-bonded from the chip surface by removing the glue layer using a stripper. After cleaning the chip surface
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by a cleaner, it is ensured that the second layer chip is bonded to the bottom layer chip. After the evaluation of the joining quality, the supporting wafer is de-bonded again by removing the glue layer. By repeating these processes for the other processor chip, a known-good 3-D stacked multicore processor chip is fabricated.
chip is performed using the alignment mark on the supporting wafer by a conventional mask aligner. Fig. 6(b) shows the infrared (IR) images after the backside TSV patterning, which indicates that TSV patterns on the backside are well located within metal 1 layer in the front side with the average alignment accuracy of within 2-µm. Following Si via etching from the backside of Si substrate, a dielectric layer underneath the metal 1 layer in BEOL emerge when Si via etching is completed. However, the dielectric layer is not etched by Si etching gases, and as a result, significant sidewall etching (notch) of Si occurs at the surface of the dielectric layer during Si over-etching because of accumulated positive ions. Time-modulation bias technology that periodically turns RF (radio frequency) bias on and off to control plasma ion energy is applied to minimize notch phenomenon during Si etching.
Fig. 5. Photographs of the fabricated Cu/Sn bumps and Cu RDL on the backside surface in die-level
Backside Cu TSV technology is developed for realizing low-cost die-level 3-D integration [9-10]. Via-last backside Cu TSV approach has high flexibility to commercial device chip/wafer. It also has better reliability from Cu TSV-induced stress and Cu contamination issues, when compared with via-middle Cu TSV approach. However, backside Cu TSV has some technological challenges such as alignment accuracy to metal 1 layer, notch-free Si via etching, and good electrical contact between backside Cu TSV and metal 1 layer [14]. To achieve compact-sized 3-D stacked system, the fine-sized backside TSV is designed, in which the Cu TSV of 10-µm diameter is connected to metal 1 layer of 18-µm width in BEOL passed through n+ well area of 14-µm width, as shown in Fig. 6(a).
(a) (b) Fig.6. Design rule of backside TSV (a) and IR images after the backside TSV patterning to M1 layer (b)
The TSV patterning on the backside surface of the thinned
(a)
(b)
(c) Fig.7. SEM cross-sectional images of before the optimization; liner under-etch (a), notch (b), and after the optimization (c) of backside Cu TSV formation
Fig. 7 shows the scanning electron microscopy (SEM) cross-sectional images before the optimization; liner under-etch at the bottom region in TSVs (a), notch phenomenon (b), and after the optimization (c) of backside Cu TSV formation. After the optimization, the notch is less than 100-nm at the surface of dielectric layer even after 50% Si over-etching. This value is not an serious issue to form TSV. The fine-sized backside Cu TSV of 10-µm diameter was successfully fabricated. Good electrical contact between Cu TSV and metal 1 layer is a key parameter for the 3-D IC fabrication, because TSV is an important factor to determine 3-D IC performance. As the dielectric liner at the bottom of the hole is contact-etched by dry etching, the bottom surface of metal 1 layer is exposed to atmospheric environment and easily gets oxidized. Before the formation of barrier/seed layers, thin metal oxide layer is removed by Ar back-scatter sputtering
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to confirm good electrical contact. The electrical characteristics between Cu TSV and metal 1 layer are evaluated using TSV daisy chain patterns in the chip, as shown in Fig. 8.
50-μm thickness (including 10-μm BEOL layer and 40-μm Si substrate) are bonded on Si interposer. The backside CuTSVs are good contacted to metal 1 in each layer without notching phenomenon.
(a) Conceptual structure of TSV chain (b) Contact resistance to metal layer Fig.8. Contact resistances between backside Cu TSV and metal 1 layer
Fig.10. The conceptual image of the prototype 3-D stacked multicore processor with two layer structure on Si interposer
The contact resistances between Cu TSV and metal 1 layer are approximately 6 mΩ (M1 Cu) and 150 mΩ (M1 Al), respectively. We assumed that Al layer is more easily oxidized, when compared with Cu layer. Thick Al oxide layer is difficult to remove than Cu oxide layer, and therefore, it raises concern of inducing relatively high contact resistance. TSV formation process needs to be optimized in the future to reduce the contact resistance to Al layer, although it has adequately low value for TSV application. The electrical characteristics of vertical interconnection have been evaluated using TSV and Cu/Sn bump daisy chain pattern in the chip. The resistances of a pair of Cu-TSV, Cu/Sn micro-bump are approximately 70 mΩ (M1 Cu) and 240 mΩ (M1 Al), respectively. Although the resistance to Al metal 1 layer is relatively high, the resistance values of the both cases are adequately low for high-performance 3-D ICs.
(a) (b) Fig.11. Top view (a) and SEM cross-section image (b) of the 3-D stacked multicore processor
(C) Characterization of 3-D Stacked Multicore Processor We evaluated the basic functions of tier boundary scan and self-repair circuits for TSVs through TSVs between two processor layers in the 3-D stacked multicore processor as shown in Fig. 12. The prototype 3-D stacked multicore processor is successfully implemented by dielevel 3-D integration and backside TSV technologies.
Fig. 9. Cross-sectional image (a) and the photographs of Cu/Sn bumps and Cu RDL on the backside surface
To flexibly connect different functional chips and avoid the stress effect induced by Cu TSV, Cu/Sn bumps are formed depart from Cu TSV by using redistribution metal lines (RDL). Fig. 9 shows the cross-sectional image (a) and the photographs of Cu/Sn bumps and Cu RDL (b), which are formed on the back surface of each chip in die-level. Fig. 10 shows the conceptual image of the prototype 3-D stacked multicore processor with two layer structure on Si interposer. Fig. 11 shows the top view (a) and SEM crosssectional image (b) of the fabricated 3-D stacked multicore processor, where two layers of processor core chip with
Fig.12. Measured output waveform from the 3-D stacked multicore processor
Fig. 13 shows X-ray computed tomography (CT) scanning images before the optimization (a) and after the optimization (b) of the fabrication process for the 3D
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stacked multicore processor with two-layer structure. Many numbers of Cu TSVs, RDLs, metal bumps, and BEOL interconnects are clearly seen from the 3-D stacked multicore processor. We can analyze the failures such as voids in Cu TSVs and bump joining qualities. X-ray CT scanning technology is useful method as a non-destructive 3-D failure analyzing to characterize high-density TSVs integration and metal-bump joining in 3-D stacked LSIs.
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[7] [8] (a) before optimization
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[10] (b) after optimization Fig. 13. X-ray CT-scan images before optimization (a) and after optimization (b) of the fabricated 3D stacked multicore processor with two-layer structure
Conclusions The 3-D stacked multicore processor with two layer structure is fabricated using die-level 3-D integration and backside Cu TSV technologies. The basic functions of tier boundary scan and self-repair circuits via TSVs between each layer in the 3-D stacked multicore processor are successfully evaluated. X-ray CT scanning technology is proposed as a non-destructive failure analysis method to characterize high-density TSVs integration, and bump joining qualities in the 3-D stacked multicore processor.
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Acknowledgments This research was supported by the Dependable VLSI Project of Core Research for Evolutional Science and Technology (CREST) of Japan Science and Technology Corporation (JST). References [1] M. Koyanagi, “Roadblocks in Achieving Three-Dimensional LSI,” Proc. 8th Symposium on Future Electron Devices, pp.50 – 60. 1989. [2] T. Kunio, K. Oyama, Y. Hayashi, and M. Morimoto, “Three dimensional ICs, having four stacked active device layers,”
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