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Letters A Scalable Hybrid Regulator For Down Conversion of High Input Voltage Using Low-Voltage Devices Monodeep Kar, Khondker Zakir Ahmed, and Saibal Mukhopadhyay
Abstract—This paper presents a voltage regulator topology, implemented using low-voltage devices, for converting high input voltage (>4.5 V) to low output voltages with fine-grain control (0.3 to 1 V). The topology merges a Dickson’s switched-capacitor stage with a current-mode inductive buck stage, and optimizes the frequency of operations to reduce the overall passive size. The proposed two-stage hybrid regulator, designed in 130-nm standard digital process, operates from 4.8 to 6 V at input and regulates output voltage as low as 0.3 V with a maximum output power of 90 mW and a peak efficiency of 69%. Index Terms—Cascaded converter, inductive buck (IB), multistage down converter, switched capacitor (SC).
I. INTRODUCTION NTEGRATION of voltage regulators (VR) with on-chip or on-package passives and digital processor in the same chip is an area of active research [1]. The input voltages (VIN ) of the VR is typically in the range of 4.5–12 V depending on the platform [2]–[4]. On the other hand, the digital processors operate at much lower voltages (0.3 V–1 V) requiring high conversion ratio. Dynamic and fine grain control of the output voltage is required to enable dynamic voltage scaling (DVS). Delivering high voltage directly to the chip also reduces current and power loss in an on-board power delivery network. Cascading multiple similar or dissimilar types of VRs to generate a large conversion ratio is a well-studied approach [2]–[5]. However, the challenges of on-chip integration of high input voltage VR with processor are: 1) to design a power stage with all low-voltage devices while supporting input voltages higher than the device breakdown voltage (VM AX ); 2) to provide regulated, controllable, and low output voltage; and 3) to facilitate integration, the topology must require small passives, as capacitor/inductor density available on chip or on package is smaller than what is feasible on board [1]. This letter presents a VR topology for down conversion of high input voltage using low-voltage devices. The VR, referred
I
Manuscript received June 28, 2015; revised August 8, 2015 and September 3, 2015; accepted September 4, 2015. Date of publication September 22, 2015; date of current version November 16, 2015. This work was supported by Semiconductor Research Corporation through Texas Analog Center of Excellence (#1836.110). The authors are with the ECE Department, Georgia Institute of Technology, Atlanta, GA 30332 USA (e-mail:
[email protected],
[email protected];
[email protected]). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TPEL.2015.2480424
Fig. 1.
Proposed hybrid regulator system block diagram.
to as a hybrid regulator, consists of a switched-capacitor (SC) stage at the input to generate an unregulated intermediate voltage, followed by an inductive buck (IB) regulator at the output (see Fig. 1). The design presented in this work couples careful architectural choices with innovative circuit techniques and passive optimizations. The design presented in this work couples careful architectural choices with innovative circuit techniques and passive optimizations. While each individual stage uses conventional topologies, the challenge is to select proper architectures for each stage. Towards this goal, the first key contribution is the use of a Dickson’s Switched Capacitor (SC) topology [6] at the input. In Dickson’s topology the voltage stress on devices is limited to twice the output voltage, making the design suitable for high input voltages even using low-voltage transistor. Second, to generate regulated output voltage even from the unregulated intermediate node, the superior power supply noise suppression capability of the current mode control is utilized in the IB stage. Innovative control circuits for load dependent variable frequency reduce the switching loss at lower load current under both continuous and discontinuous conduction mode (CCM/DCM) operation. A second challenge for the hybrid VR design is to provide safe start-up of the cascaded system. To address this challenge, a novel start-up circuit, also scalable with an increasing input voltage, is presented to prevent overstressing of the power devices during start-up without using any high-voltage blocking devices. The current mode topology of the IB also limits the maximum current seen by the SC when IB starts up. The third challenge is to reduce the total passive while managing the problems arising from cascading multiple stages. This work presents a high frequency SC stage to reduce the flying capacitance, which can dominate the overall passives. However, analysis is performed to show that a high-frequency SC stage in this cascaded topology may reduce output quality and lead to system failure. The intermediate node capacitor and switching frequencies of the stages can be used to control the interactions between the two stages and modulate efficiency, output ripple, and maximum current driving capabilities.
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Fig. 2. (a) Switched capacitor stage showing the switch matrix and the other circuit blocks (b) Block diagram of the current mode inductive buck regulator and, (c) operational waveform showing the error amplifier (EA) decision generation scheme.
The hybrid VR topology is verified using a test-chip in 130-nm CMOS. The test-chip down converts high (4.8–6 V) input to regulated low (0.3–1 V) output to provide a maximum of 20:1 conversion. The design uses thick-oxide (VM AX = 3.3 V) and thin-oxide (VM AX = 1.5 V) digital transistors. The IB stage demonstrates the fine-grain (∼20-mV resolution) and dynamic (600 mV/40 μS) control of the output voltage. The measured peak efficiency of the design is 69%.
II. DESIGN OF THE HYBRID CONVERTER
Fig. 3. Load-dependent current generation circuit for oscillator and slope compensation blocks. The generated current affects both the oscillator frequency and slope compensation signal linearly and affects the slope compensation circuit second order nonlinearly.
A. Design of the Switched Capacitor Stage The SC power stage is designed for a fixed conversion ratio 4:1 with ∼4 MHz of operating frequency to reduce the flying capacitors. The circuit diagram of the SC stage and the auxiliary circuits are shown in Fig. 2(a). Transistors M1 –M4 are situated in the power domain driven by the output voltage (VSC ) and hence implemented with thin-oxide devices. Transistors M5 – M9 are situated in power domains driven by the flying capacitors. The voltage difference across a flying capacitor in steady state is approximately twice the VSC , therefore these transistors are implemented using thick-oxide triple well devices. The body of the triple well NMOSs are connected to their respective sources. A voltage-controlled oscillator is used to generate the clock signals which drive the lower domain switches and VCO clock is level shifted using a ladder level shifter for driving the power FETs in upper voltage domains. An overvoltage protection circuit (similar as reported in [6]) is added across each flying capacitor to prevent overstressing. Flying capacitors and switch sizes are designed for optimal SSL (Slow Switching Limit) and FSL (Fast Switching Limit) impedance, according to the methods presented in [7]. Due to higher charge multiplier coefficient of capacitor CAX , its size is kept to twice that of CBY and CCA . At the end of the optimization, the SC stage in the present design remains in SSL dominated mode. To design the SC in a FSL dominated mode, either the switching frequency or the flying capacitor sizes have be increased. Higher switching frequency will increase driving losses, while larger flying capacitors will inhibit integration. Both of these factors force the SC stage to remain in SSL dominated mode, given sufficiently large power FETs are used as switches.
B. Design of the Inductive Buck Stage Fig. 2(b) shows the functional block diagram of the IB regulator designed with the peak current-mode pulse width modulation (PWM) topology. The inductor current is sensed at one of the fingers of the PFET (MP1 ), using source degeneration. The sensed signal is filtered, and added with the slope compensation signal (SL). The combined signal is then compared with the amplified error signal from the reference VREF and feedback VFB difference, generating error amplifier (EA) signal. The oscillator signal initiates every PWM pulse to turn MP1 ON and the EA signal decides when to turn it OFF, thus defining the duty cycle of the operation. The duty signal is combined with the current limit signal (limit the maximum inductor current) and zero current signal (prevent negative current through inductor). The reference signal (VREF ) can also be controlled externally for fine-grain control of the output voltage to support DVFS. A key innovation of the design is a load-dependent variable frequency PWM operation in both CCM and DCM modes. The transient current through MP1 is sensed, filtered, and used to generate a variable reference current for both the oscillator and the slope compensation blocks (see Fig. 3). A symmetric half-circuits based oscillator, presented in our prior work [8], receives the load-dependent reference current (along with a fixed current); the oscillator frequency changes from 1 to 5 MHz as the load current changes from 10 to 50 mA. As the average load current is used for control, the proposed approach works both in CCM and DCM mode. The IB stage can also operate in the pulse frequency modulation (PFM) mode to further reduce switching loss at very light-load conditions.
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Fig. 4. (a) SC stage startup schematic (The flying capacitor nodes can be figured out rom Fig. 2). The voltages of the flying capacitor nodes at the end of the startup phase and beginning of the switching phase are shown (adjacent to the node names) (b) Nodes C, A, X and output of comparators C1, C2, C3 during input ramp (c) Operating status of different modules of the SC at three phases during the startup.
The SC stage being fixed conversion ratio open loop, the system has only one feedback loop in the buck stage. Therefore, if stability of the IB stage is guaranteed, the system will be stable [4]. The local feedback loop of this peak current-mode IB stage is compensated with a linear slope compensation for stability above 50% duty cycle operation. The load-to-frequency loop that uses a much smaller bandwidth does not affect the transient management. C. System Startup of the Hybrid Topology The safe-startup of the hybrid topology is a major design challenge to prevent overstressing of devices in both SC and IB stages. When input voltage is zero, all the flying capacitors in SC are discharged and the power FETs are turned off using appropriate polarity of the level shifters. The start-up management circuit (Fig. 4) relies on the finite ramp rate of the input voltage. The resistors in the chain and the value of the flying capacitors determine the minimum ramp rate for which a safe startup can be performed. The input voltage is divided using a resistor divider and PMOS pass devices are used to connect the flying capacitor nodes to corresponding resistor divider nodes. The gates of the PMOS pass devices are driven by comparators, which compare the voltage difference between two nodes of the flying capacitors. Assuming all the internal nodes of the circuit including the flying capacitors are initially discharged i.e. at 0 V, the PMOS pass devices are initially turned on and the flying capacitors start charging as the input voltage ramps up. The flying capacitors are shorted to the resistor divider nodes for most of the startup period. As the RC constant of the resistor string and the flying capacitors is lower than the input ramp rate, the internal devices as well as the pass devices for startup never see the full input voltage and does not get overstressed. Whenever the voltage difference across any flying capacitor reaches its desired value, the higher node is disconnected from the resistor string by the startup comparator (Fig. 4). During the startup phase VSC is shorted to X (Fig. 2) through M3 and is also precharged through the startup network. However as mentioned later, a high value of CINT , larger than CFLY is used in this design. This causes
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Fig. 5.
Die photo and PCB of the proposed hybrid regulator.
the charging time for the bottommost capacitor (CAX ), as well as the CINT to be highest. Therefore the output of comparator C3 is used to decide the end of the startup phase that triggers the VCO to turn on. For the present design the mismatch of the flying capacitors and the intermediate capacitor causes node X and VSC to charge slower than the other nodes (one of such nodes, A and VSC shown in Fig. 6(a)). This causes the voltage difference across M5 to go as high as VIN /2. However as M5 is a 3.3 V device, this does not cause any overstress. After the startup phase, the resistor string is completely disconnected from the flying capacitor string and does not affect the regular operation of the converter. As the protection circuit sits between each flying capacitor rail, the bias current will continuously discharge the flying capacitors during startup. To prevent oscillatory output of the startup comparators, significant hysteresis is added in each of them. Lowering the input ramprate constraint can minimize the current bleeding through the resistor string. III. MEASUREMENT RESULTS The prototype chip is fabricated in 130 nm (see Fig. 5). All measurements are from packaged (LCC28) die mounted on PCB with external components. A. Component Choices for the Prototype For the designed prototype, to meet the transient performance and output ripple criteria, we have fixed the IB filter passives (1 mH, 2.2 μF) and its switching frequency range (1–5 MHz). To reduce the total flying capacitor (50 nF each, total 250 nF) of the SC, it is operated at a relatively high frequency (4 MHz). Due to the presence of a high package inductance between VSC and CINT , an onchip decap of 500 pF (COC in Fig. 2) is used. We have used an external capacitor for CINT of 1 μF (MLCC, 2.5 V rated) in this design. In section IV we perform a detail design space exploration to analyze the impact of CINT assuming the presence of better package. B. Startup Operation Fig. 6(a) shows the cold start of the system with input voltage ramping from 0 V to 5 V. The input voltage, the SC and IB output voltages and one of the flying capacitor nodes (A) are
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Fig. 6. The measured waveform for start-up and dynamic voltage scaling: (a) system level start up. The input (V IN ), switched capacitor output (V S C ) and buck output (V IB ) voltages are shown. The switching at node A indicates both the end of the startup phase and starting of the internal VCO. The IB starts up only after V S C has reached 1 V. (b) Demonstration of the dynamic voltage scaling considering a large reference step. The input (V IN ), switched capacitor output (V S C ), buck output (V IB ) and the reference voltage (V R E F ) are shown. The tracking speed of the rising edge is 600 mV/40 μS. (c) Demonstration of fine-grain dynamic control of the output. The results show 20 mV steps in the output voltage.
Fig. 7. Transient responses of the system. (a) Input step response and (b) load step response with 100-mA load change.
captured. We can see that as described in section II-D, A is precharged to its desired value at the end of input ramp. The output node (VSC ) however charges slowly and the VCO starts after it reaches 1 V. C. Dynamic Voltage Scaling with Fine-grain Control The ability of the VR to support dynamic voltage scaling with fine-grain control is demonstrated in measurement. Fig. 6(b) shows the response of the VR for a large reference step resulting in a output step from 0.3 to 0.9 V. The measurement shows that during up transition, output closely tracks the reference showing a transition speed of 15 mV/mS. During track-down, the output is allowed to reduce through the load, instead of using a separate path, resulting in longer transition time (similar to [9]). Fig. 6(c) shows that output can be changed within a 20 mV resolution. D. Load and Line Regulation Fig. 7(a) shows the intermediate and output voltage (0.3 V) of the converter when the input voltage is stepped from 4.9 to 5.9 V. The measured line regulation was 3.3%/V. Fig. 7(b) shows the response of VSC and VIB for a load step of 10 to 100 mA at 0.3 V output. The output drops by 20 mV and recovers within 10 μs, yielding a 3.3%/100-mA load regulation. E. Efficiency Measurement Fig. 8(a) shows the efficiency of the individual stages if driven with a dc load. The combined efficiency of the hybrid regulator at different conversion ratios with fixed input voltages is shown
Fig. 8. (a) Efficiency of the individual stages when tested with a dc load current. SC V IN = 4.8 V, IB V IN = 1.2 V, IB V O U T = 1 V. (b) Combined efficiency of the hybrid regulator. The efficiency higher at lower conversion ratios, while it shows peaking at 30 mA output load current at V IB for all conversion ratios.
in Fig. 8(b). The measured efficiency peaks at 69% while it provides a maximum of 31 mW output power at 1 V. The efficiency of the IB remains relatively constant at low load due to the PFM mode. The overall efficiency drops at the lower IB output voltage due to reduced load current seen by the SC. F. Comparison With Prior Works Table I shows the comparison of the measurement results from our design with experimental results of prior works. The comparison is performed only with silicon based VRs for high down-conversion. Illustrative examples from three classes of prior works were considered, namely, conventional single stage IB, multi-stage converters, and resonant SC stage. An inductive buck converting 5 V input to 1 V output (minimum) using a cascade power stage is presented in [10]. As expected, the single stage converter achieves higher efficiency than the proposed design, but requires transistors with VM AX > 0.5 VIN . Multi stage DC-DC conversion has also been investigated [2], [11]. A three level down converter, proposed in [11] uses merged capacitive and inductive stage with on-chip passives. The prototype achieves a high power density, however, is not scalable with increasing input voltage. Schaef et al. [12] has demonstrated a resonant SC topology with the use of trace inductance which helps to achieve zero current switching. The design shows good efficiency thanks to soft switching and uses low passive values.
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TABLE I COMPARISON CHART WITH PRIOR ARTS Item VI N (V) VO U T (V) Conversion Ratio (Max.) Switching Frequency (MHz) Power density (W/mm2 ) Cap/Ind (SC/IB) Topology Peak efficiency (%) Max PO U T (W) Process Effective Area
[2] JSSC’12
[10] TPE’12
[12] ISSCC’15
[11] JSSC’12
This Work
5 1 5 SC: 0.002-0.10 IB 10 0.082 SC: 44 μF (flying) Intermediate: 2 μF IB:4.7 μF /30 nH Series–Par/PWM Combined:82 (5 V to 1 V) 0.8 180 nm §9.65 mm2
2.5–5 1.0–4 5 1.3 – IB:4.7 μF /4.7 μH PWM/PFM 94 0.68 250 nm 2.7 mm2
6–3 3.7–1.85 2 50–60 0.91 24.6 nF/(1.1 nH–4.5 nH)
2.5 0.4–1.4 6 50–200 0.2 Merged: 29 nF/1 nH Three-Level Conv. 77 1 130 nm 5.0 mm2
4.4–6.0 0.3–1 20 SC: 4 IB (Variable):1–5 0.18 SC: 250 nF (Flying) Intermediate: 1 μF IB:2.2 μF /1 μH Dickson/PWM/ PFM 69 (4.8 V to 1 V) 0.09 130 nm 0.49 mm2
Resonant SC 89.1 63 180 nm 2.7 mm2
§ Whole die area. An unspecified amount of area is unutilized.
Fig. 9. Design space exploration of the hybrid regulator at varying switched capacitor frequency and intermediate node capacitance: (a) efficiency, (b) minimum V S C and (c) the IB output ripple. IB F R E Q = 4 MHz, IL O A D = 100 mA and IB output = 600 mV is used in the simulation. The simulation assumes absence of any packaging parasitics between V S C and C IN T . Note that with increasing value of SC F R E Q the total flying capacitor in the system decreases.
The key advantage of this work over [12] is the higher conversion ratio. The most similar work, presented by Robert et al. [2] uses a cascaded SC and IB stages achieving a high peak efficiency. The SC uses a much lower frequency (100 KHz) that reduces switching loss and the charge redistribution loss by making the SC stage see an inductive load. Therefore, a key advantage of the design over the proposed one is higher efficiency. However, the lower frequency requires larger flying capacitors (44 μF instead of 150nF as in the proposed design). The design used series-parallel SC, instead of Dickson SC as presented here; used conventional voltage mode buck, instead of current mode buck presented here, and did not use load aware frequency control in the buck stage. Overall, the design reported lower conversion ratio (5 X) than this work (20 X). The concept of merging a Dickson SC with a single inductor was proposed in [13], however, no prototype IC was presented. IV. DISCUSSION A. Design Space Exploration This section discusses the interactions between the individual stages depending on the choice of switching frequencies and the value of the intermediate capacitance. The relation between power efficiency, output ripple, switching frequency, flying capacitors and output capacitors of a SC are described in [7] and is used to optimize the standalone SC. The focus of this section is
to understand the effects of SC design parameters on the system characteristics. With increasing conversion ratio (higher input voltage) the flying capacitances (CFLY ) increases and dominates the total capacitance. Therefore, to facilitate integration, it is crucial to reduce flying capacitance by operating the SC at higher frequency as presented in this work; however, this comes at a cost of increased switching loss. A lower CINT reduces passive, but results in following impacts: 1) A lower CINT degrades system power efficiency: A lower CINT increases the maximum (IIN,IB,M AX ) and/or reduces the minimum (IIN,IB,M IN ) current seen by the SC, both of which reduces the power efficiency (higher IIN,IB,M AX ⇒ more conduction loss, lower IIN,IB,M IN ⇒ more switching loss). 2) A lower CINT increases output ripple: If the SC switching frequency is outside the IB loop bandwidth, the ripple at the IB output increases. Note due to the pulsating nature of the input current of IB, the peak load current seen by the SC is much larger than the average load current. Hence, VSC ripple can be very high if the SC is designed for the average load current (much higher than a standalone SC). Therefore, it is important to observe the effect of CINT on the overall system, not only on the SC. 3) A lower can lead to the system failure: Due to lower CINT , if nodes VSC /X reduce below the lower limit of the
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hysteretic comparator, the VCO of the SC will turn off (Fig. 4) forcing a system failure. This can happen: (a) during startup when the IB draws more than its peak current; (b) at peak ILOAD when the DC drop at the unregulated VSC node is maximum; and (c) during reference transient when the inductor current can be very high. The current mode control in the test-chip partly mitigates the above factors. We have simulated the hybrid topology considering varying SC frequencies (SCFREQ ) and CINT . The IB frequency and passives are kept fixed as in the test-chip. The products of CFLY and SCFREQ are kept constant to keep RREF (equivalent output impedance looking into the SC) constant. As expected, we observe that the system efficiency improves as the intermediate capacitance increases (Fig. 9(a)). For higher value of CINT the efficiency peaks around 4 MHz (IBFREQ ) and 8 MHz (2 × IBFREQ ). Next, as CINT increases, the droop in VSC decreases (Fig. 9(b)). Fig. 9(c) shows the output ripple of the system that reduces with increasing SCFREQ . The output ripple becomes insensitive to CINT at higher frequency. The above trends show that when the SC frequency is an integral multiple of the IB frequency with their edges aligned, the performance improves.
may exist. Larger intermediate capacitance help reduce these effects, but will lessen the advantages from soft charging.
B. Approaches to Improve Overall Power Efficiency The components with lower series resistance and use of better package can improve the efficiency at high load. For example, presence of bond-wires (L = 2.5nH, RL = 100 mΩ), along with high series and trace resistance of CFLY and CINT cause the overall efficiency to drop by 4%, compared to Fig. 9(a). A second consideration is matching the peak efficiency locations of IB and SC stages. For a given output load current, the SC load current depends on the conversion ratio of the IB stage. The peak efficiency point of the IB stage will not always be aligned with the peak efficiency point of the SC stage. A SC with load insensitive efficiency curve, therefore, is crucial to enhance system efficiency. Soft charging proposed in [2], [13], [14] can be adopted to improve efficiency. Soft charging requires a constant current source load at the SC output allowing a sudden voltage change across it during phase transition in the SC. Soft charging helps reduce the SSL resistance of the SC without much increase in the switching frequency. Pilawa et al. [2] uses a cascaded IB stage to achieve soft charging whereas the work presented in [13], [14] uses an inductor at the SC output to achieve the same. However, careful considerations will be required for soft charging in a integrated hybrid VR with multiple IB outputs. Although the large ripple at VSC improves the flying capacitance utilization, the voltage stress at bottommost four switches (M1 to M4 ) should be carefully managed. The instantaneous large droop at the intermediate node can cause VSC to collapse as the driving signals of M1 to M4 are also derived from VSC . When multiple IBs are powered from the intermediate node cross-regulation
V. CONCLUSION This paper demonstrates a hybrid power converter topology for down conversion from high voltage using low-voltage transistors. A Dickson’s SC 4:1 topology and a novel voltage stress management circuit enable operation from high input voltage with standard CMOS devices. The inductive buck at the output stage, realized using low-voltage digital transistors, enables output regulation. The key advantage of the design is that the scalable topology is capable of achieving very high conversion ratio, sustains input voltage much larger than VM AX eliminating the need for specialized power devices, provides fine-grain dynamically controllable output, and reduces the passive requirements. REFERENCES [1] N. Sturcken et al., “A switched-inductor integrated voltage regulator with nonlinear feedback and network-on-chip load in 45 nm SOI,” IEEE J. Solid State Circuits, vol. 47, no. 8, pp. 1935–1945, Aug. 2012. [2] R. C. N. Pilawa-Podgurski et al., “Merged two-stage power converter with soft charging switched-capacitor stage in 180 nm CMOS,” IEEE J. Solid State Circuits, vol. 47, no. 7, pp. 1557–1567, Jul. 2012. [3] J. Wei et al., “Two-stage voltage regulator for laptop computer CPUs and the corresponding advanced control schemes to improve lightload performance,” in Proc. IEEE Appl. Power Electron. Conf., 2004, pp. 1294–1300. [4] J. Sun et al., “High power density, high efficiency system two-stage power architecture for laptop computers,” in Proc. Power Electron. Spec. Conf., 2006, pp. 1–7. [5] M. Saad et al., “Design of integrated POL DC-DC converters based on two-stage architectures,” in Proc. IEEE Appl. Power Electron. Conf., 2013, pp. 2098–2105. [6] V. Ng et al., “A 92%-efficiency wide-input-voltage-range switchedcapacitor DC-DC converter,” in Proc. IEEE Int. Solid State Circuits Conf., 2012, pp. 282–284. [7] M. D. Seeman and S. R. Sanders, “Analysis and optimization of switched capacitor DC-DC converters,” IEEE Trans. Power Electron, 2006. [8] K. Z. Ahmed et al., “A wide conversion ratio, extended input 3.5 μA Boost regulator with 82% efficiency for low voltage energy harvesting,” IEEE Trans. Power Electron., vol. 29, no. 9, pp. 4776–4786, Sep. 2014. [9] E. A. Burton et al., “FIVR—Fully integrated voltage regulators on 4th generation Intel CoreT M SoCs,” in Proc. IEEE Appl. Power Electron. Conf., 2014, pp. 432–439. [10] H. Nam et al., “5-V buck converter using 3.3-V standard CMOS process with adaptive power transistor driver increasing efficiency and maximum load capacity,” IEEE Trans. Power Electron., vol. 27, no. 1, pp. 463–471, Jan. 2012 [11] W. Kim et al., “A fully-integrated 3-Level DC-DC converter for nanosecond-scale DVFS,” IEEE J. Solid State Circuits, vol. 47, no. 1, pp. 206–219, Jan. 2012. [12] C. Schaef et al., “20.2 A variable-conversion-ratio 3-phase resonant switched capacitor converter with 85% efficiency at 0.91W/mm2 using 1.1nH PCB-trace inductors,” J. Solid State Circuits, 2015. [13] Y. Lei et al., “Split-phase control: Achieving complete soft-charging operation of a Dickson switched-capacitor converter,” IEEE Trans. Power Electron., to be published. [14] Y. Lei et al., “Soft-charging operation of switched-capacitor DC-DC converters with an inductive load,” in Proc. IEEE Appl. Power Electron. Conf. Expo., 2014, pp. 2112–2119.
