A Space Vector PWM Method for Three-Level Voltage ... - IEEE Xplore

A Space Vector PWM Method for Three-Level Voltage Source Inverters P.F. Seixas, M.A.Severo Mendes, P.Donoso-Garcia Dept. of Electronics Engineering, Federal University of Minas Gerais AV. AntBnio Carlos, 6627,31270-901Belo Horizonte, MG, Brazil Email: pau1osOcpdee.ufmg.br

A.M.N. Lima Dept. of Electrical Engineering, Federal University of Paraiba Caixa Postal 10105,58109-970Campina Grande, PB, Brazil

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Abstract-In this paper, a space vector PWM method for three-level inverters is presented. In the proposed technique, boundary restrictions can be easily incorporated t o minimize the harmonic distortion output voltages, t o limit the minimum pulse width and t o balance the voltages of the dc-link capacitor bank. The solutions obtained are simple algebraic equations relating directly the pulse widths of the gate signals to t h e phase reference voltages. Computer simulation results are used to demonstrate the main features of the proposed technique.

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I. INTRODUCTION The recent developments of the power electronics industry resulted in a considerable increase of the power that can be manipulated by semiconductor devices. In spite of that, the maximum voltage supported by these devices remains the major obstacle in medium and high voltage applications. For such applications multilevel converters have been proposed [6], [7], [3]. Multilevel inverters present lower harmonic distortion of the output voltages when compared t o standard two-level inverters oper, [3], [l],[8]. ating at the same switching frequency [6], [7] Several PWM methods have been proposed for multilevel inverters [2], [5], [4]. In this paper, a space vector PWM method for threelevel inverters is presented. In the proposed technique, boundary restrictions can be easily incorporated to minimize the harmonic distortion output voltages, t o limit the minimum pulse width and to balance the voltages of the dc-link capacitor bank. The solutions obtained are simple algebraic equations relating directly the pulse widths of the gate signals to the phase reference voltages. Computer simulation results are used t o demonstrate the main features of the proposed technique.

n

Fig. 1. Simplified circuit diagram of a three-level inverter TABLE I SWITCHING STATES FOR A THREE LEVEL INVERTER

States P

0

c,

1

0

SI,

SzZ

ON OFF

ON ON

SsX OFF

ON

OFF OFF

period (T). With three different switching states for each phase the three-level inverter of Fig. 1 has 27 possible switching states. 1 =a

.

~

11. THETHREE-LEVEL INVERTER Fig. 1 shows the simplified circuit diagram of a threelevel GTO inverter. Each phase has four GTO switches, four freewheeling diodes and two clamping diodes connected t o the dc-link center tap. Table I shows the possible switching states for a given inverter phase. The variable c,, (x E { a , b,c}), may be 1, 0 or -1 connecting the charge t o points P, 0 or N, respectively. Fig. 2 shows a typical control signal for a switching 0-7803-5864-3/00/$10.00 0 2000 IEEE

Fig. 2. Control signal co for a switching period

Fig. 3 shows all the nineteen different voltage vectors generated by the inverter of Fig. 1. So, some vectors can be generated by two or three different switching states. These voltages vectors can be grouped into four different classes: Z) zero vector Vo having three switching states; S) small amplitude vectors (VI, Vq, V7, V10, V13 and V16) having two different switching states each. These small 549

vectors have amplitude egual t o E / 3 ; M) medium amplitude vectors (V3, VG,Vg, VIZ,VISand V I S )having only one switching state and amplitude egual t o 6 E / 3 and L) large amplitude vectors (VZ,v5, VS, VII, v14 and v17) having only one switching state and amplitude 2E/3 [5]. In general, in standard space vector methods only three voltage vectors corresponding t o the apexes of the triangle in which the reference voltage vector is inside are used and this reduces the harmonic content of the output voltages P I , [51.

Where C d q ( k ) is defined as the control vector of the three-level inverter in the k-th period. Then, for a given reference voltage vector v$q(k)the control vector can be determined by: n

The zero sequence component for the control vector is defined by:

1 Co(k) = g ( E a ( k )

+ ~ b ( k +) ~ c ( k ) )

(7)

It can be shown that the pulse widths rPzand rnxcan be determined by using equations (6) and (7) and the inverse dq transformation. The pulse widths are calculated by:

-

2T

rpx(k)

Ad

- rnx(k) = -

p X k )+ CO(W

(8)

In order t o determine the pulse widths for a given phase the zero sequence component Co(k) must be selected. By a suitable choice of this component it is possible to balance the DC-link capacitors voltages and t o reduce the load current ripple. IV. DETERMINING PULSE

Fig. 3. Space voltage vectors of a three-level inverter

111. BASICEQUATIONS The output phase voltage vzn(t),can be expressed in terms of the control variable c X ( t ) as , follows:

[ ] f[

-:][ ]

van ( t )

2 -1 -1 vbn(t) = -1 2 (1) vcn(t) -1 -1 CC ( t ) The average value of the output phase voltages in the k-th switching period, 6,,(k), is calculated by:

[ ] [ can

(k)

6bn(k)

%(k)

=

2 -1 -1

-1 -1

-1

WIDTHS IN SECTOR

A

In order t o simplify the study, the hexagon in Fig. 3 is divided into six sectors (A t o F). In this section, the switching patterns for sector A will be defined. These results can be easily extended for the others sectors. Fig. 4 shows a expanded view of sector A with its subregions numbered from 1 t o 4, as well, all the possible switching states for each vector.

Ea@)

-:][ :%:; ]

NNN

000

(2)

PPP

where, Ex(k) is the average value of the control signal of phase x in the k-th period. From Fig. 2 it is easy t o see that:

vo

F"

"2

Fig. 4. Space voltage vectors in sector A

A . Balancing the DC-lank capacitor voltages (3)

Some of the vector groups defined previously (Z,S,M,L) affect the balancing of the DC-link capacitor voltages [5], [2]. The Z and L vectors do not affect the neutral-point voltage at all. The S vectors have two different switching 2 vdq(k) = - (Ean(k) afibn(k) + a2acn(k)) (4) states. One of these states connects the load between 3 neutral-point and the upper capacitor terminal and the with a= ej2?r/3.Using the above equation and ( 2 ) it other connects the load t o the lower capacitor terminals. can be found that: The fig. 5a and b shows DC-link capacitor currents for the vector V4. If the load is inductive these two switching states are almost symmetrical during the switching period and then the DC-link capacitor voltages can be balanced. The M vectors also affect the neutral voltage but have Defining the average voltage vector in the k-th period, v d q ( k ) by:

+

550

only one switching state and thus the balancing cannot be provided. The Fig. 5c shows DC- link capacitor currents for the vector V18. P

P

,

i

,

__

I

I

.

i

c

T

Fig. 6. Switching patterns for the subregion A1

i :

As explained before, the balancing of the DC-link capacitor voltages is achieved if the switching states corresponding to the S vectors are equally used. With respect to Fig. 6 this is obtained if Tppo = TOONand Tpoo = TO". These restrictions also can be expressed in terms of the pulse widths, as follows:

(C)

Fig. 5. Capacitor Current: (a) vector V4 OON, (c) vector VIS - PNO

- PPO, (b) vectorV4 -

B. Switching patterns for subregion A1 The switching patterns consists in a ordered sequence of switching states corresponding to the voltage vectors of the inverter in a given region. The ordering of the vectors can minimize the number of commutations of the inverter switches. The subregion A1 contains three vectors (Vi,VI and V4) corresponding t o seven different switching states. If all switching states vectors are employed in this subregion to form the switching pattern the harmonic content of the output voltages is r e duced. Such a pattern is named complete pattem. The complete switching pattern for subregion A1 is given by /PPP/PPO/POO/OOO/OON/ONN/NNN/. Fig. 6 shows the control signals of the three phases of the inverter for this,switching pattern during two switching periods. Notice that in consecutive switching states only one switch commutation occurs. A switching pattern that does not uses all the possible switching states is called reduced pattern. The use of reduced patterns will be treated in the next section. In the first switching period the complete switching pattern is employed. In the second period the switching pattern is reversed minimizing the number of switch commutations. To reduce the load current ripple it is necessary t o split uniformly the utilization of the zero voltage vector over the switching period. With respect t o Fig. 6 this is obtained if ~T"N = Too0 and 2Tppp = TOOO. The (9) presents these restrictions expressed in terms of the pulse widths.

Using the restrictions (9) and (10) with the equation (8), a linear system is obtained:

Solving this system gives the pulse widths that define the control signals in Fig. 6 provided that the reference voltage vectors remain inside the subregion A l . The solution is given by:

and r o z ( k ) is calculated by:

A similar procedure can be employed t o determine the pulse widths for the subregions A2 to A4.

55 1

C. overmodulation region The region extern t o the hexagon of Fig.3 is usually named overmodulation region. The reference voltage vectors in this region give rise t o unrealizable pulse widths ( r z ( k ) < 0 ou ~ ~ (>k2')) when (12) are applied. In this section, an algorithm is presented to treat reference voltage vectors in the overmodulation region. In sector A, the limit of the overmodulation region is given by the condition (win - WE;, .> E ) as indicated in Fig.7. In.the PWM method proposed, the reference voltage vector of coordinates (win, wf, &,> in the overmodulation region is substituted by the voltage vector (win', v~,', wEn') with the same direction and the largest amplitude realizable by the inverter, as shown in Fig. 7.

in the modulation method, there will exist unrealizable regions in the hexagon of Fig. 3 that will distort the output voltage waveforms. In this section the PWM solution presented in the previous section is modified to take into account these limitations. The Table I1 shows the conduction times of each GTO during a pulse width modulation period. This table was constructed form analysis of Table I and Fig. 2. TABLE I1 STATESton AND t o f fOF THE INVERTER

SWITCHES

From Table 11, the minimum on/off times restrictions ), can be expressed as a function of r P x ( k )a.nd ~ ~ , ( kas follows:

M%' j

Tpz(k)

L Tmin

T n z ( k ) 2 Tmin Tpz(k)

(17)

+ Tnz(k) 5 T - Tmin

where Tmin is the minimum conduction time for any switch of the inverter. With these restrictions and equation (12) the unrealizable regions can be determined. These regions are shown by the shaded areas in Fig. 8.

+d

"5

Fig. 7. Overmodulation region

The voltage vector (win', w:~', wEn') is determined by the intersection of the line (win - WE, = E ) and the reference voltage vector (vi,, win, vEn). Expressed in d,q coordinates:

The solution t o this system equation in natural coordinates is:

v,,*' = kv;,

"1

"2

Fig. 8. Unrealizable regions for the three-level inverter considering the minimum on/off time

(15)

Where, the factor k is given by:

In words, before entering the PWM algorithm, if an overmodulation condition is detected, the phase reference voltages must be scaled by a factor k, given by (16).

D. Minimum

"0

on/off time

In the previous analysis the inverter switches were assumed t o be ideal. However, in multilevel converters the minimum on/off time must be considered to avoid turnon or turn-off failures, specially with GTO devices. Moreover, if the minimun on/off time is not took in t o account

The use of complete switching patterns has the advantage of maximizing the number of commutations in the output phase voltage waveform reducing its harmonic content. However, complete switching patterns generates very narrow control pulses that may violate the restrictions expressed in (17). To avoid this problem the sector A has been divided into fifteen subregions as shown in Fig. 9. In the subregions numbered from 1 t o 4, complete patterns are used and in the other subregions, reduced patterns, obtained by eliminating some of the switching states of the complete patterns, are employed. As an example, the reduced patterns for the subregion A5 is /PPO /PO O / 0 00/O ON/ ONN/ and the corresponding solution is given by: 552

VI. SIMULATION RESULTS

The proposed PWM method was tested in simulation with a three-level inverter supplying a three-phase RL load. The DC-link voltage is 300V and parameters of the load are R = 5R and L = 5.5mH. The frequency of the reference voltage vector was 60Hz and the switching frequency equal to 720Hz corresponding t o a frequency ratio of 12. The results were obtained at two different conditions: a)with ton/toff restrictions, Tminfixed t o 10% of the switching period and b) without ton/toff restrictions, say Tmin= 0. Fig. 10 shows the amplitude of the fundamental component of the output voltage when the modulation index (m) varies from 0 to 1. The linearity is observed up t o m = 0.57 as expected without ton/toff restrictions. Fig. 11 shows the total harmonic distortion calculated by:

(19)

v2 Fig. 9. Sector A regions considering the minimum on/off time

The shaded region shown in Fig. 9 corresponds to the unrealizable voltage vectors in this case. The reduced patterns for the other subregions and the corresponding solutions are given in the appendix A.

V. GENERALIZING THE

We can observe a increment of the distortion with the ton/toff restrictions, due to the use of reduced switching patterns. Fig. 12 shows the output lineto-line voltage for m = 0.4 and Fig. 13 shows the corresponding current vector locus. Fig. 14 shows the voltage of the upper DClink capacitor voltage.

RESULTS

The determination of the pulse widths of the switch control signals when the reference voltage vector is inside the sector A has been considered in the previous section. In this section these results are extended to the others sectors of Fig. 3. To determine the location of the reference voltage in the hexagon of Fig. 3 the reference phase voltages must be ordered. Table I11 shows the voltage ordering together with the respective vector locations.

U 3

U

0

TABLE I11 LOCATIONOF

I

Sector

I

02

04

06

modulation index - m

08

1

THE REFERENCE VOLTAGE VECTOR

Phase voltages order

I

Fig. 10. Fundamental component amplitude x modulation index ( Tmin = 0,- - - Tmin = 10%T)

-

7 6

5 -4

.-m 3

After the ordering procedure the phase voltages are referred as v;,(k), v;,(k) and w&(k), where vf,(k) > v,*,(k) > wgn(k). The overmodulation algorithm and the pulse widths are then calculated using the same expressions employed for sector A replacing vLf,(k), w:,(k), and vE,(k) by w;,(k), v;,(k) and vgn(k) respectively and similarly replacing Tpal r p b , rPc,Tna, Tnb and Tnc by Tpi, TP2, r P 3 , rnl,7,2 and 7,3 respectively.

2

;

,

02

04

06

modulation index - m

Fig. 11. SIG x modulation index ( Tmin= 0,- - - Tmin= 10%T)

-

553

08

VIII. ACKNOWLEDGEMENT The authors acknowledge the financial support provided by the ”F’unda&~ de Amparo A Pesquisa do Estado de Minas Gerais” - FAPEMIG and also by the ”Conselho Nacional de Desenvolvimento Cientifico e Tecnol6gico” CNPq

- P W M ALGORITHM IX. APPENDIX The complete algorithm for the proposed PWM method is described below. Due t o space limitations only the PWM equations without tonltof f restrictions are shown.

Time - (s)

c2

Fig. 12. Line-to-line voltage 100 V/div(f=60 Hz, m=0.4, q=12) 25

20-

;-; 15-

5

10

-.30-10. U

Algorithm 1 - Sample the phase reference voltages:

I

-15-

-20--

-36

-20

0

-10

IO

current Id - (A)

20

v:n(k), V L A k ) e vF,(k). 2 - Order the reference voltages samples, obtaining:

Wfn(k)>v,*,(k) e G n ( k ) 3 - Use table I11 t o determine the sector of the reference voltage vector. 4 - If w;,(k) - ws,(k) > E + overmodulation

30

Fig. 13. 1,(5A/div) x Id(5A/div) Current locus (charge: R=5 R L=5.5 mH)

U;,

= kw;,

.-U&, = kw& U&, = kw&

5 - If w;,(k) - w{,(k)

B

3

1 ‘0

I 0.005

0.01

0.015

0.02

Time - (s)

0.025

0.03

0.035

Fig. 14. Upper capacitor voltage - 20 V/div (E=300V)

The above results show that the proposed PWM technique has presented all the claimed features. The balancing of the DC-link capacitor voltages has been obtained and the distortion due to the on/off time restriction has been minimized. VII. CONCLUSION This paper has presented an elegant, simple and useful PWM technique for generating the control signals of the switches of a three-level inverter. The determination of pulse widths taking into account on/off time restrictions has been achieved via simple algebraic operations thus simplfying the practical implementation of the proposed modulator. The simulation results have demonstrated the validity of the proposed technique.

554

< E / 2 -+ region 1:

(21)

REFERENCES [l] Nikola Celanavic and Borojevic Dusan. A comprehensive study of neutral-point voltage balancing problem in threelevel neutral-point-clamped voltage source pwm inverters. IEEEAPEC, CD-ROM, 1999. [2] Masato Koyama, Toshiyuki Fujii, Ryohei Uchida, and Taka0 Kawabata. Space voltage vector-based new pwm method for large capacity three-level gto inverter. IEEE-IECON, 1971276, November 1992. [3] J.S. Lai and F. Peng. Multilevel converters - a new breed of power convertrs. 30th IAS - Annual Meeting, 32348-2356, October 1995. [4] Yo-Han Lee, Bum-Seok Suh, Chang-Ho Choi, and Dong-Seok Hyun. A new neutral point current control for a %level converter/inverter pair system. PESC’99, CD-ROM, 1999. [5] Yo-Han Lee, Bum-Seok Suh, and Dong-Seok Hyun. A novel pwm scheme for a threelevel voltage source inverter with gto thyristors. In IEEE hnsactions on Industry Applications, volume 32, pages 260-268, March/April 1996. [6] Akira Nabae, Isao Takahashi, and Hirofumi Akagi. A new neutral-point clamped pwm inverter. In IEEE lhnsactions on Industry Applications, volume IA-17, pages 518-523, september/october 1981. [7] Bum-Seok Suh and Dong-Seok Hyun. A new n-level high voltage inversion system. In IEEE lhnsactions on Industrial Electronics, volume 44, February 1997. [8] R. Teodorescu, F. Blaabjerg, J.K. Pedersen, E. Cengelci, S.U. Sulistijo, B.O. WOO,and P. Enjeti. Multilevel convertrs a survey. EPE’99, CD-ROM, 1999.

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