A Subthreshold CMOS Continuous-Time Bandpass Filter with Large-Signal Stability Paul M. Furth The Klipsch School of Electrical & Computer Engineering New Mexico State University, MSC 3-0 Las Cruces NM 88003, USA,
[email protected] (505)646-1659 (phone) (505)646-1435 (FAX) June 2, 1998 Abstract
Continuous-time lters implemented in subthreshold CMOS have limited operating range. When processing real acoustic stimuli, input signals exceeding this range will occasionally be encountered. We compare the response of an RLC proto-type bandpass lter based on three transconductors to that of one based on four transconductors. It is found that, in response to large slowly varying input signals, the three-transconductor design tends toward oscillation whereas the fourtransconductor design is stable. Simulation and chip measurements of a four-transconductor bandpass lter implemented in a 2-m process verify these claims. The lter measures 117 x 416 m2 , operates on 1:25V supplies, and consumes less than 20 nW when tuned to 1 kHz.
KEYWORDS: Subthreshold CMOS, Continuous-Time Filters, MultiResolution Filter Banks
1 Introduction Low-power continuous-time bandpass lters implemented in subthreshold CMOS nd application in multi-resolution lter banks [1]. To a rst1
order, multi-resolution lter banks abstract the function of the mammalian cochlea [2, 3]. These so-called cochlear lter banks have been used to extract acoustic features in discrimination tasks with some success [4]. Moreover, it has been demonstrated that feature extraction based on auditory models of speech processing yields improved recognition rates in the presence of signi cant background noise [5]. Recent research is aimed at developing a miniature, low-power, real-time robust speech recognizer for portable applications [6]. A linear lter bank representation of cochlear function approximates wavelet analysis in a scale domain that preserves good temporal resolution at high frequencies and good frequency resolution at low frequencies [13]. Silicon systems that incorporate some of the nonlinear characteristics of cochlear function is ongoing [14, 11, 15]. It is hypothesized that such systems will achieve more robust performance in the presence of acoustic variability than the linear counterpart. A number of linear continuous-time multi-resolution lter bank architectures have been proposed [2, 3]. These lter banks exploit the exponential voltage-to-current relationship characteristic of subthreshold CMOS in order to achieve multi-resolution [7, 8]. On the other hand, this same characteristic limits the useful range of operation of the lter bank. Indeed, the basic CMOS di erential pair operating in the subthreshold region has a linear transconductance range at 1% distortion of only 7:4 mV [9]. Several techniques which extend the linear range of the CMOS di erential pair have been proposed [10, 9, 11]. Nevertheless, when processing real acoustic data, such as speech [12] or certain classes of transients [4], input signals which exceed the linear range will eventually be encountered. Under these circumstances, a continuous-time lter, which is small-signal stable, can be rendered oscillatory. In order to keep input signals within the normal range of operation, diode clamping, non-linear compression, and/or adaptive gain control are variously employed. These techniques require careful design involving tradeo s between power consumption, non-linear distortion, dynamic range, and silicon area. To complement the above circuit techniques, we are interested in nding circuit structures which are robust to inputs which may be momentarily out of the operating range.
2 Filter Bank Architecture In this work, we have chosen to investigate the linear lter bank architecture proposed in [3, 13]. The design is the result of the e ective bandwidth concept and reproduces faithfully the results from hydrodynamic simulations of a onedimensional uid-mechanical model of the cochlea [16]. The model consists of a cascade of lowpass lters with taps leading to two series bandpass lters, as depicted in Fig. 1. The lters are designed with corner frequencies and quality factors that are linearly spaced on a logarithmic scale, in order to achieve multi-resolution. A mathematical description of this lter bank model is as follows:
0 Hn(s) = @
1+
1 12 n 0 s Y Q3 (n)!c (n) A @ 1s A 2 s s i=1 1 + !c(i) Q3 (n)!c (n) + !c (n)2
(1)
where n = 1; 2; : : : ; N is one of N output sections, !c(n) is the corner frequency of the lowpass lter and the bandpass lters of the nth output section, and Q (n) is the 3-dB quality factor of the two series bandpass lters of the nth output section. The four tuning parameters of this multi-resolution lter bank are the center frequency range, !c(1) - !c(N ), and the quality factor range, Q (1) - Q (N ). 3
3
3
3 Transconductance-C Bandpass Filters The transfer function of a general second-order bandpass lter has the following form: A Q3s!c HBP (s) = (2) 1 + Q3s!c + !s2c2 where A is the peak gain and other terms are de ned earlier. Continuous-time lters can be implemented using MOSFET-C, transconductance-C, or log-domain lters. The major advantage of the MOSFET-C implementation is that it can approach the dynamic-range maximum as de ned in [17]. Its chief disadvantage is the relatively narrow frequency tuning range of approximately half of octave. On the other hand, transconductance-C lters that span several decades in frequency can be easily made using MOS transistors operating in the subthreshold region. One
has the added bonus of low power and low voltage operation, since the lowest possible saturation voltage occurs in the subthreshold region [8, 18]. The major drawback of this approach is the limited linear range. Log-domain lters exploit the translinear characteristics of MOS transistors operating in the subthreshold region [19]. However, mismatch and nonlinear e ects of parasitic capacitances appears to limit the performance of these lters. More development is required before these lters can be employed in a multi-resolution lter bank. 3.1
Three-Transconductor Design
Liu [3] proposed the second-order RLC proto-type bandpass lter for use in continuous-time multi-resolution lter banks. This particular second-order section is the optimum design for low-Q, wide frequency range lters [20]. One desirable property is that the noise level in a cascade structure of RC and RLC proto-type lters increases only linearly with the number of stages. Fig. 2(a)shows the RLC proto-type bandpass lter implemented in [3]. It consists of three transconductors and two capacitors. Transconductor G behaves as a one-sided resistor. Transconductors G and G constitute a gyrator, thereby converting capacitor C into an equivalent inductance. In practice, transconductors G and G and capacitors C and C are made equal. For small input signals, the transfer function of this lter is 1
2
3
2
2
3
1
2
s GC22GG13 (3) C1 C2 C2 G1 G2 G3 + s G2 G3 + 1 Setting C = C = C and G = G the corner frequency and 3dB quality Vout (s) = Vin(s) s
2
1
factor are given by
2
2
3
!c = GC G Q = G
2
3
2
1
(4)
The peak gain A is unity. In order to study the behavior of this circuit in response to large-signal transients, it is necessary to make assumptions concerning the non-linearities
introduced by the transconductor. We assume that the transconductor exhibits a saturating characteristic, such as that shown in Fig. 3. The exact scales on the x and y axes are not important to this discussion. We de ne the transconductance, G, as the slope of the curve in Fig. 3. Qualitatively, we note that for di erential input voltages, Vdm , near zero the slope is at a maximum. On the other hand, for large values of Vdm, either positive or negative, the slope, and hence the transconductance, is greatly reduced. A transconductor that has an expansive nonlinearity, such as the CMOS inverter [1], would give the opposite response. We do not consider such a transconductor in this work. In Fig. 2(a), for transconductor G , the di erential input voltage Vdm equals Vin , Vout. For small input signals, jVin , Vout j is small. However, for large input signals, jVin , Voutj becomes large. In this case the e ective transconductance of G will be much smaller. From (4) it is clear that as G decreases, Q will increase. If we consider only white noise sources, the noise power in a bandpass circuit is proportional to Q [1, 23]. Thus, even in the absence of an input signal, the lter can be rendered oscillatory by applying a large DC input voltage. This type of circuit behavior has been observed in lter banks made using the three-transconductor design. 1
1
1
3
3.2
2 3
Four-Transconductor Design
In order to avoid the possibility of oscillations, we propose the bandpass lter structure shown in Fig. 2(b) for use in multi-resolution lter banks. The same lter topology is commonly found in di erential transconductance-C designs [22]. The proposed lter has four transconductors, instead of three, thereby increasing static power consumption, silicon area, and output noise level slightly. Assuming linear operation, the transfer function of the fourtransconductor lter is s GC22GG13 Vout (s) = (5) Vin(s) s GC12 CG23 + s GC22GG43 + 1 With C = C = C , G = G the corner frequency, 3dB quality factor, and peak gain are given by 2
1
2
2
3
!c = GC
2
Q = G G A = G G
2
3
4
(6)
1 4
The small-signal quality factor and peak gain for this architecture can be made identical to that of the three-transconductor design by setting G = G . Setting G = G further establishes this lter as an RLC proto-type. The major bene t of this bandpass lter structure is that it is found to be stable under very large input signal conditions. The di erential input voltage of transconductor G is now Vin. As with the three transconductor design, for jVinj large, transconductance G is greatly reduced. Under this condition, we note from (7) that the peak gain of the lter decreases. However, the quality factor is now independent of G and, hence, independent of the input level. 1
1
4
4
1
1
1
4 Circuit Implementation The choice of capacitor value for C and C is a tradeo between dynamic range and silicon area. As the capacitor value increases, the dynamic range increases almost linearly [1]. Similarly, the area also increases. Capacitor values are limited to less than 10 pF if a multi-channel lter bank is to t on a single piece of silicon. In this work, we chose C = C = 3.2 pF. Transconductors G , G were implemented using di erential pairs with source degeneration via double di usors [9]. A schematic of one such transconductor is shown in Fig. 4. Its linear range at 1% distortion is maximized at 29:2 mV when the width-to-length ratios of di usors M ; are chosen to be half that of the input transistors M ; . In this case, its smallsignal transconductance is [23] 1
2
1
1
2
4
34
12
G = Ib 3V
(7)
T
where Ib is the total bias current of transistors M ; , 0:7 is the substrate electro-static coupling coecient and VT 25 mV is the thermal voltage. Width-to-length ratios of transistors are given in Table 1. The input capacitance of the transconductor with double di usors can be estimated from Cin = Cg (W L + W L ) (8) 56
1
1
3
3
Table 1: Transistor Sizes (m/m) (W=L) 20/10 10/10 10/10 20/10
M; M; M; M;
12 34 56 78
where Cg is the gate capacitance per unit area, W is the width of transistor M , etc... Assuming Cg = 0:5 fF/m , Cin is computed as 0.15 pF. The input capacitance appears in parallel with capacitors C and C . For C = C = 3:2 pF, from (7) we anticipate a decrease in the center frequency in the range of 5% to 10%. The parasitic high-frequency pole of the transconductor with double diffusors occurs at the input of the NMOS current mirror. It is given by 1
2
1
1
2
1
2
!p = C (W Lgm+ W L )
(9)
7
g
7
7
8
8
where gm is the small-signal transconductance of the transistor M . In subthreshold CMOS, the transconductance is computed as 7
7
gm = IVDS
(10)
T
We note that IDS = IB =2 for M . From (7), we can rewrite the parasitic pole as !p = 32 G (11) C 7
where is the ratio of the parasitic capacitance Cg (W L + W L ) to capacitors C and C . For C = C = 3:2 pF and Cg be 0.5 fF/m , is computed as .0625. For transconductors G and G , we note from (7) that the parasitic pole will occur at a frequency 10.67 times the center frequency. The major e ects of this pole will be to introduce phase distortion at or near the center frequency and reduce the magnitude response at higher frequencies. 7
1
2
1
2
2
3
7
2
8
8
5 Simulation Results Whereas for small input signals, the three- and four-transconductor designs can be made to give virtually identical outputs, their response to large input signals is markedly di erent. In order to demonstrate this di erence, we simulated an ideal bandpass lter, the three-transconductor design and the four-transconductor design in T-SPICE. T-SPICE employs the physicallybased Maher-Mead MOSFET model, which is accurate in the subthreshold region [7]. Referring to Fig. 2, transconductors G and G are biased at 1.25 nA, while G and G are biased at 2.5 nA. Capacitors C and C are 3.2 pF. Supply voltages are 1.25V. Thus, the nominal power consumption for the three- and four-transconductor designs are 15.625 and 18.75 nW, respectively. The nominal cuto frequency is 1 kHz and quality factor is 2 for both designs. Magnitude and phase responses of the ideal bandpass lter and two real bandpass lter designs are shown in Fig. 5. Deviations from the predicted response can be attributed to the parasitic pole within the transconductor [24]. In particular we see that the peak gain of the three- and four-transconductor lters is slightly more than unity and the phase response deviates from the ideal response above the center frequency. However, qualitatively, we note that the two lters give almost the same small-signal frequency response. For a large-amplitude input waveform, the response of the two bandpass lter designs di ers markedly. To demonstrate this di erence, we chose a time-varying input signal that consists of a small-amplitude sinusoid close to the center frequency of both lters and a large-amplitude sinusoid that is approximately one decade below the center frequency. The input signal is de ned by Vin(t) = 50 sin(2 1000 t) + 450 sin(2105 t) mV (12) The input signal is shown in the top graph of Fig. 6(a). During the rst ten cycles of the 1-kHz signal, the 105-Hz component is o . Ever after, the two continue together. The response of the ideal bandpass lter to the input signal in (12) is shown in the bottom graph of Fig. 6(a). During the rst ten cycles, the input and output follow each other faithfully. When the low frequency signal is turned on, the amplitude of the 1-kHz sine wave in the output waveform is unchanged, even while it rides upon a low-amplitude 105-Hz signal. 1
2
3
4
1
2
The response of the two bandpass lter designs is shown in Fig. 6(b). During the rst 10 cycles of the 1-kHz input signal, we see that the output response is linear and virtually identical for both designs. However, as the large, low frequency component becomes active, the design based on three transconductors gives an output voltage which tends to increases in amplitude during each half cycle. Its maximum amplitude exceeds that of the ideal response. This problem is compounded in the real circuit by the presence of random noise, which is maximal at the resonant frequency [23]. On the other hand, consider the response of the lter based on the four-transconductor design. The output signal decreases in amplitude during each half cycle and thus exhibits much more stable behavior.
6 Chip Measurements We submitted for fabrication a 20-channel lter bank using the fourtransconductor design in a 2-m n-well double-poly CMOS process. The chip included a single transconductor, lowpass lter, and bandpass lter for tuning and measurement. The layout of a single second-order section with four transconductors is shown in Fig. 7. It measures 117 x 426 m . In the layout, Metal2 is used as a ground plane to reduce noise and substrate leakage. Metal2 was omitted from the gure so as not to obscure other layers. In testing the chip, a power supply of 1.25 V was used. The lowpass lter was tuned to a corner frequency of 1.0 kHz using a 50 mV sinusoid, thus establishing a nominal bias current of 2:5 nA in the transconductors. This same bias current was applied to the bandpass lter to set the center frequency, as is done in the lter bank. A quality factor of 2 was set by biasing transconductors G and G with currents half those of G and G . Thus, experimental conditions and simulation conditions matched. Input and output waveforms were measured using an HP54520A digitizing oscilloscope. Two screen images were captured and stored on disk, as shown in Fig. 8. A voltage follower internally bu ered the output signal of the bandpass lter. Once o -chip, a second bu er consisting of a unity-gain TLC2272 CMOS opamp drove the oscilloscope. In Fig. 8(a), the input is a 50-mV 1-kHz sinusoid in channel 1. The measured response in channel 2 is almost identical to the input, except for a slight decrease in amplitude and a small phase lead. 2
1
4
2
3
To measure the large-signal response of the bandpass lter, a continuous sinusoid at 1.0 kHz and 50-mV amplitude was combined with a tone burst at 105 Hz and 450-mV amplitude using an inverting and summing ampli er. The input signal is shown in the top graph of Fig. 8(b), the response is in the lower graph. The measured response of the four-transconductor bandpass lter is very similar to the simulated response in Fig. 6(b). During the cycles where only the 1 kHz signal is present, the output follows the input signal. However, when the large-amplitude 105-Hz signal turns on, the output gain is greatly reduced and the output is stable.
7 Summary and Conclusion Continuous-time bandpass lters implemented in subthreshold CMOS have a limited linear range. When dealing with real acoustic data, input signals that exceed the linear range will be encountered. In these circumstances, we desire the behavior of the circuit to change gracefully, rather than break into oscillation. An RLC proto-type lter based on three transconductors tends toward oscillations for large slowly varying input signals. In this work, we have proposed the use of a bandpass lter using four transconductors. The transfer functions and linear ranges of the two designs are nearly identical for small-signal inputs. However, in response to large input signals, the output of the three-transconductor design is shown to increase in amplitude, whereas that of the four-transconductor design is signi cantly damped. A 20-channel multi-resolution lter bank using the four-transconductor bandpass lter was built in a 2-m CMOS process. An individual bandpass lter measures 117 x 426 m . It operates from 1:25-V supplies and consumes less than 20 nW when tuned to 1 kHz. 2
Input LOWPASS
Outputs BANDPASS
BANDPASS
Out1 LOWPASS
BANDPASS
BANDPASS
Out2
LOWPASS
BANDPASS
BANDPASS
OutN
Figure 1: Filter bank architecture proposed in [3, 13].
Vout
G3+ -
Vin
+ -
G G1
+
G G2
C1
C2
(a)
Vout
G3+ -
+ -
G1
+
G4
Vin
C2
+ -
C1
G2
(b)
Figure 2: Bandpass lter architectures: (a) based on three transconductors, and (b) based on four transconductors.
Transfer Characteristics 1 0.8 0.6 0.4
Iout [nA]
0.2 0 −0.2 −0.4 −0.6 −0.8 −1 −200
−150
−100
−50
0 Vdm [mV]
50
100
150
200
Figure 3: Output current as a function of di erential input voltage for a transconductor with a saturating non-linearity.
M5
Vb
M6
M4
V1
M1
M3 M2
V2 Iout
M7
M8
Figure 4: Linearized CMOS transconductor based on the double di usor di erential pair.
Magnitude Response
0
Vout [dB]
−5
−10
−15
−20
−25 100
200
1000 Freq [Hz]
2000
10000
(a)
Phase Response 100
Vout [degrees]
50
0
−50
−100
−150 100
200
1000 Freq [Hz]
2000
10000
(b)
Figure 5: Simulated (a) magnitude and (b) phase response of ideal bandpass lter (solid), three-transconductors bandpass lter (dotted), and fourtransconducor banpdpass lter (dashed). The lters are tuned to have a corner frequency and quality factor of 1.0 kHz and 2, respectively.
Sum of Sinusoids
Input [mV]
500
0
−500 0
5
10
15
20
25
20
25
20
25
20
25
Ideal Response
Output [mV]
50 0 −50 0
5
10
15 Time [ms] (a)
Three Transconductors
Output [mV]
50 0 −50 0
5
10
15
Four Transconductors
Output [mV]
50 0 −50 0
5
10
15 Time [ms] (b)
Figure 6: (a) Input signal consisting of a sum of two sinusoids at 1kHz and 105Hz (top) and response of ideal bandpass lter (bottom), and (b) the response of the three-transconductor lter (top) and the four-transconductor lter (bottom).
Paul M. Furth received the B.S. degree in engineering from California Institute of Technology, Pasadena, CA, in 1985. From 1985 to 1989, he was a project engineer for TRW Technar, Irwindale, CA. He then received the M.S.E. and Ph.D. degrees in electrical and computer engineering from Johns Hopkins University, Baltimore, MD, in 1992 and 1996, respectively. In 1995 he joined New Mexico State University, Las Cruces NM, as an Assistant Professor of Electrical and Computer Engineering. His research interests include analog circuit design, cochlear modeling, and analog image processing.
References [1] P.M. Furth and A.G. Andreou. A design framework for low power analog lter banks. IEEE Trans. Circ. and Syst., 42(11):966{971, November 1995. [2] R.F. Lyon and C. Mead. An analog electronic cochlea. IEEE Trans. Acoust., Speech, and Signal Proc., 36(7):1119{1134, July 1988. [3] W. Liu, A.G. Andreou, and M.H. Goldstein, Jr. Voiced-speech representation by an analog silicon model of the auditory periphery. IEEE Trans. Neural Networks, 3(3):477{487, May 1992. [4] F. Pineda, K. Ryals, D. Steigerwald, and P.M. Furth. Acoustic transient processing using the Hopkins Electronic EAR. In World Congress on Neural Networks 95, volume 1, pages 136{141, Washington, DC, July 1995. [5] C. Neti. Neuromorphic speech processing for noisy environments. In IEEE Intl. Conf. on Neural Networks, pages 4425{4430, Orlando, FL, July 1994. [6] N. Kumar, W. Himmelbauer, G. Cauwenberghs, and A.G. Andreou. An analog VLSI chip with asynchronous interface for auditory feature extraction. IEEE Trans. Circuits Syst. II, 45(5):600{606, May 1998. [7] C.A. Mead. Analog VLSI and Neural Systems. Addison-Wesley, Reading, MA, 1989. [8] E.A. Vittoz. Micropower techniques. In J. Franca and Y.P. Tsividis, editors, Design of MOS VLSI Circuits for Telecommunications and Signal Processing. Prentice-Hall, 2nd edition, 1994. [9] P.M. Furth and A.G. Andreou. Linearised di erential transconductors in subthreshold CMOS. Electronics Letters, 31(7):545{547, March 30 1995. [10] L. Watts, D.A. Kern, R.F. Lyon, and C.A. Mead. Improved implementation of the silicon cochlea. IEEE J. Solid-State Circuits, 27(5):692{700, May 1992.
[11] R. Sarpeshkar, R.F. Lyon, and C.A. Mead. An analog VLSI cochlea with new transconductance ampli ers and nonlinear gain control. In ISCAS-96, volume 3, pages 292{296, Atlanta, GA, May 1996. [12] P.M. Furth, N.K. Goel, A.G. Andreou, and M.H. Goldstein, Jr. Experiments with the Hopkins Electronic EAR. In The 14th Speech Research Symposium, pages 183{189, Baltimore, MD, June 1994. [13] W. Liu, A.G. Andreou, and M.H. Goldstein, Jr. Analog cochlear model for multiresolution speech analysis. In S.J. Hanson, J.D. Cowan, and C.L. Giles, editors, Advances in Neural Information Processing Systems 5, pages 666{673. Morgan Kaufmann, San Mateo, CA, 1993. [14] N. Bhadkamkar. A variable resolution, nonlinear silicon cochlea. Technical Report CSL-TR-93-558, Stanford University, Stanford, January 1993. [15] E. Fragniere, A. van Schaik, and E. Vittoz. Design of an analogue VLSI model of an active cochlea. Integrated Circuits and Signal Processing, 13(1/2):19{35, May/June 1997. [16] J.B. Allen. Cochlear modeling. IEEE ASSP Magazine, 2(1):3{29, Jan. 1985. [17] G. Groenewold. Optimal dynamic range integrators. IEEE Trans. Circuits Syst. I, 39(8):614{627, August 1992. [18] A.G. Andreou and K.A. Boahen. Neural information processing II. In M. Ismail and T. Fiez, editors, Analog VLSI Signal and Information Processing. McGraw-Hill, 1994. [19] W. Himmelbauer and A.G. Andreou. Log-domain circuits in subthreshold CMOS. In 40th Midwest Symp. Circ. Syst., volume 1, pages 26{30, Sacramento, CA, Aug. 1997. [20] H. Nevarez-Lozano and E. Sanchez-Sinencio. Minimum parasitic e ects biquadratic OTA-C lter architectures. Analog Integrated Circuits and Signal Processing, 1(4), Dec. 1991.
[21] P.M. Furth and A.G. Andreou. Cochlear models implemented with linearized transconductors. In ISCAS-96, volume 3, pages 491{494, Atlanta GA, May 1996. [22] Y.P. Tsividis. Integrated continuous-time lter design|an overview. IEEE J. of Solid-State Circ., 29:166{176, March 1994. [23] P.M. Furth. On the Design of Optimal Continuous{Time Filter Banks in Subthreshold CMOS. PhD thesis, Johns Hopkins University, Baltimore, 1996. [24] A. Rodrguez-Vazquez, B.Linares-Barranco, J.L. Huertas, and E. Sanchez-Sinencio. On the design of voltage-controlled sinusoidal oscillators using OTAs. IEEE Trans. Circuits Syst., 37:198{210, Feb. 1990.
Figure 7: Layout of a second-order bandpass lter, consisting of four transconductors and two grounded capacitors. Metal2, which is signal ground, has been omitted to aid in viewing.
(a)
(b)
Figure 8: Screen images from HP54520A digitizing oscilloscope: (a) 1-kHz 50mV sinusoid (channel 1) lags slightly the response of the four-transconductor bandpass lter (channel 2). (b) Input signal consisting of a continuous sinusoid at 1kHz with tone bursts at 105Hz (top) and response of fourtransconductor bandpass lter (bottom). The bandpass lter was tuned to a center frequency of 1.0 kHz and quality factor of 2.
