“A Verilog Overview” A Verilog Overview - The College of New Jersey

“A A Verilog Overview Overview” by Orlando J. Hernandez, Ph.D. Electrical & Computer p Engineering g g School of Engineering THE COLLEGE OF NEW JERSEY Fall Semester, 2004

Presentation Overview

Introduction to Verilog – Part I Introduction to Verilog – Part II

Introduction to Verilog g – Part III

ALU Design

Control and Data Path Organization

AND, OR, HALF ADDER, FULL ADDER

Finite State Machines,, Digital g Filter

Q&A Sessions

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Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY

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INTRODUCTION TO Verilog PART I

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Design Automation

Need To Keep With Rapid Changes, Electronic Products Have To Be D i Designed d Extremely E t l Quickly Q i kl Electronic Design Automation (EDA)

Design Entry Simulation S th i Synthesis Design Validation & Test

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Design Automation. Cont…

D i Entry Design E t

S

R

Schematic Capture

SET

CLR

Q

Q

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Design Entry - Textual Form:

Verilog VHDL (VHSIC Hardware Description Language) VHSIC (Very High Speed Integrated Circuits)

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Design Entry - Textual Form: module and_2 (X, Y, Z); input X, X Y; output Z; assign Z = X & Y; endmodule

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Introduction To Verilog

Verilog Is an Industry Standard Language to Describe Hardware From the Abstract to Concrete Level.

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BRIEF HISTORY OF Verilog

Began as a proprietary i HDL promoted d by b Cadence C d Design Systems. Cadence transferred control of Verilog to a consortium of companies and universities known as Open Verilog International (OVI).

Verilog is an IEEE Standard (IEEE Standard 13641995).

Verilog continues to be extended and upgraded (IEEE y Verilog). g) Standard 1364-2000,, System

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MOTIVATION

Need a Method to Quickly Design, Implement, Test and Document I Increasingly i l Complex C l Digital Di it l Systems. S t Schematic and Boolean Equations Inadequate for Million-Gate ICs. Design Portability

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What is Verilog?

A Design entry language A Simulation modeling language. A Verification language. A Standard language. language As simple or complex as required.

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How is Verilog Used?

For Design Specification (“Specify”)

Specify

For Design Entry (“Capture”)

Capture

Fo Design Sim For Simulation lation (“Verify”) (“Ve if ”)

For Design Documentation (“Formalize”) ( Formalize )

Formalize

As an Alternate to Schematics

Implement

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Verify

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Design Process (e. g. for FPGAs)

Verilog Can Be Used for Both Design and Test Development Design Entry Synthesis Device Mapping

Test Development

Functional Simulation Timing Simulation

Device

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When Should Verilog Be Used?

Verilog is highly beneficial to use as a structured, top down approach to design. Verilog e og makes a es itt easy to bu build, d, use, a and d reuse libraries of circuit elements. Verilog can greatly improve your chances of moving into more advanced tools and design flows. flows

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Advantages of Verilog

The Ability to Code the Behavior and to Synthesize an Actual Circuit.

Power and Flexibility

Device (specific FPGA) Independent Design

Technology (specific silicon process) Independent p Design g

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Advantages of Verilog Cont…

Portability Among Tools and Devices

Fast Switch Level Simulations

Quick Time to Market and Low Cost

Industryy Standard

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Getting Started with Verilog

Its Easy To Get Started With Verilog, But It Can Be Difficult To Master It. To Begin With, A Subset of The Language Can Be Learned To Write U f l Models. Useful M d l Later, More Complex Features Can Be L Learned d To T Implement I l t Complex C l Circuits, Libraries, And APIs.

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A First look at Verilog

Lets start with a simple Combinational circuit: an 8 8-bit bit Comparator Comparator.

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An 8 Bit Comparator

Comparator Specifications:

Two 8-bit inputs p 1-bit Output Output p is 1 if the inputs p match or 0 if theyy differ.

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An 8 Bit Comparator Comparator A[8] EQ

B[8]

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0

1

2

3

4

5

6

7

A

1

0

1

1

0

0

1

1

B

1

0

1

1

0

0

1

1


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Comparator Verilog Source Code // Eight-bit Comparator module compare (A, B, EQ) input [7:0] A, B; output EQ; assign EQ = (A == B); endmodule

¾Define the inputs p and outputs p - the p ports of the circuit ¾Define the function of the circuit Fall Semester, 2004


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What is a module

Every Verilog design description has at least one module construct. A large design has many modules and are connected to form the complete circuit circuit. The module port declarations describe the circuit as it appears from “outside”- from perspective of its input and output interfaces.

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What is a module? module d l compare (A, (A B, B EQ) input [7:0] A, B; output EQ; : :

The module and port declarations includes a name, compare, and port direction statements defining all the inputs and outputs of the module. The Rest of the module Describes the Actual Function.

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What is a module? : :

assign EQ = (A == B); endmodule

Before the keyword endmodule is found the actual functional description of the comparator.

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Data Types

Verilog’s high level data types allow data to be represented in much the same way as in high-level programming languages. A data type is an abstract representation of stored data.

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Data Types

These data types might represent individual wires in a circuit, or a collection of wires.

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Data Types

B i Data Basic D T Types

Nets

wire, wand, tri, wor Continuously driven Gets new value when driver changes LHS of continuous assignment

tri [15:0] data; // unconditional assign data[15:0] = data_in; // conditional assign data[15:0] = enable ? data_in : 16’bz;

R i t Registers

Reg Represents storage Always stores last assigned value LHS of an assignment in a procedural block reg signal; @(posedge clock) signal = 1’b1; // possitive edge @(reset) signal = 1’b0; // event (both edges)

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Some Data Types Data Type Bit Array of bits B l Boolean Integer Real Time Register g Character String Fall Semester, 2004

Values

Examples

'1' , '0' , 'x' , 'z' Q = 1’b1; "101001" Data[5:0] = 6’b101001; U Bit Use EQ = 1’b1; 1’b1 // True T -2, -1, 0, 1, 2, 3 C = c+2; 1 0 -11.0E5 1.0, 0E5 V1 = V2/5.3; V2/5 3; ‘timescale 1ns/1ps #6 Q = 1’b1; Single g or array y of bits Use 8-bit register Use register of length 8 x the # of characters Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY

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Design Units

Design units are a concept that provide advanced configuration management capabilities. Design units are modules of Verilog that can be compiled separately and stored in a library.

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Library Design unit

A Library is a collection of commonly used modules to be used globally among different design units. Library is identified with compiler/simulator command line switches.

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Levels of Abstraction (Styles)

Verilog supports many possible styles of design description. These styles differ primarily in how closely they relate to the underlying hardware. hardware

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Levels of Abstraction (Styles)

Levels of Abstraction refers to how far your design description is from an actual hardware realization. The e tthree ee main a levels e es o of abst abstraction act o are:

Behavior Dataflow Structure

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Levels of Abstraction (Styles) Behavior

Dataflow

Structure

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Performance P f S Specification ifi i Test Benches Sequential Description State Machines Register Transfers Selected Assignments g Arithmetic Operation Boolean Equations Hierarchy Physical Information


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Behavioral Modeling

The Highest Level of Abstraction Supported in Verilog. The Behavior Approach Describes the Actual Behavior of Signals Inside the Component. Component

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Verilog Timing Issues

The Concept of Time Is the Critical Distinction Between Behavioral Descriptions and Low Level Descriptions. The Concept to Time May Be Expressed Precisely, With Actual Delays Between Related Events

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A Example An E l off Behavioral B h i l Modeling: M d li A half h lf adder dd

sum

a

carry

b

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half adder half_adder

Half Adder Inputs a, b : 1 bit each. Output Sum, Carry : 1 bit each. a

sum

b carry

Figure 1-1 Half adder circuit Fall Semester, 2004


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Verilog Code for half_adder half adder // Half H lf Adder Add module half_adder (a, b, sum, carry); input a, b; output sum, sum carry; reg sum, carry; always @ (a or b) begin sum = a ^ b; carryy = a & b;; end endmodule

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INTRODUCTION TO Verilog PART II

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Dataflow Modeling

The dataflow level of abstraction is often called Register Transfer Language (RTL). Some behavioral modeling can also be called RTL. RTL The dataflow level of abstraction describes how information is passed between registers in the circuit.

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Concurrent and Sequential Verilog

Verilog Allows Both Concurrent and Sequential Statements to Be Entered. The Difference Between Concurrent and Sequential Statements Must Be Known for Effective Use of the Language Language.

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Concurrent Verilog

All Statements in the Concurrent Area Are Executed at the Same Time. There Is No Significance to the Order in Which Concurrent Statements Occur.

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Concurrent Verilog : Statement St t Statement t Statement : Fall Semester, 2004


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Example of Concurrent Verilog

Full Adder a Sum

b

Full-Adder C_out

C_in

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Full Adder circuit

a b

s1 sum s2 s3

c_out

c_in

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Verilog code for Full Adder // Full Adder Using Signal Assignment Instructions module full_adder (a, b, c_in, sum, c_out); input a, b, c_in; output sum, c_out; wire s1, s2, s3; assign s1 = a ^ b; assign s2 = s1 & c_in; assign s3 = a & b; assign sum = s1 ^ c_in; assign c_out = s2 | s3; endmodule Fall Semester, 2004


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Verilog code for Full Adder

The assign expressions are all g assignment g concurrent signal statements. All the statements are executed at the same time. assign assign assign i assign assign ass g

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s1 = a ^ b; s2 = s1 & c_in; s3 3 = a & b; b sum = s1 ^ c_in; c out = ss2 | s3; c_out Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY

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The simulator evaluates all the assign expressions, and then applies the results lt to t th the signals. i l Once the simulator has applied the results it waits for one of the signal to change h and d it reevaluates l t allll the th expressions again.

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This cycle will continue until the simulation is completed. This is called “event event driven simulation” simulation . IIt iis more computationally i ll efficient ffi i than h time driven simulation.

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Wires

In the full_adder Verilog code we came across “wire”.

So what are “wires”? wires ?

Wires Are Used to Carry Data From Place to Place in a Verilog Design Description.

Wires in Verilog Are Similar to Wires in a Schematic.

Wires are internal to a module.

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Sequential Verilog

Sequential Statements Are Executed One After the Other in the Order That They Appear. Example of Sequential Statement: Always. Always

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Sequential Verilog Begin

St t Statement t Statement Statement End Fall Semester, 2004


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Always Construct

The Always construct is the primary means to describe sequential operations. Always starts with the keyword always, then b begin , and d ends d with h the h keyword k d end d. The whole always construct itself is treated as a concurrent statement.

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Always Statement

The always construct consists of three parts

Sensitivity List Declaration Part Statement Part

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Syntax of Always Statement module module_name module name ( … ports … ); : always @ (sensitivity_list) begin : block_name local_declaration; …… sequential statement; sequential statement; …… end endmodule Fall Semester, 2004


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Always Example module nand2 ((a,, b,, c); ); input a, b; output c; reg c; always @ (a or b) begin : nand2_always_block nand2 always block reg temp; temp = ~(a & b); if (temp == 1’b1) 1 b1) #5 c = temp; else if (temp == 1’b0) #6 c = temp; end endmodule

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Example Description

The always sensitivity list enumerates exactly which signals causes the block to execute. always @ (a or b)

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Example Description

The declarative part is used to declare local variables or constants that can be used in the block. reg temp;

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Example Description

Variables are temporary storage areas similar to variables in software programming languages. reg temp;

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Use of Sequential Statements

Sequential Statements Exist Inside the Always Statements As Well As in Sub Programs. The Sequential Statements Are: if case while for

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forever wait Electrical & Computer Engineering School of Engineering THE COLLEGE OF NEW JERSEY

repeat fork/join

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if Statements

The IF statement starts with the keyword if and ends with the keyword end. if (x < 10) begin a = b; end

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if Statements

There are also two optional clauses

else if clause else clause

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if (day == Sunday) begin weekend = true; end else if (day (d == Saturday) d ) begin weekend = true; end else begin weekday = true; end


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if Statements

The if statement can have multiple else if statement parts but only one else statement part.

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Case Statement

The Case statement is used whenever a single expression value can be used to select l t between b t a number b off actions. ti A Case statement consists of the keyword case followed by an operator expression, i and d ended d d with ith an endcase keyword.

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Case Statement

The expression will either return a value that matches one of the choices in a statement part or match a default clause.

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Case Statement Example reg [1:0] [1 0] bit_vec; bit …… case bit_vec 2’b00 2 b00 : return = 0; 2’b01 : return = 1; 2’b10 : return = 2; 2’b11 : return = 3; endcase

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Loop Statements

The loop statement is used whenever an operation needs to be repeated. Loop statements are implemented in three ways

repeat p condition loop p statement while condition loop statement for condition loop statement

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Loop Statements (repeat)

The repeat condition Loop statement will loop as many times as the condition expression. repeat (flag) begin dayy = gget_next_day _ _ y ((day); y) end

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Loop Statements (while)

The while condition Loop statement will loop as long as the condition expression is TRUE. while (day == weekday) begin dayy = gget_next_day _ _ y ((day); y) end

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Loop Statements (for loop) for (i = 1; i

“A Verilog Overview” A Verilog Overview - The College of New Jersey

“A Verilog Overview” A Verilog Overview - The College of New Jersey

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