this paper we use a CMLI that consist ot some H-Bridge inverters and with un-equal DC. Its also namely. Asymmetric Cascaded Nultilevel Inverter (ACMLI). Its.
International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: 06
47
Advanced Carrier Based Pulse Width Modulation in Asymmetric Cascaded Multilevel Inverter Bambang Sujanarko Dept. of Elect. Eng., Universitas Jember, currently toward Doctor in Institut Teknologi Sepuluh Nopember (ITS) Surabaya, Indonesia
Mochamad Ashari Mauridhi Hery Purnomo Ontoseno Penangsang Soebagjo Dept.of Elect. Eng., Institut Teknologi Sepuluh Nopember (ITS) Surabaya, Indonesia
Abstract –This paper proposes a new scheme Pulse Width Modulation (PWM) to overcome low performances of conventional PWM control strategy in Cascaded Multilevel Inverter (ACMLI). This scheme advance conventional Carrier-Based PWM (CBPWM) using triangle carrier in different amplitudes. By this scheme ACMLI can control by PWM that according to dc voltage amplitude used and finally the Total Harmonics Distortions (THD) can reduce to the settle standard. Simulation using Matlab Simulink used to verify the performance and result simulation shown than this proposed scheme can reach the goals.
the ACMLI, there is a problems, that is its have low power quality performance, so many method to adjust this controller find in many papers in the last decade. To solve this problem, this paper propose a new scheme, which namely Advance Pulse Width Modulations (APWM). This scheme on behalf of PWM, but its not use triangle carrier waveform in equal amplitude as like to in the conventional PWM. The frequency and amplitude of triangle modulation must be according to amplitude of DC voltage on each H-Bridges inverter .
Key word- asymmetric cascaded multilevel inverter, multi carrier pulse width modulation, power quality, total harmonic distortion.
CMLI proposed to solve all the problems of the multilevel inverters as well as conventional multi pulse (or PWM) inverters [5-7]. CMLI eliminates the excessively large number of bulky transformers required by conventional multi pulse inverters, the clamping diodes required by multilevel diode clamped inverters, and the flying capacitors required by multilevel flying capacitor inverters. CMLI consists a series connection of multiple Hbridge inverters. Each H-bridge inverter has the same configuration as a typical single-phase full-bridge inverter [3-4]. CMLI introduces the idea of using separate DC sources to produce an AC voltage waveform. Each Hbridge inverter is connected to its own DC source. By cascading the output voltage of each H-bridge inverter, a stepped voltage waveform is produced [5-7]. If the number of H-bridges is N, the voltage output is obtained by summing the output voltage of bridges as shown in equation (1). Fig. 1 shows configuration of CMLI on single-phase.
I.
INTRODUCTION
The multilevel inverter [MLI] is a promising inverter topology for high voltage and high power applications [1]. This inverter synthesizes several different levels of DC voltages to produce a staircase (stepped) that approaches the pure sine waveform [3-9]. Its have high power quality waveforms, lower voltage ratings of devices, lower harmonic distortion, lower switching frequency and losses, higher efficiency, reduction of dv/dt stresses and gives the possibility of working with low speed semiconductors if its comparison with the two-levels inverters. Numerous of MLI topologies and modulation techniques have been introduced and studied extensively, but most popular MLI topology is Diode Clamp, Flying Capacitor and Cascaded Multilevel Inverter (CMLI). In this paper we use a CMLI that consist ot some H-Bridge inverters and with un-equal DC. Its also namely Asymmetric Cascaded Nultilevel Inverter (ACMLI). Its most implemented because this inverter more modular and simple construction and have other advantages than Diode clamp and flying capacitor [7]. There are many modulation techniques to control this inverter, such as Selected Harmonics Elimination or Optimized Harmonic Stepped-Waveform (OHSW), Space Vector PWM (SVPWM) and Carrier-Based PWM (CBPWM). Among thes modulation CBPWM is the most used for multilevel inverter, brcause it have simple logical and easy to implemented. But if CBPWM used in
II.
108606-5353 IJECS-IJENS © December 2010 IJENS
ACMLI
IJENS
International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: 06 Fig. 1. Single-phase cascaded multilevel inverter. Using fig. 1, output voltage could express as (1). If ACMLI have N H-Bridges, there are many output voltages that produce from (1) with each H-Bridges has three varieties and has switching-states that appropriated on the voltages.
V o (t ) = V o ,1 (t ) + V o , 2 (t ) + ..... + V o , N (t )
(1)
48
sinusoidal pulse width modulation (SPWM), which uses a triangular carrier to generate the PWM as shown in Fig. 2. Fig.2. Basic principle of PWM CBPWM uses several triangle carrier signals, one carrier for each level and one reference, or modulation, signal per phase. CBPWM .for three phases is shown in Fig.3. In this figure shows the reference and carrier waveform arrangements necessary to achieve CBPWM for a seven levels inverter.
I In the CMLI, the DC voltage may or may not be equal to one another. If there are equal DC voltage, it namely symmetric CMLI and if there are un-equal DC voltage, it namely Asymmetric CMLI (ACMLI). Binary and trinary DC voltages progressions are the most popular of unequal DC sources of ACMLI [4]. In binary progression and if the number of H-Bridge inverters are N, the amplitude of DC voltages having ratio 1: 2: 4: 8. . : 2N and the maximum voltage output can equal (2N-1) Vdc. While in the trinary progression the amplitude of DC voltages having ratio 1: 3: 9: 27. . : 3N and the maximum voltage output voltage reach to ((3N1)/2) Vdc. Other un-equal DC voltage is equal interval DC voltage progression. If N=2, the DC voltage are V1=1, V2=1/2; N=3, V1=1, V2=2/3, V3=1/3; N=4, V1=1, V2=3/4, V3=1/2, V4=1/3; and N=5, V1=1, V2=4/5, V2=3/5, V3=2/5, V5=1/5. ACMLI use sine quantization progression [2], also can used in the ACMLI where each DC voltage can be determined by equation (2). In this equation the voltage of sine wave reference is Vm, the frequency is f, the sequence
Vdc , j = Vm sin(ω t j ) (1/ f ) j) 4N 1 = 2 V sin(π j ) j = 1,2,3..., N ( 2 ) 2N = 2 V sin(2πf
Fig.3 CBPWM for seven levels IV.
PROPOSES SCHEME AND DESIGN
The proposed scheme of advance CBPWM can show at Fig. 4. Each carrier wave in the CBPWM has amplitude of voltage peak to peak (vpp) that equal to each DC voltage. In this figure, vpp of carrier wave C3 equal to VDC3, vpp of C2 equal to VDC2, vpp of C1 equal to VDC1, and so also vpp in the negative phase. VDC1 VDC2
III.
CARRIER BASED PWM
Among other modulation, CBPWM strategies are the most popular methods used in CMLI, because they are easily implemented. Basic principle of CBPWM is
C1 C2
reference
VDC3
C3 0
Fig. 4 Proposed scheme Implementation this scheme in the circuit is similar to CBPWM conventional. The difference is only the amplitudes of triangle carrier. Fig. 5 shows block diagram of this circuit. This circuit then simulate with MATALB/SIMULINK. Fig. 6 shows this circuit
108606-5353 IJECS-IJENS © December 2010 IJENS
IJENS
International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: 06
49
simulation. Among DC voltages progression, simulations done using sine quantization DC voltage progression, because has optimum performance [3]. Amplitude of DC voltage in this simulation are Vdc5=1; Vdc4=0.95; Vdc3=0.81; Vdc2=0.59; Vdc1=0.31 9see eq. 2). While the amplitude of triangle are 3.66/5 for CBPWM in the conventional scheme and Vpp C5=1; Vpp C4=0.95; Vpp C3=0.81; Vdc2=0.59; Vdc1=0.31. Amplitude of sine reference in this simulation is 3.66V.
Sine CBPWM
Load
ACMLI
Carrier Triangles Fig, 7. H-Bridges circuit Each H-Bridges in ACMLI has power electronics as shown in Fig. 7. IGBT used in this circuit. In Fig. 8 shown detail of each CBPWM on each H-Bridges.
DC Voltages Fig, 5 ACMLI block diagram
Pulses
Discrete, Ts = 1e-005 s powergui
Pulses Pulses
Subsystem
Pulses
Subsystem1
Pulses
Subsystem2 +
g1
-
g2
V1
g3
+
g1
-
g2
V2
INV 1
g4
-
g2 g3 g4
INV 2
+ v -
g1
V3
g3
g4
+
INV 3
+ v -
+ v -
Subsystem3 +
g1
-
g2
V4
+
g1
-
g2
V5
g3 g4
Subsystem4
g3 g4
INV 4
INV 5
+ v -
+ v -
THD signal
+
i + v -
Fig, 8 Detail of CBPWM 0.1177
Fig, 6. Simulation circuit
V.
RESULT AND DISCUSSION
Results of simulations are shown in Fig.9 to Fig.12. Fig.9 is result simulation in the conventional CBPWM. In this system carrier triangle have equal amplitude, while the DC voltage have sine quantization as decrypted above. Its show that the waveform has fundamental amplitude 3.997 and THD in the frequency up to 1500 is 8.94%. The frequency spectrum this system is shown in Fig. 10.
108606-5353 IJECS-IJENS © December 2010 IJENS
IJENS
International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: 06
50
conventional. Fundamental output voltage in this system has amplitude 3.663 and THD in the frequency up to 1500 Hz is 0.49%. Wile the spectrum frequency up to 1000 Hz in this system shows in Fig.12.
Fig, 9 Output waveform and frequency spectrum of CBPWM conventional
Fig, 10 Frequency spectrum of CBPWM conventional Fig. 11 shows result of CBPWM was proposed in this paper. This result indicates that the proposed scheme can improve power quality, although this system only replaces the amplitudes of carrier triangle in the CBPWM
Fig, 11 Output waveform and frequency spectrum of Advance CBPWM
Fig, 12 Frequency spectrum of Advance CBPWM From Fig. 10 to Fig, 13, it show that the performance of the ACMLI more different, where the proposed scheme has better quality, especially to reduce THD. The different also happen in the other DC voltage progression.
108606-5353 IJECS-IJENS © December 2010 IJENS
IJENS
International Journal of Electrical & Computer Sciences IJECS-IJENS Vol: 10 No: 06 CONCLUSION A new scheme of CBPWM for ACMLI was proposed to improve the output voltage of CMLI. This scheme only replaces amplitude of carrier wave in the CBPWM according with amplitude of DC voltage that used in each H-Bridge. In the five H-Bridge of sine quantization ACMLI, THD can improve from 8.94 to 0.49%, Beside this power quality parameter, other parameter also can improve extremely, such as frequency spectrum and amplitude of fundamental output voltage. REFERENCES [1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
B. S. Suh, G. Sinha, M. D. Manjrekar, T. A. Lipo, “Multilevel Power Conversion – An Overview of Topologies and Modulation Strategies”, IEEEOPTIM Conference Record, pp. 11-24, vol. 2, 1998. Bambang Sujanarko, Mochamad Ashari and Mauridhi Hery Purnomo, “Universal Algorithm Control for Asymmetric Cascaded Multilevel Inverter”, International Journal of Computer Applications (0975 – 8887), Vol.8, No.15, November 2010. E. Babaei, S.H. Hosseini, G.B. Gharehpetian, M. Tarafdar Haquea, M. Sabahi, “Reduction of dc voltage sources and switches in asymmetrical multilevel converters using a novel topology”, Electric Power Systems Research, 77, 2007, pp. 1073–1085. J.S. Lai and F.Z. Peng, “Multilevel converters—A new breed of power converters”, IEEE Transactions on Industry Applications, vol.32, pp. 509–51, May/June, 1996.
51
Mochamad Ashari received the Bachelor degree in electrical engineering from the Institut Teknologi Sepuluh Nopember(ITS) Surabaya, Indonesia, in 1989 and Master and Ph.D. from Curtin University of Technology, Perth, Australia. He has been with ITS since 1990 as a Lecturer in the Department of Electrical Engineering. He is a Professor and head of Electrical Engineering ITS. His research interests include power electronics and inverter applications, power system modeling, simulation, and analysis of hybrid power systems.
Mauridhi Hery Purnomo received the B.S. degree from Institut Teknologi Sepuluh Nopember (ITS) Surabaya, Indonesia and Master ad Ph.D from Osaka City University, Osaka, Japan. He is a Professor in the Department of Electrical Engineering, ITS. Since 2007, he was vice director on ITS postgraduate program. He has been engaged in research and teaching in the areas of intelligent system and pattern recognition, power system simulations, and computer programming Ontoseno Penangsang is a Professor in the Department of Electrical Engineering, Institut Teknologi Sepuluh Nopember (ITS), Surabaya , Indonesia. He has been engaged in research and teaching in the areas of power system and electric power simulations. Soebagyo is a Professor in the Department of Electrical Engineering, Institut Teknologi Sepuluh Nopember (ITS), Surabaya , Indonesia. He has been engaged in research and teaching in the areas of electric drive and electrical vehicles.
Kuhn, H. Ruger, N.E. Mertens, A., “Control Strategy for Multilevel Inverter with Non-ideal DC Sources”, Power Electronics Specialists Conference (PESC), Hanover, 2007. L. M. Tolbert, John N. Chiasson, Zhong Du, and Keith J. McKenzie, “Elimination of Harmonics in a Multilevel Converter With Nonequal DC Sources”, IEEE Transactions On Industry Applications, Vol. 41, No. 1, January/February 2005, pp. 75-82. M. G. Hosseini Aghdam, S. H. Fathi, G. B. Gharehpetian, “A Complete Solution of Harmonics Elimination Problem in a Multi-Level Inverter with Unequal DC Sources”, Journal of Electrical Systems, 3-4, 2007, pp.259-271. S. J. Park, F. S. Kang, S. E. Cho, C.J. Moond, H. K. Nam, “A novel switching strategy for improving modularity and manufacturability of cascadedtransformer-based multilevel inverters”, Electric Power Systems Research, 74. 2005, pp. 409–416 S. Krishna, “Harmonic Elimination by Selection of Switching Angles and DC Voltages in Cascaded Multilevel Inverters”, Fifteenth National Power Systems Conference (NPSC), IIT Bombay, December 2008.
AUTHOR PROFILE Bambang Sujanarko received the B.Sc. from Universitas Gadjah Mada, Yogyakarta Indonesia and Master from Universitas Jember, Indonesia. He is senior lecture of Departement Electrical Universitas Jember and currently toward his Ph.D in Institut Teknologi Sepeluh Nopember (ITS) Surabaya, Indonesia. His research interests included power electronics and renewable energy systems, hybrid power systems, artificial intelligent, and instrumentation.
108606-5353 IJECS-IJENS © December 2010 IJENS
IJENS
