Pulse Width Amplitude Modulation Based CMOS Multiplier - IEEE Xplore

2010 Electronics, Robotics and Automotive Mechanics Conference

Pulse Width Amplitude Modulation Based CMOS Multiplier Ricardo Astro†∗ , H´ector G´omez†∗ , Jhoan Salinas†∗ and Alejandro Diaz-Sanchez†‡ † Instituto Nacional de Astrof´ısica, Optica ´ y Electr´onica - INAOE Luis Enrique Erro 1, Tonantzintla, Puebla, M´exico ∗ Grupo de Dise˜ no de Circuitos Integrados – CIDIC Carrera 27-Calle 9, Ciudad Universitaria, Bucaramanga, Colombia ‡ Instituto Tecnol´ ogico de Puebla Av. Tecnol´ogico 420, Puebla, M´exico Email: {rastro, hgomez, jsalinas, adiazsan}@inaoep.mx Abstract—In this paper, a pulse width amplitude modulation multiplication scheme, that uses a novel flipped voltage follower (FVF) based current switch is presented. Simulations performed in Hspice with the standard AMI 0.5 μm CMOS process shows a system with dynamic range of ±140 mV for both input signals with a maximum gain error of 1.1%. The circuit works with VDD = 3 V and a power consumption of 2.2 mW. The multiplier has a bandwidth of 16 kHz.

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Keywords-Pulse width amplitude modulation, multiplier, flipped voltage follower, current switch.

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Figure 1: PWAM based multiplier.

I. I NTRODUCTION Multipliers are basic blocks in many analog systems. In their design it is desired to have high linearity over a wide input dynamic range, wide bandwidth and low power consumption. Typically multiplication is done by a nonlinear device that generates the product and many undesired terms around it, so a cancellation scheme is needed in order to cancel those terms [1]. However, there are other forms to multiply. One of these consists in a combination of pulse width modulation (PWM) and pulse amplitude modulation (PAM). Both of them generate a signal which duty cycle have the information about multiplication. This scheme is called pulse wide amplitude modulation (PWAM) and it is reported in previous works. For example, [2] describes a two quadrant multiplier and [3] describes a four quadrant multiplier. In this paper, an scheme of a PWAM based multiplier is presented. The multiplier uses a novel high speed current switch based on the flipped voltage follower (FVF), a cell with a wide field of application [4]–[6] . The document is organized as follows: section II gives a general overview of the system. The system at circuit level is explained in section III and section IV shows simulation results of the complete multiplier. Conclusions are drawn in section V.

The desired waveform of vm is shown in Fig. 2. It should be noted that vm amplitude depends on v1 and its duty cycle, defined by T1 and T2 times as shown in Fig. 2, depends on the input signal v2 and period T and amplitude E of signal reference. Equations (1) and (2) describe times T1 and T2 as function of v2 , E and T . v2 + E T (1) 2E E − v2 T2 = T (2) 2E When signal vm is generated with the characteristics defined above, it is necessary to filter the signal in order to extract the DC component and get a voltage proportional to the product v1 · v2 . The low-pass filter (LPF) bandwidth should be less than the triangular reference signal frequency 1/T . The mechanism used to generate vm consists in getting a value proportional to v1 and another proportional to −v1 depending on the switch state whose control signal comes from a circuit that compares v2 with the triangular reference signal. T1 =

III. D ESIGN II. PWAM BASED M ULTIPLIER

General implementation of the system is shown in Fig. 3. The circuit creates the signal vm by adding two current signals in the resistor R, one proportional to v1 and the other with the following characteristics:

The goal of the system, shown in Fig. 1, is to generate a squared shape signal vm whose duty cycle contains the information of the multiplication of signals v1 and v2 . 978-0-7695-4204-1/10 $26.00 © 2010 IEEE DOI 10.1109/CERMA.2010.135

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Figure 4: PMOS differential pair with active load. VDD

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Figure 2: Typical signals of Fig. 1 circuit.

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A 0 value when the switch is open. A value proportional to −2v1 when the switch is closed. The basic blocks used in the PWAM multiplier are OTAs, A a gain 2 A A current switch, a gain 1 A current mirror, a low pass filter and a Vc generator. These circuits are described below. The OTAs use a PMOS differential pair with current mirror as active load (Fig. 4). In their design a low transconductance is sought in order to increase input dynamic range in v1 and keep low distortion level. The bias point of the output must bring DC coupling with the next FVF stage and minimize offset currents. Fig. 5 shows the proposed FVF based current switch. The circuit is characterized by an input-node with a very low impedance suitable for current sensing [7] and a large

M5 M6 iout vm M7 M8

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impedance output-node appropriate for current delivering. The block works as follows: • When Vc =“1” (Vc = 1.8 V), all transistors are turned on. M3,4 and M7,8 form a cascode current mirror with signal current gain iout /iin = 2 A A . Transistors M5−8 drive the same bias current, so node vm delivers only-signal current and not DC component. • When Vc =“0” (Vc = 0 V), the low logic signal turns off M3 , M8 tends to increment its current because it has VGS = VDD , so it is needed to switch off transistor M7 in order to avoid a current path from M8 to node vm . In the same way M6 is placed as a means to block the current flow from M5 to node vm . As a consequence the node vm acts as a high impedance node and both the static power consumption and offset associated with M5,6 bias current are reduced. An FVF cascode current mirror (Fig. 6) is used as a current buffer. A cascode structure (M18 ) is used to improve the current copy. This current mirror also establishes the bias point of node vm by sinking a current from the resistance R. This bias point must be equal to current switch one in order to reduce offset. The signal addition is performed by the resistance R, and voltage vm corresponds to PWAM modulated signal with multiplication information contained

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Figure 5: FVF based current switch.

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Figure 3: Diagram of the system.

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where it is observed a high level of linearity and a maximum gain error of 1.1% in an input dynamic range of ±140 mV for both input signals v1 and v2 . Fig. 11 presents the multiplier transient response for inputs that produce transitions between extreme product values. It can be noticed that the maximum allowed frequency is 16 kHz, which is defined by the LPF natural response.

in its duty cycle. VDD

M14 M15 VB3

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V. C ONCLUSIONS

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In this paper, a pulse width amplitude modulation multiplication scheme is presented. The modulator uses a novel FVF based current switch which give both low-input and high-output impedances. The multiplier generates a squared shape signal vm whose duty cycle contains the information of the multiplication of signals v1 and v2 . The simulations were performed in Hspice for a standard AMI 0.5 μm CMOS process, and they show linear responses for controlled signals by v1 and v2 . The whole system presents a dynamic range of ±140 mV for both input signals with

Iout2 M17

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Figure 6: FVF based current mirror. Control signal Vc is generated by adding in series, amplifying and regenerating v2 and Vref . As it is shown in Fig. 7 that is realized with a common source stage followed by a pair of CMOS inverters and a level shifter that guarantees a high logic level “1” of 1.8V. This voltage is needed for biasing the FVF switching.

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IV. S IMULATION R ESULTS

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Figure 8: Linear increments in vm node voltage amplitude. 2.5

V2=0 V2=35mV V2=70mV V2=105mV V2=140mV

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The proposed circuit has been designed and verified with Hspice for the standard AMI 0.5 μm CMOS process. The circuit is operated by a single 3 V power supply and presents a power dynamic consumption of 2.2 mW. Since the multiplier is based in amplitude and pulse width modulation of signals v1 and v2 , it is required a linear variation of these parameters respect its control voltage. Fig. 8 shows modulated signal amplitude variations respect to voltage v1 , where it can be seen the desired linear behavior. On the other side the output signal pulse width is controlled by Vc , which depends on v2 . In Fig. 9 it is shown the dependence between duty cycle and v2 where it is observed a linear relationship. These characteristics improves the linearity, which is established by getting the DC transfer characteristic. The result is shown in Fig. 10, VDD

V1=0 V1=35mV V1=70mV V1=105mV V1=140mV

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Figure 9: Linear increments in Vc pulse width.

Figure 7: Control signal generator.

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R EFERENCES [1] G. Han and E. Sanchez-Sinencio, “CMOS transconductance multipliers: a tutorial,” Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, vol. 45, no. 12, pp. 1550 –1563, dec 1998.

    









 





[2] J. Holt, “A two-quadrant analog multiplier integrated circuit,” Solid-State Circuits, IEEE Journal of, vol. 8, no. 6, pp. 434 – 439, dec 1973.



Voltage [V]

Figure 10: DC transfer characteristic. 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1

[3] M. Siripruchyanun and P. Wardkein, “A four-quadrant analog multiplier based on switched-capacitor and pulse-width amplitude modulation techniques,” in Electronics, Circuits and Systems, 2002. 9th International Conference on, vol. 1, 2002, pp. 235 – 238 vol.1. [4] I. Padilla, J. Ramirez-Angulo, R. Carvajal, A. LopezMartin, and A. Carlosena, “Compact implementation of linear weighted cmos transconductance adder based on the flipped voltage follower,” in Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on, 0-0 2006, pp. 4 pp. –4284.

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INAOE and Conacyt for post-grade education opportunity and the support provided through scholarships number 344971, 344975 and 344973.

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[5] A. Lopez-Martin, J. Ramirez-Angulo, and R. Carvajal, “Lowvoltage low-power wideband cmos current conveyors based on the flipped voltage follower,” in Circuits and Systems, 2003. ISCAS ’03. Proceedings of the 2003 International Symposium on, vol. 1, 25-28 2003, pp. I–801 – I–804 vol.1.


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Figure 11: Transient response.

[6] J. Ramirez-Angulo, R. Carvajal, A. Torralba, J. Galan, A. VegaLeal, and J. Tombs, “Low-power low-voltage analog electronic circuits using the flipped voltage follower,” in Industrial Electronics, 2002. ISIE 2002. Proceedings of the 2002 IEEE International Symposium on, vol. 4, 2002, pp. 1327 – 1330 vol.4.

a maximum gain error of 1.1%. The circuit works with VDD = 3 V and a power consumption of 2.2 mW. The modulator and multiplier bandwidth obtained are 1 MHz and 16 kHz respectively.

[7] R. Carvajal, J. Ramirez-Angulo, A. Lopez-Martin, A. Torralba, J. Galan, A. Carlosena, and F. Chavero, “The flipped voltage follower: a useful cell for low-voltage low-power circuit design,” Circuits and Systems I: Regular Papers, IEEE Transactions on, vol. 52, no. 7, pp. 1276 – 1291, july 2005.

VI. ACKNOWLEDGEMENT The authors thank Juan Carlos Mateus Ardila for useful discussions and edition support. Also we want to thank

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