An accurate time-domain current waveform simulator for VLSI circuits ...

An Accurate Time-Domain Current Waveform Simulator for VLSI Circuits Jyh-Herng Wang , Jen-Teng Fan and Wu-Shiung Feng Department of Electrical Engineering National Taiwan University Taipei, Taiwan, R.O.C. Abstract

adopt another approach in [2] which is more complex, but it can give accurate results even when the load is very large. After analyzing the possible transition of a gate, the current waveform under one input vector excitation can be obtained with only four parameters. No matter which model is used in previous works, simulation or estimation, only the current flowing during the rising and falling edges of the output signals of CMOS gates is considered. After developing the first current model [2], we find that large errors still exist in some large circuits. The primary reason is the neglect of the current flowing across the gate capacitance of CMOS gates. Currents flow across these gate capacitors when the input signals change, whether the gate changes state or not. So we develop another current model which takes this current into account. In this model, we decompose the total current supported by the VDDbus into three components. We try to calculate the individual charge for each of these three components, and then the total current is obtained.

A new charge-based current model for CMOS gates is presented in this paper. The current during a transition consists of three components : one occurs when the input changes and the others ezist only when the output changes. So, this model can generate current waveform with negative values, like SPICE. These three components are characterized b y triangular functions with four parameters which can be easily obtained after timing simulation. When comparing the resulta obtained b y wing SPICE with those b y our model, we find agreement, especially on the time points at which mazimum current occurs.

1

Introduction

In large integrated circuits, current flow in power and ground buses leads to the problems of voltage drop and metal migration, which are the major reliability problems. The problems are especially important in the widely used CMOS technology, where switching transients from different parts of a circuit can occur almost simultaneously and thus, may generate large noise spikes (in the form of voltage drops) in the power/ground buses. Unrestricted voltage drops in the P/G buses may result in incorrect logic operation and degradation in switching speed. Restricting voltage drops to safe limits requires the knowledge of peak current in the P / G buses. A time-domain current waveform simulation is proposed in [I], where the current is approximated by an isosceles triangular current pulse. This model can achieve great accuracy when the load of each gate is small. Since the current pulse is asymmetric when the load is large, so this model will result in large errors. Also because of the asymmetry, the peak current obtained by this model will deviate from the real peak current, so the peak value of the total current supported by the power bus is not correct. We

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There are many parasitic capacitors existing insidSo there will be current e a CMOS gate, e.g. Cgs. flowing if the voltage drop of any two terminals of a MOS transistor changes. We assume that current flows only when the inputs of the gate change. This means that leakage currents are neglected. The current drawn from the VDDbus consists of three components : (1) gate capacitor differential current, (2) load capacitor charging current, and (3) short-circuit current. The last two components exist only when the output of the gate changes state. Let us consider the circuit shown in Fig.l(a). Let B be HIGH,then this NOR gate will not change state no matter which state A is in. When the input of the inverter increases from OV t o 5V, the voltage of node A will decrease. We can find one current component in the NOR gate, t-

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Current Model

flows into the VDDbus. This current is labeled as I1 shown in Fig.2. Since this current is due to the change of the input, the values of T , l and Tcl are set as the time when the input signal begins and stops changing respectively, as shown in this figure. The peak current occurs when the voltage slope of the input is a t its maximum. So Tpl is the time when the input is 2.5V approximately.

WO current components in the first inverter, and three current components in the second inverter, as shown in Fig.l(b). All researchers [1,2,57] focus attention on the charging/discharging current and short-circuit current of CMOS gate, so only the currents I13 and I3a+I33 are considered. But owing to the change of the voltage drop across the gate capacito, there are currents I2 and I31 flowing from VDDt o node A across the gate capacitors, and I11 flowing to VDDacross the gate capacitor of the inverter gate. Notice that I1 decreases and then increases due to the existness of 113. So there will be large error if neglecting this current. Each current waveform can be represented as a triangle with four parameters (T,, T,,T,and Q), as shown in Fig.2. Q is the total charge transferred to/from the VDD bus and is equal t o the area of this triangle. These three time parameters designate the time when the current waveform begins, reaches its peak value and stops changing. We try t o calculate the charge transferred and determine the values of these three time parameters from the voltage waveforms, then each current waveform can be obtained. After we sum each current waveforms up, the total current is obtained.

2.1

2.2

Fig.3(a) shows the generic CMOS gate structure used in many literatures [SI. The output node capacitance is split into two lumped capacitors, C, and C,. Only $ 1 and &I are considered [6]. The primary problem in this model is how t o split parasitic capacitors into C , and C,? Not all capacitances are connected directly to VDD or G N D ,so the value of C, and C,, is time-variant. Since the total charge transferred to the load during the transition is VDD the point is how to calculate the load capacitance accurately. We use the circuit shown in Fig.3(b) to measure the input capacitance of a CMOS gate. We try to adjust the value of Ca# to make voltage waveform VI coincide with Va and make i l x i a , and then the input capacitance of the test gate at this input terminal is set to Ca#. The input capacitance is a function of the design parameters(& W ,.. .), and its value seems to be independent of what type of gate is. So the total charge transferred can be calculated as

Capacitor Differential Current

To simplify the calculation, the currents flowing to/from VDD are considered only, though there are many parasitic capacitances existing inside the CMOS gate. This current can be calculated as When the input increases(decreases), the current flows into(from) the VDD bus. Since C,, and c g b are inputdependent and nonlinear, so the total charge transferred due to this current can be calculated as :

q.

This current is labeled as I2 shown in Fig.2. Since this current is due to the change of the output voltage, the values of Tdaand Tea are set as the time when the output voltage begins and stops changing respectively. The peak current occurs when the voltage slope of the output is at its maximum. So Tpa is the time when the output voltage is 2.5V approximately. We want to find the total current supported by the VDD bus, so we are interested in the current on the low-to-high transition. Of course, the current will be larger than $ 1 or & I , as shown in Fig.S(a). But since C, is the gate capacitance at the next stage, there will be a capacitance-differential current flowing to VDD. So the over-estimated current will be eubtracted when we process the next stage. On the other hand, the current will be under-estimated on the high-to-low transition owing t o our neglecting the discharging current. But because C, is the gate capacitance at the next stage, there will be a capacitance-differential current flowing from VDD. So the under-estimated current will be also complemented.

VDD-V.

Q=/

c(v).dv=Cejf*(K-ve),

(1)

VDD-V.

where V, and V, are the initial and final values of the input during this transition, respectively. Its value is determined by the total capacitance considered, no matter how fast the input changes. If the source of the MOS is connected to VDD, e.g. M I , the capacitance is C,, c g b . If the source of the MOS is not connected to VD ’ directly, e.g. Ma, then the capacitance is either c g b c,, if there is a conducting path connecting the source of this MOS t o V’D, or c g b if no conducting path to VDD, where k is equal to So it is determined during the simulation process that how many parasitic capacitances needed considering. These capacitances are functions of the design parameters (L,W, .. .), and these values can be measured using SPICE previously . If V, is smaller than V,, Q is negative and it means that the differential current

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Capacitor Charging Current

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2.5

Short-circuit Current

During a transient on the input, there is a time period in which both the N-block and the P-block conduct, causing a current to flow from VDD to ground. This current flows as long as the input voltage is higher than a &N above GND and lower than a V;p below VDD.It is very difficult t o describe the short-circuit current precisely, and the analytical solution of this current can be obtained only when the gate is a CMOS inverter gate under some assumptions. The total charge transferred due t o this current can be obtained previously with SPICE as follows:

Q= 'n''/

Ivpp

- Q d i j f - Qlocrdi

This current model has been embedded into our timing simulator BTS [3, 81. BTS uses a recursive technique to calculate the delays in the series-parallel MOS circuits [4]. The results of BTS are accurate because BTS uses an accurate delay calculation method that computes the switching delays and slopes with the considerations of the effects of the internal charges [E]. Fig.2 shows the voltage and current waveforms at the second stage of a 3-stage inverter chain. When the timing simulation finishes, the event list at the output of each gate can be obtained. The input of this inverter begins t o decrease at 2 . 2 5 ~and its slope is -7.14. 10gV/sec. The output increases at 2.74 ns and its slope is 8.62V/ns. Since the input decreases, the current waveform consists of three components. The areas of these three components can be obtained using Eqn.(l), (2) and (4). These time parameters can be obtained from the voltage waveform as described in previous sections and their values are :

(3)

t.1.,*

where tatart and t e n d are the time when the input begins to change and the output stops changing. IvDD is the current drawn from the VDD bus. Qdiff and Qload are the charge due t o the differential and charging current, respectively. This charge is a function of the total effective resistances Rp and R N and can be modeled as A B Q=+-+C, (4) RP RN where A, B and C are the fitting parameters. R p and RN are the total effective resistances of the P- and N-block, respectively. After assigning the ON/OFF state to each MOS according the states of inputs, we can obtain R p and RN, then the charge Q is obtained. This current is labeled as I3 shown in Fig.2. The values of Ta3and Te3are set as the time when the voltage difference of the input and the output are 4V and -4V respectively with the assumption that lqpl = lVtnl = 1V. Tp3is the time that the input voltage and the output voltage are equal. 2.4

Simulation

3

Tal = 2.25ns Tpl= 2.6ns Tel= 3.7ns T.1 = 2.74ns Tpa= 3.03ns Tel= 3.97ns Ta3= 2.43ns Tp3= 2.86ns Te3= 3.33ns The time-domain current waveform supported by the VDD bus is the summation of the current waveforms of each block. The current waveform of each block consists of a series of triangular pulses, and is represented as a current source to the VDD bus. Since the metal resistance is negligibly small within a subcircuit, we can combine several sources in a subcircuit into a single current source, which represents the power-bus current drawn by the subcircuit. Let the addition of a triangle t o the waveform be a basic unit of calculation. And let M , N, and K be the total event number of all blocks, the total event number of all primary inputs of this circuit, and the total event number of the primary outputs of this circuit, respectively. When we calculate the current waveforms, the number of the addition operation required are follows

Glitch

The accuracy of the current simulation depends strongly on the voltage waveforms. The glitch may occur when two adjacent events are so close that the second event occurs before the first event finishes, as shown in Fig.4(a). Glitches may draw significant amounts of currents and should not be neglected. When calculating the current waveform resulting from the first event, we assume that this event can reach its final state, so that the whole current waveform can be obtained. But since the second event occurs before the first event finishes, so the current waveform is cut at the time the second event occurs, as shown in Fig.4(b). We approximate the current waveform resulting from the second event according to the peak where Vz is the voltage swing of the glitch. ratio,

M-N for capacitor differential current ( M - N - K ) for load capacitor current M-N for short circuit current.

3

e

So the total number of the addition is q M - q ( N + K ) . Because M ,in general, is larger than N + K ,the CPUtime overload of the current calculation to the timing simulation is strongly dependent on the event number, no matter how large the circuit.

e,

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4

Results and Conclusions

Circuits," Proc. ICCAD-88, pp. 208-211.

The simulator has been tested extensively for basic modules such as counters, decoders, adders and ALUs. The CPU time comparisons are summariaed in Table 1. The CPU time consists of the time that the timing simulator BTS used and that the current calculation used on a SUN SPARC station l+. Since BTS considers the effects of the internal charges, the simulator is not as fast as other timing simulators, but the waveforms it derives are more accurate. It is very important that the accuracy of the current waveform calculation is strongly coupled t o the accuracy of the timing information. In Table 1, we list three more error values, DC, M a x J and Max-T. DC error is the relative error between the average current I a U g . ~ pand ~ cI~a U g . ~ ~Msa. x 1 is the relative error between the value of the peak current I p e 0 ~ . s p ~ c ~ and Ipc&.BTS. M a x 2 is the absolute error about the time that the peak current occurs. Fig.5 shows the current comparisons of an encoder SN74147 with SPICE'S result. For the purpose of comparison, the current waveform is the summation of all the currents from individual subcircuits. If a circuit is implemented based on some restricted design styles, such as full complementary CMOS, Pseudo-NMOS, Dynamic CMOS, etc., the circuit can be simulated by using BTS and then the current waveform can be obtained. Fig.6 shows the voltage and current waveforms of a 4-bit carry-lookahead adder. The carry gate of this circuit is implemented as a domino CMOS gate. A current model is presented which can be used to generate the time-domain transient current waveforms in the power bus lines. The simulated waveforms in general differ by no more than 10% from those simulated by SPICE. Its speed is loz lo3 times faster than that of SPICE for circuits with hundreds of transistors, and the speed ratio is expected to be even more significant for larger-scale circuits. At the cost of a little speed ratio, the results are more accurate, especially the time a t which the peak current occurs.

J.H. Wang, J.T. Fan, and W.S. Feng, "A NOVEL CURRENT MODEL FOR CMOS GATES," Proc. ISCAS-92, pp-2132-2135, 1992. J.H. Wang, M. Chang, and W.S. Feng, "The Effects of Internal Charges t o Waveform Calculation," Proc. APCCAS, Sydney, Australia, 1992. J . P. Caisso, E. Cerny, and N. C. Rumin, "A Recursive Technique for Computing Delays in Series-Parallel MOS transistor Circuits," IEEE Trans. on CAD, pp. 589-595, May 1991. H.J .M. Veendrick, UShort-Circuit Dissipation of Static CMOS Circuitry and Its Impact on the Design of Buffer Circuits," IEEE JSSC, vol. sc-19, No. 4, pp.468-473, August, 1984

S.Chowdhury, and Javed Sabir Barkatullah, UEstimation of Maximum Currents in MOS IC Logic Circuits," IEEE h n s . on Computer-Aided Design, vol9, no. 6, pp. 642-654, June, 1990. Ulrich Jagau, "SIMCURRENT - An Efficient Program for the Estimation of the Current Flow of Complex CMOS Circuits," Proc. ICCAD-90 pp. 396-399, 1990. J.H. Wang, M. Chang, and W.S. Feng, "Binarytree timing simulation with consideration of internal charges," IEE Proceedings-E, vol. 140, No. 4, pp. 211-219, July 1993. VDD

VDD

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Table 1 :Comparisons between BTS and SPICE3 Ckt. 74381 7483 L 74147 Inv

Error IMad DC 0.56% -8.52% -1.71% -4.15% 1.78% 5.76% -7.43% 2.2%

I

CPU time(sec)

I M a c T I BTS I SPICE -8.2e-11 -6.4e-13 7.0e-10 -4.2e-12

1.48 1.38 1.11 0.70

1478.7 282.37 I 121.55 I 100.7

References

Figure 1: (a) A %stage CMOS circuit and (b) the voltage and current waveforms obtained by using SPICE.

[I] A. c. Deng, Y. C. Shiau, and K. H. Lob, ''Time Domain Current Waveform Simulation of CMOS

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Figure 2: Each current waveform is modeled as a triangle, 1 1 , 12 or 13. 1lotcll is the summation of these current triangles. The dashed line is obtained using

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Figure 5: The current w%%%8f to 4-line BCD encoder SN74147.

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Figure 3: (a) A generic CMOS gate and (b) the method used to measure the input capacitance of CMOS gate.

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Figure 4: Voltage waveforms with glitch. (a)the voltage waveforms of an two-input NOR gate and (b) the waveform of the total current. Since the second event occurs, so the dashed tail is cut.

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