An Alternative Approach for Real Time Digital Controller Implementation

An Alternative Approach for Real Time Digital Controller Implementation NITISH PATEL, SING KIONG NGUANG Dept. of Electrical and Computer Engineering University of Auckland Private Bag 92019, Auckland NEW ZEALAND

Abstract: - In a digital controller, a multi-bit binary word is produced at regular intervals which an arithmetic unit uses to generate a new control word for the next sampling interval. This paper proposes a similar and yet a different technique to implement cascade controllers. Instead of a multi-bit word a single bit stream represents the analogue signal and elementary digital gates implement the required control algorithm. These controllers can be implemented on Field Programmable Gate Arrays, FPGA’s. Bit-stream controllers for two single-inputsingle-output, SISO, systems have been successfully implemented and presented. The design methodology is similar to continuous time controllers and also offers the versatility of digital systems. The inherently parallel nature of this technique also makes it possible to implement controllers for larger and more complex multipleinput-multiple-output, MIMO, systems. Key-Words: - Real-time systems, MIMO, bit-streams

1 Introduction The availability of a variety of integrated circuits have made digital control systems [1] easier to implement. Micro controllers and Digital Signal Processors, DSPs, are optimized for fixed width binary words typically 8 bit, 16 bit or 32 bits. All these have one thing in common and that is they are all serial processors, i.e. at any point in time they can only execute a single instruction. The choice of the word size is governed by the required dynamic range, the signal to noise ratio, the nature of the control algorithm or even the cost of the silicon hardware and the associated development tools. Large systems or complex algorithms requiring a large number of computations for every sampling interval would naturally require a faster processor. In MIMO systems the current control action is dependent on several inputs. Since several different control algorithms may be required for each output, several algorithms need to be processed by the next sampling interval. These kinds of systems may require more than one processor. An artificial neural network [2] is an example of a typical coupled MIMO system. In this case each algorithm is simple but usually has a large number of inputs. In a serial solution, a fast processor updates the output of each neuron one at a time. In a parallel solution several processors, ideally one for each neuron, are interconnected. However the difficulties in routing of data usually restricts the complexity of the network.

The routing difficulties can be mitigated by bitserializing the data word [3] e.g. an 8 bit word is sent to its destination over 8 clock cycles. The receiver must then accumulate these bits to reconstruct the full 8 bit word and process it normally. Alternatively, the 8 bit word could be sliced into 2 or 4 sections [4] which the receiver can then reconstitute accordingly. In a multi-bit word environment, each processor is fairly complex requiring an appropriate arithmetic unit and may require some local RAM to store intermediate results. Bit-slicing necessarily introduces delays in the order of the number of slices which can be used advantageously by pipelined arithmetic units. However they are still reasonably complex. This study introduces the use of a uniformly weighted single bit stream to achieve simple but typical control algorithms. The uniformity leads to simple logic operations for typical control actions which can be easily implemented on a Field Programmable Logic Device, FPGA. The bit-stream representation of analogue signals is presented in Section 2. A method of generating bit-streams and converting them back to analogue signals is shown in the Section 3. The structures of bit-stream control elements and their applications to two systems are presented in Section 5.

2 Magnitude Representation

In a multi-bit binary representation, the weight of each bit is 2m-1 where m is the index into the binary word. 2s complement is used to represent negative values. In a uniformly weighted bit-stream each bit carries the same weight. Here a logic '1' is taken as a positive quantum and a logic '0' as a negative quantum.

2.1 Zero Magnitude Since a logic '1' is defined to be a positive quantum and a logic '0' as a negative quantum then an alternating stream of 1s and 0s represents a zero value, or more accurately a signal whose value is not changing. This perfect zero is shown in Fig 1.

Zero

+Q −Q +Q −Q +Q −Q

t

S1

0

+Q

0

0

0

+Q

0

0

0

+Q

0

+Q

0

t

S2

0

0

−Q

0

0

0

−Q

0

0

0

−Q

0

0

t

Fig. 1 Magnitude Representation

2.2 Non-zero Magnitudes A positive valued signal must be represented with a bit-stream that has more positive quanta. Another way to view this is by inverting some of the negative quanta into positive quanta. Signal S1 in Fig 1 shows a positive valued signal while S2 is a negative valued signal. Statistically, a positive valued bitstream will have more positive quanta while a negative signal will have more negative quanta. A full-scale positive signal will have all the bits at logic '1' while a full-scale negative signal will have all its bits as logic '0'. By comparing an unknown bit-stream with the zero valued signal it can be decomposed into two other bit-streams: a high, 'h', signal and a low, 'l', signal. Each one is active when a positive or negative quanta arrive respectively. Here zed is the zero valued signal, h is a bit-stream that is active for the positive quanta while l is the bit-stream for the negative quanta. Usually, h and l are 'internal' signals and used primarily within a functional element. This form of magnitude representation is also shift independent. This is important as the bit-streams are likely to experience a single bit delay when processed by functional elements discussed later in this document. Since all digital logic involving latches and counters require a clock signal for synchronization, the zero signal can

be easily derived from this clock and does not require much more addition logic nor does it consume any interconnect resources on the FPGA.

3 Bit-Stream Converters Bit-stream converters are widely used in non-realtime applications like CD players and PC soundcards. They usually consist of a delta modulator followed by a decimator. In bit-stream processing the decimation process is not required. Hence both the Analogue to Digital Converter, A/D, and the Digital to Analogue Converter, D/A are even simpler. Conceptually, a bit-stream A/D is built around a comparator and a charge-pump. Conceptual diagrams of an A/D and a D/A are shown in Fig 2. The charge pump shown in Fig 2 delivers a positive or negative charge to the capacitor depending on the state of the comparator. As long as the rate of change of the analogue input is less than that generated by the charge-pump/capacitor combination, the converter will be guaranteed to lock on to the input. De-modulating a bit-stream is achieved by driving a charge-pump/capacitor with the bit-stream. To ensure zero drift, the charge pump must deliver an exact amount of charge in both states. This requirement is difficult to meet even if the devices are made in a silicon foundry however with clever charge balancing techniques the problems can be alleviated. Analog in

BS out +

Latch Clock

Charge pump

Analog out

BS in Charge pump

Fig. 2 Conceptual Bit Stream Converters

Fig 3 shows a simple variation of an A/D and D/A that can be easily constructed with discrete of-theshelf components. Here the charge pump is replaced with a voltage drive. The deviation from the linear behavior to an exponential one is particularly dominant as the voltages approach the rails, however if the D/A is built as an inverse of the A/D

then the non-linearity is negated. As can be seen the A/D is built around a single comparator and two transistors while the D/A uses only two transistors. The design of these converters is based on the maximum rate of change of the input signal. If an effective resolution of 'N' is required i.e. 'N' bit resolution in terms of multi-bit designs, the converter must slew between the two rails in N clock pulses. Analog in

+

BS out D

Q

− +V Qbar CLK

DFF

D/A were constructed out of standard components and assembled on a printed circuit board. An Agilent 54622D Mixed-Signal-Oscilloscope was used for measurements and data acquisition. 4.1.1 Summer The logical OR of two bit-stream effectively sums them. However this simple approach will loose bits when the bit density increases. By incorporating an accumulator this overflow is eliminated. The word width of this accumulator is, ideally, equal to the effective resolution of the bit-stream A/D. Fig 4 shows the structure of a two input bit-stream summer and Fig 5 plots the simulated results of adding two sinusoids S1 = 0.25cos(π20t) and S2 = 0.35 cos (π 20 t + π/4). zed Sum out S1

h

S2

l

Decode

n

n

+V

Accumulator Analog out

Fig. 4 Bit Stream Summer

BS in

0.4 0.2

Fig. 3 Simple Bit Stream Converters

← Output

0 −0.2

4 Control Elements With a collection of a few simple elements complex controllers can be implemented by interconnecting them. Each element is fully bit-stream i.e. the inputs are bit-streams and the outputs are bit-streams. Thus a complex network can be easily constructed. Each element has been, firstly, simulated and then implemented on a FPGA. At each stage several inputs, sinusoidal, square and triangular, were considered and the outputs compared with expectations. This collection of functional elements has been categorized into two libraries: primitives and tool-set. The primitive collection consists of much simpler structures with which functional elements like an inverter or an integrator can be constructed. The functional elements pertaining to the implementation of controllers are presented below. Active-HDL 5.1 was used for simulations, Quartus II was used for synthesis on the FPGA and Matlab for verification. Simulations also required test vectors that were created using C Programming Language. All bit-stream elements have been implemented on an Altera NIOS development board. This boards host a 20KE200 FPGA. The bit-stream A/D and

← S1 ← S2

−0.4 −0.6 −0.8 −1 −1.2

0

0.05

0.1

0.15 0.2 time, secs

0.25

0.3

0.35

Fig. 5 Adding Two Sinusoids

4.1.2 Gain/Attenuate To amplify a bit-stream by 'M', a generator produces 'M' positive quanta (a logic '1') for every positive quantum in the input bit-stream and similarly 'M' negative quanta (a logic '0') for every negative quantum received. The bit-stream structure of a gain element is similar to that of a summer. Attenuation is the inverse of amplification. 4.1.3 Inverter Fig 6 shows a bit stream inverter. Here the logic simply inverts the high and low bits and hence an accumulator is not necessary. zed Inv out S

h l

Fig. 6 Bit Stream Invertor

zed Integ out

h S

l

n Decode

n Acc.

BRG

Fig. 7 Bit Stream Integrator

Gain, dB

30 25 20 15 10 5 0 −5 −10 −15 −20 2 10

0.2 0.1

Output, volts

4.1.4 Integrator The process of integration is an accumulation of past values. In a bit-stream environment it is exactly the same. Here every input bit is stored in an accumulator. Since the accumulated value is a multibit word it is converted back into a bit-stream by a bit-rate-generator. Here too, the word-width is made equal to the effective resolution. To characterize this integrator standard frequency and time domain measurements were taken. Since a perfect integrator will saturate with small DC signals, the frequency domain measurements were taken with small sinusoidal signals. The frequency response is shown in Fig 8. A 20 dB/dec slope has been superimposed on the data points and it shows that the behavior is as expected. Alternatively, a unity feedback system around an integrator should result in a low-pass frequency response. With such a structure DC offsets do not pose any problems and hence large magnitude signals can be used. The results of the open-loop integrator were thus verified at large signal levels. In the time domain, an integrator should triangulate a square wave. The response of the bit-stream integrator to a square wave is shown in Fig 9. Again, the behavior is as expected.

0

−0.1 −0.2 −0.3 −5

0

5

10

15

time, sec

20 −3

x 10

Fig. 9 Time Response of Integrator

4.1.5 Approximate Differentiator This is a process of representing a change in the current value. If the effective resolution is 'N' then the current value of the input signal is obtained by accumulating the past N bits in a shift register. For every bit that is shifted in and shifted out, a count of the difference between the high and the low bits is maintained. This count then represents the instantaneous value of the input signal. The derivative of the input of the input can be computed by taking the difference between the current count and the previous count. Alternatively, by comparing the values of the in and out shifted bits the change can also be determined. In terms of FPGA resource usage this method could be 'expensive' as a long shift register is required. Again, a frequency response was determined and the behavior was as expected. The time domain behavior to a square wave and a triangular wave were also as expected but were quite noisy. An approximate derivative of the form ks/((s/p)+1) could be easily created using an integrator as shown in Fig 10 This form has the advantage that high frequencies are attenuated and hence the overall performance could be less susceptible to noise. The frequency and transient responses are shown in Fig 11 and Fig 12 respectively. The results are as expected. R(s)

C(s) +−

3

10

4

freq, r/s 10

Fig. 8 Frequency Response of Integrator

5

10

Integ

Scale Down

Fig. 10 Approximate Differentiator

transport lag adds some additional phase lag given by φlag=ω.Tlag. The phase response with this lag numerically removed is also shown in the Bode Phase response. The plots clearly show the system is conditionally stable with gain margin of ≈3.

0

Gain, dB

−5 −10 −15 −20

Detector

Heater

−25 2 10

Blower

3

4

10

5

10

10

Phase, deg

freq, r/s 90 80 70 60 50 40 30 20 10 2 10

Power Supply -

Control

Y

X

Output

+ S1

S2

Two-step Control

+ + A

B

External Input

External Control

Set Value

Fig. 13 Experimental Thermal Plant 3

10

4

5

10

10

Fig. 11 Frequency Response of Differentiator

Air Flow

4

Blower

3

Sensor

Heater External Controller

2

Output, volts

Bridge Circuit

Proportional Band

Continuous

Ref Input

1 0

Output A

B

Plant

−1 −2 −3 −4 −2

0

2

4 6 Time, ms

8

Fig. 14 Conceptual Diagram of Thermal Plant

10 −3

x 10

5

Fig. 12 Time Response of Differentiator

0 Gain, dB

−5 −10 −15 −20 −25

5 Bit-Stream Controllers

5.1 Thermal Plant The first system under consideration is a thermal plant simulator made by Feedback Instruments. It is shown in Fig 13. The plant consists of an air-blower which blows air through a tube. The air is heated at the blower end and its temperature is measured at the other end. The conceptual diagram of this plant is shown in Fig 14. The plants operating point can be set anywhere between room temperature and ≈50°C. The plant exhibits a second order behavior with a transport lag, Tlag, of 180 ms. Its Bode frequency response is shown in Fig 15. The

0

1

10

10

2

10

Freq,r/s 0 −50

Without transport lag

−100

Phase, deg

In this section, bit-stream cascade controllers for two laboratory scale systems are presented. Each system operates at different signal levels and hence additional interface circuits were constructed. Again, standard components were used except where accuracy is important. Small gain errors are still present but do not pose too much of a problem.

−30 −1 10

−150 −200 −250 −300 −350 −1 10

0

1

10

10

2

10

Freq,r/s

Fig. 15 Frequency Response of Thermal Plant

The simulator also comes with a separate PID controller that can be connected between terminals A and B shown in Fig 13 and Fig 14. The bit-stream and continuous controllers are connected between these two terminals so that their performances can be compared. The plant is set to operate at ≈35°C and is fed a square-wave that rapidly changes the operating point to ≈30°C and ≈40°C. The transient responses with the controllers under test are captured on a digitizing oscilloscope and DC offsets

have been numerically removed. Fig 16 compares the performances with Kp = 1 while Fig 17 that with Kp = 2. Since the gain margin is 3, the transient response with Kp=2 is significantly more underdamped than with Kp=1. The reduction of the DC offset or the steady-state error that naturally follows any increase in proportional gain is not directly seen in the plots. However, this equivalence can be seen by noting the change in output is greater with a proportional gain of two than with a gain of one. With Kp=1, the ratio of the change in output to the change in input is ≈0.5 while with Kp = 2 this ratio is ≈0.69. Both these are in accordance with theory i.e. 0.5 and 0.66 respectively.

A three term PID controller was also compared. Ziegler-Nichols' method was used to determine the coefficients. The inclusion of the integral term should remove the steady state error. The integral term also increases the oscillatory tendency which can be improved with the derivative term. The transient responses are compared in Fig 18. As can be seen the steady state errors are indeed much smaller, ≈0, than with a proportional controller. The transient responses of the continuous time and bitstream controllers are not identical simply because the coefficients cannot be matched to be identical. However, their overshoots and settling times are comparable.

1.5

5.2 Magnetic Levitation

1 0.5 0 Continuous

−0.5 −1

Bit−Stream

−1.5 −1 0 1 2 time, 3 4secs 5 6 7 8 9

Fig. 16 Step Responses with kp = 1 1.5 1 0.5 0

0.62 Continuous

−0.5

−0.75

−1 −1.5

Bit−Stream

−2 −1 0 1 2 3time,4secs 5 6 7 8 9

Fig. 17 Step Responses with kp = 2 2 1.5 1 0.5 0 Bit−Stream Controller −0.5 −1 −1.5 Continuous Controller −2 −2.5 −1 0 1 2 time, 3 4secs 5 6 7 8 9

Fig. 18 Step Responses with PID Controllers

The second system investigated is a magnetic levitation system, ML-EA from Extra Dimension Technologies. It consists of an electromagnet below which a magnetic cylinder is to be levitated. Gravity pulls the cylinder down while the magnetic force from the electromagnet pulls the cylinder up. The position of the cylinder is sensed optically. To reduce the power consumption, the manufacturer has placed additional permanent magnets in both the electromagnet and the cylinder. Such a system is inherently unstable. An analogue PID controller has also been provided. Unlike the thermal plant, a model of this system is much more difficult to obtain and hence the manufacturer provided model and controller were considered. The analogue PID controller does indeed levitate the cylinder however a comparison of the bit-stream and a (multi-bit) digital controller is presented. A multi-bit digital controller was implemented on a dSPACE DS1104 board in conjunction with Simulink (Matlab). The DS1104 is a PCI card that slots into a PC and hosts A/D, D/A and a Digital Signal Processor. The controller is 'built' in Simulink and downloaded on to the DS1104 which then implements this controller as software code. As with the thermal plant, the coefficients of the bitstream and dSPACE controllers were set to be similar. The cylinder was successfully levitated by both the controllers however the bit-stream controller does not completely damp-out a dominant (approximately) 10 Hz oscillation. In spite of this small oscillation, the cylinder remains levitated perpetually. The transient behaviors were compared by feeding a 1Hz square-wave which changes the set point i.e. the height of the levitated object. The resulting responses are plotted in Fig 19.

7

Bit−Stream Controller

6.5

Digital Controller

Position

6 5.5 5 4.5 4 3.5 3

1

1.5 time, secs

2

2.5

Fig. 19 Step Responses of the Magnetic Levitation System

The multi-bit digital controller clearly damps the 10 Hz oscillations however the bit-stream controller does not. This aspect has not yet been resolved however greater insight into this problem is expected when the model of this plant is determined experimentally.

6 Conclusion Controllers for SISO systems have been demonstrated. This technique can be extended to MIMO systems as well. The FPGA resources consumed are quite small thus larger or more complex controllers could be implemented. Implementation on digital signal processors requires real-time issues to be clearly resolved. Since bitstream controllers are truly parallel, real-time 'execution' is guaranteed as long as the design can be fitted on the FPGA. Usually the outputs of controllers drive a power device i.e. a heater element or electromagnet. The bit-stream output can be easily modified into a pulse-width-modulated, PWM, signal at a suitable frequency. PWM drivers are more power efficient and hence a bit-stream solution could further improve the design. References: [1] K. Ogata, Discrete Time Control Systems, 2nd ed. New Jersey: Prentice Hall, 1995. [2] M. A. Sartori and P. J. Antsaklis, Implementations of learning control systems using neural networks, IEEE Control Systems Magazine, 1992. [3] A. Ohta, T. Isshiki, and H. Kunieda, A new fpga architecture for high performance bit-serial pipeline datapath, IEICE Trans. Fundamentals, 2000. [4] J. Mick and J. Brick, Bit Slice Microprocessor Design. New York: McGraw Hill, 1980.