An Approach to Computer Simulation of Bonding and Package Crosstalk in Mixed-Signal CMOS ICs Gabriella Trucco, Giorgio Boselli, Valentino Liberali Dept. of Information Technologies University of Milano 26013 Crema, Italy
[email protected],
[email protected],
[email protected] ABSTRACT This paper presents an approach for simulation of mixed analog-digital CMOS integrated circuits, aiming at estimating crosstalk effects due to current pulses drawn from voltage supplies. A simple expression of voltage and current in the pull-up and the pull-down of a CMOS logic gate is derived, and a representation of digital switching noise in time domain can be easily calculated through a dedicated computer program. This representation is used to perform an analog simulation using SPICE, to evaluate the propagation of the switching noise through the parasitic elements of the package and of the bonding wires. Simulation results for two case studies are presented.
Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids—simulation
General Terms Design
Keywords Crosstalk, mixed-signal ICs
1.
INTRODUCTION
In mixed analog-digital integrated circuits, effects of digital switching noise on the analog section are often the limiting factor affecting the overall system performance [2]. Therefore, analog designers must choose optimum circuit architectures taking robustness and crosstalk immunity into account. Hence, a correct design methodology should account for digital switching noise from early stages of the design process. ∗This research has been partially supported by the Italian na-
First of all, a realistic model of interconnection parasitics must be adopted for simulations. This aspect is discussed in Sect. 2. Then, a fast but accurate analysis of current consumption during logic transitions is required, to evaluate the noise due to the switching activity of digital cells [4]. Digital simulation tools are mostly optimized for simulation speed and for “average” power consumption. On the other hand, analog simulators are quite inefficient for the analysis of large digital circuits. Therefore, we propose a dedicated simulation method to analyze the current consumption in the digital part of the circuit. To this end, suitable simplified models of active devices are required: in particular, we need to consider all relevant aspects to obtain sufficiently accurate results, and we wish to neglect all issues that do not contribute to a remarkable improvement, in order to keep simulation time reasonably small [3]. It is well known that circuit-level (SPICE/SPECTRE) simulation for large digital circuits is very time-consuming. Dedicated algorithms can be more efficient, although they can be applied only to a specific class of circuits. In the case of mixed analog-digital circuits, we can speed up simulation by analyzing the digital and the analog sections separately, as illustrated in Fig. 1. A dedicated algorithm, described in Sect. 3, evaluates the supply currents iDD and iSS drawn by the digital part, and saves a piece-wise linear (PWL) description of current waveforms. In Sect. 4, the current waveforms are used as an input for subsequent simulation of the analog section of a mixed-signal circuit. This approach
INPUT STIMULI
DIGITAL CIRCUIT
ANALOG CIRCUIT
Dedicated algorithm
tional program FIRB, contract no. RBNE01F582. iDD(t), iSS(t) (PWL)
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SPICE/ SPECTRE
OUTPUT
Figure 1: Flow diagram of the proposed approach.
CGND1
iDD
VDD (external)
VDD L K
L
R C1,2
R
(on-chip)
K
v(t) vs
CGND2
Figure 2: Equivalent circuit for digital switching noise. is applied to two blocks used in radio-frequency front-end ICs. The first circuit is a pipeline analog-to-digital converter (ADC), which includes a two phase clock generator acting as digital noise source, and a flash ADC based on resistive string affected by digital disturbances. The second circuit is a voltage-controlled oscillator (VCO), also affected by the disturbances coming from the clock generator.
L
i/2 i i/2
L
K K
2.
MODEL FOR BONDING AND PACKAGE PARASITICS
Package effects cannot be neglected in an accurate mixedsignal IC design. Indeed, parameters associated to the package severely affect the stability of bias voltages; in particular, bondwire and pin parasitic resistance, inductance and capacitance constitute an RLC network which can cause the internal supply voltages to be significantly different from external voltages. Moreover, mutual inductance and cross-capacitance between bondwires cause electromagnetic coupling between digital and analog supplies. Therefore, the advantage of kelvin ground for substrate bias vanishes, as disturbances due to digital switching currents propagate through mutual inductances and cross-capacitances. To evaluate effects of such parasitic elements, a suitable model has been developed. Fig. 2 illustrates a simpified model of bonding and package parasitics for two adjacent wires [7]. The instantaneous current iDD due to digital switching of logic gates produces a voltage drop, which affects the on-chip digital supply VDD , and propagates to the adjacent wires through both capacitive coupling due to the capacitance between wires C1,2 and inductive coupling due to the mutual inductance represented by K. Therefore, the analog on-chip voltage v(t) is no more equal to the external voltage vs , but it results to be a function of the voltage vs and of the digital switching current iDD and its derivative:
v(t) = f
diDD vs , iDD , dt
.
(1)
Multiple bonding is often used to reduce effects of parasitic inductance. Indeed, two bondwires in parallel allow us to halve parasitic inductances and resistances (L and R in Fig. 2). However, it is easy to see that parallel bondwires do not reduce coupling between wires: from Fig. 3, we can
L Figure 3: Inductances of two bondwires in parallel and mutual inductances with respect to third wire. notice that parallel bonding reduces the series inductance of the interconnection to L/2, but its effect on neighboring wires is exactly the same as the effect of a single bondwire. From these considerations, it is apparent that an accurate analysis of a mixed-signal circuit must account for parasitics. To this end, we have derived a model for a TQFP64 (64-pins thin quad flat pack) package. For each one of the 64 pins, we considered parasitic coupling with the nearest four wires on both sides. This results in a SPICE subcircuit containing about 1200 parasitic elements, which was used to perform time-domain simulations.
3.
TIME-CONTINUOUS SIMULATION OF SWITCHING CURRENTS
A dedicated simulation algorithm was written in C++, to analyze current waveforms in digital circuits using timecontinuous functions, instead of sample sequences, to represent signals. The advantages of this approach are: better accuracy in the calculation of derivatives, pre-layout switching noise estimation, and faster simulation speed compared to a circuit-level simulator. Accurate calculation of derivatives is important, as voltage drops due to bonding inductances represent a major source of crosstalk in mixed-signal systems. In our analysis of the digital switching in CMOS logic cells, the pull-up and the pull-down branches of logic gates are modeled either as current generators (MOS transistors
clk ph1
ph2
Figure 5: Circuit of the two phase clock generator. in the saturation region) or as resistive switches (MOS transistors in the triode region), in order to keep the complexity of the network at an acceptable level. The analysis method is similar to the one described in [1]. The overall simulation time is divided into time slices, depending upon input signal variations and the operating region of pull-up and pull-down MOS devices. Within each time slice, time-continuous functions describing the output voltage vout (t) and the supply currents ip (t) (through the pull-up branch) and in (t) (through the pull-down branch) are calculated. When the operation region of a digital cell changes, an event is generated and all the digital cells are analyzed again. At any time slice, the operating condition of the pull-up and the pull-down branch of each cell is determined. The output voltage vout (t) and the currents drawn from the positive and the negative supply (iDD (t) and iSS (t), respectively) are calculated as a function of the input voltage vin (t). The use of a simple model for active elements ensures that a closed-form expression exists. Under the above assumptions for the models of MOS transistors, when piece-wise linear external inputs are applied, all signals at the output of digital gates can be expressed in the form: v(t) =
X
−αi t
pi (t) · e
(2)
where pi (t) is a real polynomial function in t and αi is a real quantity (the inverse of a time constant). As an example, let us consider the case of a CMOS inverter having the NMOS transistor working in the saturation region and the PMOS transistor in the triode region; this occurs when VSS + Vth,n < vin (0) < VDD + Vth,p and vin (0) − vout (0) < Vth,p . Fig. 4 illustrates the simplified model used for the analysis. The current through the NMOS transistor is: in (t) = Kn · (vin (t) − VSS − Vth,n )2
, with usual meaning of symbols. where Kn = Assuming that the PMOS transistor in the triode region can be approximated by a resistance rp constant over the time interval [0, tmax ], the output voltage can be obtained from the differential equation: dvout (t) + vout (t) − VDD + rp in (t) = 0 dt where CL is the capacitive load. The solution is: rp C L
− r tC
vout (t) = v0 e +e
L
L
1 CL
− r tC p
+
p
Z
t 0
ip (t) =
VDD
VDD rp vout
vout
CL VSS (a)
t VDD − in (t) · e rp CL dt rp
(4)
(5)
The current through the PMOS transistor is:
i
vin
(3)
1 µ C W 2 n ox L
in
CL VSS (b)
Figure 4: CMOS inverter: (a) schematic diagram; (b) simplified model with NMOS in saturation and PMOS in triode.
VDD − vout (t) rp
(6)
If the input voltage vin (t) is expressed in the form (2), a closed form solution for voltages and currents can be calculated. For the cascade configuration of logic cells, the output of any gate is used as the input for the next one. After calculating the output voltage, we also need to determine the maximum time tmax for which the computed solution is valid: tmax is the time instant until which no change occurs in the operation region of any device in the circuit. The average on-resistance of a MOS transistor in triode region, r, depends on its gate-to-source voltage vGS and, therefore, on its input voltage, through the relationship: r=
1 K |vGS − Vth |
(7)
where the drain-to-source voltage vDS has been neglected with respect to the gate-to-source voltage vGS . A more detailed description of the algorithm can be found in [9].
ital section has been modeled with two PWL current generators, which generate periodical time-domain current waveforms iDD and iSS , as shown in Fig. 6. Parasitic elements due to the TQFP64 package are included, as described in Sect. 2.
−3
x 10
2
iSS
1.5
4.1
Current (A)
1
Effects of Crosstalk on an ADC
The first circuit is a pipeline ADC, whose architecture is shown in Fig. 8 [8]. Each pipeline stage contains the flash ADC shown in Fig. 9.
0.5
0
D1 bits
−0.5
iDD
−1
300
400
500
600
700
800 Time (ps)
900
1000
1100
1200
R
R
...
...
Dk bits
R
1300
Vin
Figure 6: Current consumption of the two phase clock generator.
Di bits
stage 1
Vi
Vk
stage i
+
0.6
+
VSS, noise
S/H ADC
0.4
stage k
-
2 Di
DAC Di bits
Voltage (V)
0.2
Figure 8: Architecture of the pipeline A/D converter.
0
−0.2
VDD
−0.4
V
300
400
500
600
700
800 Time (ps)
900
vin
VBG
DD, noise
1000
1100
1200
1300
Figure 7: Switching noise due to inductances on power supply lines. The proposed algorithm has been used to simulate the two phase clock generator illustrated in Fig. 5. Currents and switching noise due to series inductances are shown in Figs. 6 and 7, respectively. The time-domain current waveforms in Fig. 6 are in good agreement with the result obtained with a SPECTRE simulation [10]. To obtain the switching noise waveform shown in Fig. 7, the currents calculated assuming ideal supply lines (Fig. 6) were injected into the respective inductances (LSS = LDD = 5 nH).
4.
ANALYSIS OF CROSSTALK THROUGH PARASITICS
To evaluate the effects of switching currents on analog circuits, we have considered two case studies: a pipeline ADC and a VCO. Both circuits have been simulated with SPICE. The analog part has been described at transistor level, while the dig-
VSS Figure 9: Schematic diagram of the flash ADC.
2.515V
VDD
Vc v1
2.485V VDD
v2
15mV
-15mV 0s
0.2ns
0.4ns
0.6ns
0.8ns
1.0ns
VB
1.2ns
VSS Time
Figure 10: Simulated on-chip values of VDD and VSS in the flash ADC.
Req v1
v2
Vc VSS (on chip)
Cj,w Rsub
p-well buried n-well
Cj,b
p-substrate
Figure 12: Model for propagation of digital noise to the VCO through interconnections and substrate. −3
3
x 10
2 iSS
1 0
−1 iDD
−2 −3 3000
Effects of Crosstalk on a VCO
We have investigated the effects of crosstalk on a VCO, which is the most critical block in a PLL-based clocking system [5]. The schematic diagram of the VCO is illustrated in Fig. 11 [6]. The VCO frequency is tuned by adjusting the voltage Vc , which controls the gate-to-channel capacitance of the two MOS transistors. To reduce the effect of digital disturbances, the VCO has a fully-differential structure and the output signal is differential: v1 − v2 . Since the digital switching noise is a common mode signal, the differential output should not be affected, provided that the differential structure is perfectly matched. However, the control voltage of the VCO (Vc ) is affected by switching noise, which propagates through interconnection parasitics and through the substrate. Fig. 12 shows a simplified model for the coupling mechanism. The voltage Vc is generated by the charge-pump and the loop filter
Cc
VSS (external)
3500
4000
4500
5000
5500
1.5 with digital switching noise 1 sign(v1 − v2)
4.2
charge pump + loop filter
Digital switching current [A]
The sample-and-hold (S/H), the digital-to-analog converter (DAC) and the residue amplifier are synchronized with a two phase clock generated by the circuit in Fig. 5. We have simulated the flash ADC including the effects of the switching currents through all parasitics associated to bonding and package. Values of parasitic elements used in simulation are: inductance L = 2.5 nH, resistance R = 50 mΩ, ground capacitance CGND = 15 fF, capacitance between wires Ci,j = 5 fF, mutual inductance coupling factor K = 0.2. Fig. 10 shows the on-chip supply voltages waveforms of the analog section (nodes VDD and VSS in Fig. 9). From the waveforms in time domain, we can see that on-chip analog supplies are affected by digital noise and display a “bouncing” effect with a peak value larger than 10 mV. Moreover, from Fig. 10 we can see that the bouncing effect continues after the current in digital blocks has returned to zero. Indeed, the oscillation period is dependent on parameters of the parasitic RLC network. As a consequence, the common clocking strategy, consisting in sampling the analog input signal during “quiet” intervals of the digital section, becomes useless. The bouncing effect limits the resolution of the pipeline ADC to 8 bits, irrespective of analog sampling instants.
Figure 11: Schematic diagram of the VCO.
0.5 0
−0.5 −1 without digital switching noise −1.5 3000
3500
4000
4500 Time [ps]
5000
5500
Figure 13: Sign of the differential VCO output voltage with and without digital switching noise. in the PLL. Electromagnetic coupling through bonding and package parasitics affects the on-chip VSS voltage, and the substrate is no more held at a constant voltage. Since the
substrate is capacitively coupled with the well of the MOS transistors used for tuning, part of the high-frequency digital switching noise is injected into Vc . As a consequence, the VCO output signal is affected by phase noise. Fig. 13 illustrates the polarity of the differential VCO output v1 − v2 , with and without the noise due to the digital switching current. The effect of switching noise is apparent: it delays the zero-crossing instants of the VCO signal, thus modulating the VCO phase.
5.
CONCLUSION
This paper has presented a method for the analysis of the effects of digital switching noise on analog circuits. A model for bondwires and package parasitics has been described. Besides series inductances and resistances of the interconnections, also coupling between neighboring wires can be harmful for accurate analog circuits. The effects of both capacitive and inductive coupling between bondwires have been considered for a TQFP64 package. A dedicated algorithm for the calculation of digital switching current in time domain has been used to obtain current waveforms within the digital section of a mixed-signal circuit. Current waveforms can be used as an input for SPICE analysis of the analog section, to evaluate the performance degradation of analog circuits due to bondwires and package parasitics. Our analysis indicate that disturbances due to switching currents in digital blocks propagate through interconnection parasitics, and affect analog voltages, including the substrate bias voltage, even when kelving ground interconnection is used. Simulation results on an ADC and on a VCO demonstrate that switching noise can severely degrade circuit performance. Therefore, digital switching effects must be carefully considered when designing accurate analog circuits. Reduction of interconnection parasitics is essential in mixed-signal high-frequency circuits, such as radio-frequency front-ends. Therefore, it is expected that mounting technologies without bondwires (e.g., flip chip mounting) will be more and more popular in the next future for mixed-signal integrated systems.
6.
REFERENCES
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