Encoders & Decores from the web DASYGENIS Minas
Introduction
An online tool to design custom optimized encoders and decoders
Related Work Our Tool Experimental Results Conclusions
Minas Dasygenis
[email protected] Department of Informatics and Telecommunications Engineering University of Western Macedonia, Kozani, Greece Presentation is delivered by: Mrs Tsourma Maria, Dipl. Eng
EUC2016 1
Presentation Outline Encoders & Decores from the web
●
Introduction & Motivation
●
Related work
Introduction
●
Tool architecture
Related Work
●
Experimental results
●
Conclusions & Future work
DASYGENIS Minas
Our Tool Experimental Results Conclusions
EUC2016 2
Encoders and Decoders are utilized in every programmable architecture Encoders & Decores from the web
●
Encoders are mostly used: –
DASYGENIS Minas
Introduction Related Work Our Tool Experimental Results Conclusions
EUC2016 3
●
Detection of hardware interrupts. Every peripheral is connected with a bit line to the interrupt controller, and the interrupt controller encodes these inputs to a multibit line and transmits these to the processing core for interrupt handling.
Decoders are mostly used: –
Register file → Bank of memory locations. The distinction of what memory should be written is done by a decoder block.
–
Random Access Memory → Each RAM consists of multiple row and column decoders that operate in parallel memory bit planes. The number of parallel row or column decoders defines the bitwidth of the RAM For example, a 32x32 bitwidth RAM could be implemented with a decoder to select one of the 32 rows and a decoders for the appropriate columns.
Encoders and Decoders are utilized in every programmable architecture Encoders & Decores from the web DASYGENIS Minas
Introduction Related Work Our Tool Experimental Results Conclusions
EUC2016 4
Decoder is used in RAM
Decoder is used in Register File
Encoders and Decoders are utilized in every programmable architecture Encoders & Decores from the web DASYGENIS Minas
Introduction
Encoders are used in handling the interrupt request of peripherals with priority
Related Work Our Tool Experimental Results Conclusions
EUC2016 5
CPU
IRQ
n
0
Peripheral 1
priority 1 encoder
Peripheral 2 ...
n
Peripheral N
Fundamental encoder and decoder types Encoders & Decores from the web DASYGENIS Minas
●
Encoder (2n → n) –
Introduction Related Work
Priority: Accepts inputs with multiple ‘1’ and outputs the binary representation of the highest value. in3 in2 in1 in0 out1 out0 V ● 0 0 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 1 –
Our Tool Experimental Results Conclusions
EUC2016 6
Normal: Accepts 2n inputs with only one ‘1’ and the rest ‘0’, outputs the binary representation n. It has a valid output to report the validity of the input (e.g. if more than one ‘1’ exist in input the output is invalid).
Fundamental encoder and decoder types Encoders & Decores from the web DASYGENIS Minas
●
Decoder (n → 2n) –
Normal: Break the combination of inputs to a set of values that have no activation (‘0’) except one that is active (‘1’).
–
Inverted: Implemented using NAND gates, inverted operation (not activated outputs bear ‘1’, with the one activated value to have ‘0’).
Introduction Related Work Our Tool Experimental Results Conclusions
EUC2016 7
in1in1 0 0 0 0 1 1 1 1
in0 in0 00 11 00 11
out3 out3 00 00 00 11
out2 out2 00 00 11 00
out1 out1 00 11 00 00
out0 out0 11 00 00 00
Encoders & Decores from the web DASYGENIS Minas
Introduction Related Work Our Tool Experimental Results Conclusions
EUC2016 8
Our tool creates all types of encoders and decoders IP blocks We present a public web accessible tool that designers accepts a number of user parameters and creates an IP block of an optimized encoder or decoder and a random generated test bench.
Our tool is fully parametrized Encoders & Decores from the web
The inputs to our tool are:
DASYGENIS Minas ●
Introduction Related Work
●
Our Tool Experimental Results Conclusions
EUC2016 9
Types of IP blocks –
Normal or priority encoders
–
Normal or Inverted decoders
Design parameters –
Maximum available inputs per gate
–
Insertion or not of input latches
–
Insertion or not of output latches
–
Insertion of not of enable module input
–
Degree of pipelineability
●
The number of requested test vectors
●
Creation of a schematic or not
Our web tool is user friendly Encoders & Decores from the web DASYGENIS Minas
Introduction Related Work Our Tool Experimental Results Conclusions
EUC2016 10
The automation of decoders and encoders is very important Encoders & Decores from the web
●
DASYGENIS Minas
Introduction
●
Related Work Our Tool Experimental Results Conclusions
EUC2016 11
●
●
Rapid design space exploration requires the automation of HDL circuits. Designing by hand is a very complicated process, which cannot be automated with GENERIC constructs. These IP blocks are used in every modern programmable architecture. Automation allows fast design space exploration for evaluating circuits methodologies that make use of them.
Our tool is the first to provide such functionality
Encoders & Decores from the web
●
DASYGENIS Minas
●
Introduction Related Work ●
Our Tool Experimental Results
●
Conclusions ●
EUC2016 12
IP block generators from major EDA vendors (Altera, Xilinx, Mentor, etc) do not provide a custom design capability for encoders and decoders. Nobody until now has published a tool (local execution or web execution) to create parametrized HDL descriptions of these. The most related tool is EUDOXUS web tool from D. Bakalis, 2006 but it does not create decodes/encoders. Also, Flopoco from Florent de Dinechin designs Ip cores, but not decoders/encoders. There are tools to create HDL codes from High level synthesis, but they do not provide the granularity required for encoders and decoders.
Our tool architecture has a frontend and backend Encoders & Decores from the web DASYGENIS Minas
Introduction Related Work Our Tool Experimental Results ●
Conclusions
●
EUC2016 13
Frontend –
User input form.
–
Input validation.
Backend –
IP block generator.
The frontend parses the input and feeds the backend with data Encoders & Decores from the web
●
Presents the user input forms.
●
Validates the data.
DASYGENIS Minas
Introduction
●
Related Work ●
Our Tool ●
Experimental Results Conclusions
EUC2016 14
Performs sanitization of user inputs (for web security) Creates the input string for the backend. Executes python code with that input string.
The backend uses a number of modules Encoders & Decores from the web
●
DASYGENIS Minas
Introduction Related Work
●
Our tool has a modular structure. It consists of three major components. –
(1/3) Decoder/Encoder aHDL generator.
–
(2/3) HDL generator.
–
(3/3) Test bench Generator.
Our Tool Experimental Results Conclusions
EUC2016 15
IP
Decoder/encoder
(1/3) The first module creates the encoder/decoder aHDL netlist Encoders & Decores from the web
●
DASYGENIS Minas
Introduction Related Work
●
●
Our Tool Experimental Results Conclusions
EUC2016 16
●
This module creates the intermediate net list format aHDL (abstracted HDL). Uses a number of reductions, until output connections have been formulated Creates gradually all the iterations (~operational cycles). Inserts appropriate gates (AND/NAND/not etc) and D-flip-flops at appropriate positions of the 3D-netlist. The abstracted HDL net list format is a 3D net list, where components are placed in nodes. Every node carries a number of input vectors.
(1/3) The aHDL module is optimized Encoders & Decores from the web DASYGENIS Minas
●
The module creates a sophisticated gate tree for every decoder/encoder design: –
The number of inputs define the number of bits that take part in the formulation of every output and require bitwise operations on this number of bits. The user selects the max number of inputs per gate in order not to use large multi-input gates that have large fan in, are area and energy inefficient and pose significant latency.
–
Our tool inserts as many gates as necessary (max gate inputs) respecting dependencies.
–
Stray bits are handled using heuristics:
Introduction Related Work Our Tool Experimental Results
●
Conclusions
●
EUC2016 17
–
If gate has been added in this iteration leave stray bit for next iteration. Otherwise, connect them to a gate with neutral unused inputs (either ‘1’ or ‘0’ depending on the gate).
Performs correct cascade of gates (cascading OR is different than NAND which reverses output).
(1/3) The aHDL is pipeline parametrizable Encoders & Decores from the web
●
DASYGENIS Minas
Introduction Related Work
●
●
Our Tool Experimental Results
●
Conclusions ●
EUC2016 18
An important parameter is the level of pipeline The pipeline level specifies every how many logic levels a pipeline latch is inserted. If the user has defined pipeline level 0, then no pipeline is used. if the user specified pipeline level 2, then every two gates, a pipeline latch is inserted and so on. We are using pipeline D flip-flop latches in a master-slave configuration, in order to ensure the correct timings.
(1/3) The aHDL computes correct timing on multiple paths Encoders & Decores from the web
●
DASYGENIS Minas
Designing encoders/decoders is difficult, especially when clocked elements are used. –
Introduction Related Work Our Tool
●
Our tool correctly handles all these problems as follow: –
it creates a directed graph of every sub-circuit that must be of equal delay and computes all paths from every input to every output, taking into consideration the encountered clocked elements.
–
All the sub-circuits are equalized by appending the correct number of D flip-flops to the outputs.
–
Every clocked module has outputs synchronized and placed simultaneously at the I/O buffers.
Experimental Results Conclusions
EUC2016 19
There are multiple outputs computed from independent computational paths, all outputs paths must have equal latency.
(2/3) The HDL generator Encoders & Decores from the web
●
DASYGENIS Minas
Introduction Related Work
●
Our Tool ●
Experimental Results Conclusions ●
EUC2016 20
The HDL generator is a generic engine developed at our laboratories, that accepts a aHDL structural netlist description and outputs a syntactically correct VHDL. It performs a number of safety checks to ensure that the output VHDL is correct. It has been used to synthesize various components (see http://arch.icte.uowm.gr/hdl). It is used for more than 3 years.
(3/3) The test bench generator creates parametrized random vectors Encoders & Decores from the web
●
DASYGENIS Minas
Introduction Related Work Our Tool Experimental Results Conclusions
EUC2016 21
●
The last module is the test bench generator. For the number of test vectors requested by the user the following is repeated: –
Creates a random number for every input.
–
Computes the correct output.
–
Inserts the signal assignment for the input vectors, the wait statement for the result to be computed and the assert statement to test the output.
(3/3) The created test bench file allows automatic verification Encoders & Decores from the web
●
DASYGENIS Minas
Introduction Related Work Our Tool Experimental Results Conclusions
EUC2016 22
●
●
The generated code can be compiled and simulated. The designer is not required to check manually the outputs. In the simulation the messages OK or FAIL will be reported.
-- input vector: 49 signal0
