CFSMcharts : A New Language for Microprocessor ... - Semantic Scholar

CFSMcharts : A New Language for Microprocessor Based System Design Partha S. Roop A. Sowmya School of Computer Science and Engineering The University of New South Wales Sydney, NSW 2052, AUSTRALIA proop,[email protected]

Abstract

Component-based design is a well known engineering design method that uses prefabricated components with known properties to design larger systems. We propose a new language called CFSMcharts for component-based design of microprocessor based systems. In this domain, there exists a vast library of programmable devices, which may be used during design synthesis for cheap bulk production of these systems. However, the use of these components during design synthesis is still low-key. CFSMcharts will alleviate the above problem by encouraging the use of programmable components during design synthesis. The language is an extension of CFSMs [11] proposed recently to model the behaviour of programmable components. We also propose a formal semantics of the above language based on the concept of Sequence Function Trees (SFTs).

1 Introduction

Microprocessor (MP) based systems are normally designed by experienced designers using a microprocessor together with a set of programmable hardware and software components. In this domain, there exists a vast library of programmable components, and the use of these components in design helps in substantial cost reduction. However, the use of these components in the automated synthesis task is still low-key. One of the principal reasons is the complexity involved in modelling and understanding the behaviour of these devices. A second reason is the lack of a speci cation language that can easily model and reason about these devices. However, the idea of using pre-designed and developed components has been successfully tried in other domains e.g, in the domain of large distributed real-time systems this is termed as component-based design [8] where prefabricated components with known properties are used in building larger systems. The

main objective of this paper is to introduce a new formalism that encourages component-based design of microprocessor based systems. Recently, Mitra et al. [11], have proposed a new FSM model, called Composite Finite State Machine (CFSM), that is well suited to modelling microprocessor programmable components. Many programmable components have data registers and support operations on them. Representation of the behaviour of such devices as single sequential FSMs will require a huge number of states. Other available methods of state reduction such as the EFSM model [4] and Statecharts [5] are not considered as they cannot be used easily to test the implementability of a design function by a suitable device. Interested readers are referred to [11] for a more detailed comparison of the CFSM model to other reduced FSM models. A CFSM consists of a number of constituent machines, operating concurrently and communicating with each other. One of these constituent machines is termed as the primary machine (PM), and represents the abstract functional behaviour of the overall CFSM. The other constituent machines are called subsidiary machines (SMs), which handle data and memory operations only. The PM is represented by a state transition graph (STG) whereas the SMs are represented as the names of the functions they perform. The operational semantics of every constituent machine of a CFSM is based on the synchrony hypothesis [1]. Every state transition arc in the PM is labelled by a triplet e[c]=a where e is an event that triggers the transition, c is a set of guard conditions that enables the actual ring of the transition, and a is a set of actions that are executed by the PM before entering the next state. Though ideal for modelling the behaviour of programmable components, CFSMs were not proposed as a speci cation language. Speci cally, it lacks composition operators, which are essential for modelling com-

posite design speci cations. In this paper, we propose the CFSMcharts language, that uses CFSMs as the basic building blocks and thus encourages componentbased design of MP based systems. We also propose a formal syntax and semantics of the language based on the concept of Sequence Function Trees (SFTs) proposed by Yodaiken [15], which are essential for formal veri cation. We can think of three distinct design levels of varying complexity, namely circuit level, board level and systems level. We are targeting the board level design of MP based systems. Hardware description languages such as VHDL [7] and other formalisms such as Orbital nets [13] are suitable for speci cation acquisition at the circuit level. Other state-based languages such as in [1, 5, 9, 12, 10] are more appropriate for acquiring speci cations at the systems level. Statecharts [5] is one of the pioneering languages in this family, and is an FSM extension with features such as concurrency, depth and broadcast communication. Some Statecharts variants such as SPecCharts [12] and SPeX [10] were proposed for acquiring embedded systems speci cations. The former is based on the concept of program state machines. The latter has data and control ow in the same language. It is a perfect language for microprocessor based systems, except that it requires a knowledge base to re ne the nodes of the speci cation to a speci c level of detail. Many of these languages are not suitable for board level component-based design, which requires the modelling of component behaviours as part of the speci cation. Since many components have memory and support operations on memory, these languages require either a huge number of states to encode the memory operations or use variables. This will make it very expensive to test the implementability of a given design function by a set of components, while trying design synthesis. Hence the need for a new speci cation language. The organization of the paper is as follows : Section 2 will discuss the main features of the CFSMcharts language along with a modelling example in this language. This section will also present the formal syntax and semantics of the above language. Section 3 will be devoted to the behaviour mapping algorithm for CFSMcharts and some results of mapping will be presented. The nal section will be devoted to conclusions.

which we support behavioural hierarchy and a parallel composition operator; the leaf level behaviours of this language are CFSMs. In this paper we propose a bottom up syntax of CFSMcharts which is inspired by the bottom up syntax proposed for Statecharts by Hooman et al. [6]. However, no OR operation is supported between any higher level states except the leaf states of a CFSM mainly because we are trying to model a system composed of a set of devices which are operating concurrently. Thus, a CFSMcharts is basically a parallel composition of a set of CFSMs. Since a CFSMchart is a parallel composition of a set of CFSMs, some mode of communication and synchronisation has to be chosen. We adopt the synchronous broadcast mechanism proposed by Berry [1] which assumes that events generated in any of the parallel components are broadcast instantaneously throughout the system and can be sensed by any of the parallel components. Since we are attempting small board level designs using a microprocessor and a set of programmable components, such an assumption is quite plausible. Before presenting the formal syntax and semantics of our language, we will illustrate its features by the following example.

2.1 Example

This example describes the modelling of an analog to digital converter using an up-counter, a digital to analog converter(DAC) and a comparator in the CFSMcharts language. The speci cation of the ADC is given in Figure 1. The CFSMchart of the ADC is a parallel composition of three CFSMs namely that of an up-counter, a DAC and a comparator. Conversion process is initiated by giving a START signal to the counter to initiate counting. The counter outputs the count value at every CLK transition and this output is subsequently converted to an equivalent analog value by the DAC. This analog value (output of DAC) is compared by a comparator with the analog value speci ed for conversion. If they are not equal then the cycle just repeats. Otherwise, a STOP signal is generated for the counter to stop counting and the output generated at that instant is the digital equivalent of the analog input. There is a default start state in every CFSM and a name is speci ed for every parallel component that indicates the functionality being modelled by a particular CFSM. Being in any of the parallel components implies being in all the parallel components simultaneously. Moreover, exiting a parallel component results in the forced exit from all other components parallel to this component. Structuring of states by

2 The CFSMcharts Language

CFSMs are incapable of modelling composite functionality since they lack composition operators. The CFSMcharts language is an extension of CFSMs in 2

Stati cation: Stat(U,Super) - Makes Super a super state with U inside it, where U denotes a CFSMchart or any basic CFSM. Parallel Composition: ParallelComp(U1,U2) Makes U1 and U2 two parallel components of the CFSMchart where U1 and U2 are also CFSMcharts. Based on the above de nitions, the formal syntax of CFSMcharts is given below in BNF notation. CFSMChart ::= Default j ParallelComp(Default; CFSMChart) Default ::= Stat(Basic; Super) j Stat(CFSMChart; Super) Basic ::= B

ADC UP COUNTER a2 a4 a1

a3

EDGE LABLINGS DATA I/P : CLK CONTROL I/P : START, STOP a1 : START / init(S1) DATA O/P : OUT a2 : CLK+ / OUT=S1 CONTROL O/P : a3 : STOP / OUT=S1 SMs : S1 : no-of(CLK+) a4 : ε

DAC

DATA I/P : DIN (OUT) CONTROL I/P : DATA O/P : AOUT CONTROL O/P :SMs : S2 :Analog_Val(DIN)

A1

EDGE LABLINGS A1 : OUT / AOUT=S2 A2 : ε

A2

2.3 Semantics of CFSMcharts

COMP

We propose a denotational semantics of our language based on the concept of Sequence Function Trees (SFTs) proposed by Yodaiken [15]. The original de nition of SFTs were based on the feedback product of Moore machines. Since we are dealing with CFSMs, which are a form of Mealy machines, we have proposed a modi ed SFT de nition. In our semantics, a CFSMchart will be denoted by an equivalent SFT and each CFSM will be denoted by its equivalent sequence function. The following is a de nition of sequence functions and SFTs used for the proposed semantics.

a3 a1

a4

a2

DATA I/P : INP1(AOUT), INP2 CONTROL INPUT : DATA O/P : CONTROL O/P : EQ, NEQ EDGE LABLINGS a1 : AOUT(INP1=INP2)/STOP=1 a2 : AOUT(INP1INP2)/CLK=1 a3 : ε a4 : ε

Figure 1: CFSMchart of ADC using up-counter, DAC, comparator a superstate-substate relation is thus supported implicitly. Moreover, by the instantaneous broadcast assumption, actions/events originating in one component are made available instantaneously in other parallel components.

2.3.1 De nition of SFT

Before presenting the formal de nition of SFTs we will rst describe their intuitive meaning. A sequence function modelling a CFSM is basically a map from a set of inputs to a given set of outputs. In other words given a sequence of inputs to a CFSM (a sequence of events and conditions), a sequence function models the outputs produced by the CFSM. An SFT models the behaviour of a system which is a parallel composition of a set of n subsystems. Let the sequence functions of the corresponding subsystems be denoted by T1 to T . The function h denotes the input map for each T , which is used to compute a sequence of inputs for the T when the composite system is given particular input. The function g is the output map that combines the outputs of each T to produce the system outputs. Thus, an SFT can be treated as a tree structure with the root node denoting the SFT of the entire system and the leaf nodes being the sequence functions corresponding to the black-box components.

2.2 Formal Syntax

The primitive objects of our syntax are the CFSMs modelling individual functionalities. We shall call them basic CFSMs, as de ned below:

De nition 1 :

Basic CFSM B is a tuple, B = (A,X,S,start,,) where, A denotes the input alphabet, X denotes the output alphabet, S denotes a nite set of states, start denotes the default start state and  and  are the transition and the output functions respectively, de ned below.

n

i

i

i

i

  : S  A ! S is the transition function.   : S  A ! X  is the output function and  denotes the closure operator over output strings.

De nition 2 :

Now we shall de ne two composition operators, stati cation and parallel composition, using which CFSMcharts may be built using basic CFSMs as the building blocks.

Let A and X be the same sets as de ned earlier. Then a sequence function f is de ned as a mapping from A to X  e.g, f : A ! X 

De nition 3 :

3

A sequence function tree is de ned recursively as :

DIGITAL OUTPUT

 each f : A ! X  is a trivial SFT of type (A,X).  if T1 to T are SFTs of type (A ; X ), h denotes the input map for each T de ned as h : A  X1  :::X  ! A and h(a,~x) = (h1 (a; ~x); :::; h (a; ~x)), where ~x 2 X1  :::  X  n

i

i

i

n

LOAD

i

PULSE

i

n

i

DOWN INVAL COUNTER

n

and g is the output map de ned as g : X1  ::  X  ! X  then, T=[h, T1 ,..., T , g] is an SFT of type (A,X) and T(!) = g(k =1 T (h !)) where, !  A and k denotes the concatenation operation. h is de ned recursively as given below: h  = ; h !< a > = h !kh (a; k =1 T (h !))

VAL mem(INVAL) DIGI-IN -VAL

AN-OUT

I1

DAC

NOTEQAL COMP

I2

EQAL

n

n i

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j

ANALOG-INPUT

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i

LATCH

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Figure 2: System Architecture of ADC

n j

j

It may be noted that the function h is an extension of h to deal with sequences. Also, < a > denotes a single input event, in contrast to ! which denotes a sequence. We use the set of all SFTs as the semantic domain of our language because they have well de ned algebraic properties and can be used to reason about the systems being modelled. We can even use the techniques similar to the ones developed in [16] to verify temporal properties of the system. Similarly, using the sequence functions as a semantics of CFSMs we have generated a proof of correctness of the behaviour mapping algorithm developed by Mitra et al. [11], which is being communicated separately.

performed for this component. Here, we make the assumption that we are dealing with one particular type of MP and designer intervention is required to generate the code equivalent to this parallel component. The designer will also be required to provide the signal equivalences in the above case. Presently we are trying to automate this task by developing an algorithm to translate a CFSM into an equivalent C language program, similar to the translation of automata into C programs in ESTEREL [2]. This program can subsequently be compiled into the assembly language of the suitable microprocessor.

i

i

3.1 Example

Consider the speci cation of the ADC using an upcounter, a DAC and a comparator which was described in Example 1. Figure 2 shows the system architecture generated by the above mapping algorithm.

3 The Behaviour Mapping Algorithm for CFSMcharts

The behaviour mapping algorithm tries to map each parallel component of the CFSMchart to an existing device CFSM in a design library (a device here refers to either a hardware programmable component or a software module corresponding to a functionality). This mapping is performed by using the behaviour mapping algorithm of Mitra et al. [11], that determines the device in the library that can implement a parallel component and also develops the speci cation of the interface for that mapping to be successful. Once a mapping is obtained for each of the parallel components, interconnection among the signal lines is performed by looking at the signal equivalences (bindings generated during mapping). Here we are assuming that each of the parallel components maps to a single device in the library. If a component functionality is denoted as microprocessor in the CFSMchart, then no mapping can be

3.2 Results

Designs for the following systems have been generated by using the CFSMchart speci cation and the mapping algorithm: ADC using down-counter, a DAC and a comparator, ADC using an up-counter, a DAC and a comparator, a simple robot controller using a downcounter(intel 8253), an MP, a port and a lathe controller using a port(intel8255), an MP and a tape reader.

4 Conclusion

The main contributions of the paper are :

 the development of a new formal speci cation

language, CFSMcharts, to eectively model systems that may use many programmable periph-

4

eral components and thus encourage componentbased design at the board level, and  the development of a formal syntax and semantics of this language. CFSMcharts can be used to automate the interfacing of system components to the microprocessor for various design applications. The proposed semantics of the language is based on SFTs [15]. We can also verify properties of the system being modeled by CFSMcharts, using the SFT semantics [14]. SFT semantics is similar to the string functional semantics in [3], where the intensional semantics of the system is given by a set of string functions modeling the components of the system and the extensional semantics is obtained by the least xed point of these functions. Similarly, we use sequence functions to model the behaviour of the components and the behaviour of the system is modelled as an SFT, which is a tree structure composition of these sequence functions. One advantage of the SFT approach over the string functional semantics is that, we can perform temporal veri cation using this semantics. The second advantage is that, unlike string functions, which are proposed as a semantics for circuit level, we are proposing SFTs as a semantics for board level systems. Moreover, our language is automata-theoretic and hence SFTs are a more intuitive choice as they model feedback products of automata. In the present version of the CFSMcharts language, no constructs for modelling time is proposed. Since MP based systems are real time systems, it is very important that constructs for modeling timing constraints be supported. We have already overcome this limitation and timed-CFSMcharts will be communicated shortly.

[5] [6] [7] [8]

[9]

[10]

[11]

[12]

[13]

References

[1] G. Berry and G. Gonthier. The ESTEREL synchronous programming language. Sc. Comput. Prog., 19:87{152, 1992. [2] F. Boussinot and R De. Simone. The esterel language. Proceedings of the IEEE, 79(9), September 1991. [3] A. Bronstein and C. L. Talcott. String-functional semantics for formal veri cation of synchronous circuits. Technical Report STAN-CS-88-1210, Department of Computer Science, Stanford University, California, 1988. [4] K. T. Cheng and A. S. Krishnakumar. Automatic functional test generation using the extended -

[14]

[15] [16]

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nite state machine model. In Proc. 30th DAC, pages 86{91, 1993. D. Harel. Statecharts : a visual formalism for complex systems. Sci. Comput. Prog., 8:231{274, 1987. J. Hooman, S. Ramesh, and W. P. de Roever. A compositional semantics for statecharts. Theoretical Computer Science, 1992. IEEE. IEEE Standard VHDL Language Reference Manual, 1988. H. Kopetz. Component-based design of large distributed real-time systems. In 14th IFAC Workshop on Distributed Computer Control Systems (DCCS'97), pages 171{177, Seoul, Korea, 1997. F. Maraninchi. The argos language : graphical representations of automata and descriptions of reactive systems. In IEEE Workshop on Visual Languages, Kobe, Japan, 1991. R. S. Mitra. Hardware Software Codesign Of Microprocessor Based Systems: A Knowledge Based Framework. PhD thesis, Department of CSE, IIT, Kharagpur, India, October 1994. R. S. Mitra, P. S Roop, and A. Basu. A new algorithm for implementation of design functions by available devices. IEEE Transactions on very large scale integration (vlsi) systems, 4(2):170{ 180, June 1996. S. Narayan, F. Vahid, and D. D. Gajski. System speci cation and synthesis with the SpecCharts language. In Int. Conf. on CAD (ICCAD), pages 266{269, 1991. T. G. Rokicki. Representing and Modeling Digital Circuits. PhD thesis, Department of Computer Science, Stanford University, 1993. P. Roop and A. Sowmya. CFSMcharts: A New Langauge for the Speci cation and Veri cation of Microprocessor Based Systems. submitted for publication, 1997. V. Yodaiken. Representations of automata. Technical Report CSTR199, New Mexico Institute of Mining and Technology, October 1995. V. Yodaiken. Automata-theoretic compositional semantics for temporal logic. In Third Workshop on Logic, Language, Information and Computation (WOLLIC) 1996, Salvador, Brazil, 1996.