Channel length extraction for DMOS transistors using ... - IEEE Xplore

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Channel Length Extraction for DMOS Transistors Using Capacitance-Voltage Measurements Roger Valtonen, Student Member, IEEE, Jörgen Olsson, Member, IEEE, and Peter De Wolf

Abstract—This paper presents a new measurement method for extraction of submicrometer channel lengths in double diffused MOS (DMOS) transistors. The method is based on capaci) measurements of the gate to p-base and the tance–voltage ( gate to drain capacitance. A channel length of 0.3 m has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the result and the measurement principle along with scanning capacitance microscopy (SCM) measurements. Index Terms—Channel length, DMOS transistors, extraction. Fig. 1. Schematic cross section of a lateral DMOS transistor where the p-base is connected to the source.

I. INTRODUCTION

B

OTH vertical and lateral double diffused MOS (DMOS) transistors are widely used today for various power electronic applications, e.g., motor controls and power supplies using vertical transistors and RF power amplifiers using lateral transistors [1]–[3]. In the case of vertical DMOS transistors, the drain region is formed by the substrate and an epi-layer with the drain contact at the bottom, while the gate and source terminals are located on top of the wafer. For lateral devices, the drain is usually consisting of either a lateral implanted n-layer on a p-substrate, or a deeper lateral n-well (n-channel devices). The drain and gate contacts are on the top of the wafer while the source contact could be either on the top or, if the substrate is connected with a p sinker diffusion, at the bottom of the wafer. The channel region, however, is often the same in both lateral and vertical devices. One important parameter for the device performance is the transistor channel length, which affects the transconductance and the on-resistance as well as the high frequency behavior. The channel in a DMOS transistor is defined by lateral diffusion of the p-base dopants under the polysilicon gate. A cross section of a typical lateral DMOS transistor structure is shown in Fig. 1. There are several methods for determining the channel length for ordinary MOS transistors [4]–[8]. These methods are not applicable to the DMOS transistor since they often rely on the variation in channel resistance versus the change of gate length, which is done lithographically in the MOS technology. The channel resistance for a DMOS transistor, however, cannot be changed in the same way since the channel length is set by the process and not by lithography. For DMOS transistors Manuscript received March 9, 2000; revised December 21, 2000. This work was carried out in the “GHz Power Transistor” project, financed by the Swedish Foundation for Strategic Research (SSF). The review of this paper was arranged by Editor K Shenai. R. Valtonen and J. Olsson are with the Uppsala University, The Ångström Laboratory, Solid-State Electronics, SE-751 21 Uppsala, Sweden. P. De Wolf is with the Digital Instruments, Santa Barbara, CA 93117 USA. Publisher Item Identifier S 0018-9383(01)05337-0.

Fig. 2. DMOS test structure for capacitance measurement is a double-sided, four-terminal device.

rather long channel lengths, a few micrometers, have been measurements in combination determined with the help of with process simulations [9]. In this paper, we have developed a nondestructive, electrical measurement method to determine the submicrometer channel lengths of modern DMOS transistors. The method is based on separate measurements of the and . It is applicable to gate terminal capacitance, both vertical and lateral DMOS transistor technologies. Test structures for this measurement method are well suited to be added on process monitor test chips, for any DMOS process. II. THEORY Normal operation of the DMOS transistor requires the source and the p-base to be connected to each other and normally grounded (see Fig. 1). The measurement method presented here requires a structure where the terminals are separated, thus forming a four-terminal DMOS test structure, schematically shown in Fig. 2. This allows the gate-to-p-base capacitance, , to be measured separately. It can also be seen that the test structure is double-sided. The fringe effects on the drain side is thereby eliminated, which otherwise would arise in a standard DMOS-structure, such as in Fig. 1. A. Numerical Simulations Numerical device simulations in Atlas (from Silvaco International) of a four-terminal DMOS structure were made in order

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Fig. 4. Charge distributions under the gate for (a) V and (c) 0 V.

V



 0 V, (b) V

< 0 V,

Fig. 3. Double-sided simulation structure for numerical device simulation in Atlas. A rather dense mesh in the gate area is required in order to obtain reliable capacitance and charge data. The drain contact is at the bottom of the structure.

to investigate different regions of operation with respect to the applied gate voltage. The simulated structure is shown in Fig. 3. m, a gate length This structure has a channel length m, and a gate oxide thickness . The simulated structure is somewhat simplified and all regions (gate, source, drain, and p-base) have uniform doping concentrations. The reason for this is that the gate voltage dependence of the charge distribution under the gate will be more clearly visible in the simulation. Consequently, the resulting shapes of the capacitance curves will also be more distinct and easier to explain. Gaussian shaped doping profiles or structures from process simulation could also be used. However, this will not affect the absolute capacitance values, on which the method relies on, only the shape of the capacitance slopes. The drain electrode is located at the highly doped n -region at the bottom of the simulated structure. The charge concentrations in the gate area and the smallsignal capacitance were extracted from the simulations. Simulations of other structures, having different channel lengths, doping levels, and geometries were also carried out. B. Charge Distribution The carrier distribution in the simulations made below, can be V, V, and divided into three different regions: V, which are shown in Fig. 4(a)–(c), respectively. The voltages ranges for these three regions are set by the threshold voltage of the n-well and p-base regions, respectively. When the gate voltage is negative, the drain region is strongly inverted while the p-base region is accumulated. This gives a continuous hole sheet, spanning the drain and the p-base regions [see Fig. 4(a)]. The drain inversion layer will vanish as the gate voltage approaches the threshold voltage of the drain [see Fig. 4(b)]. A diminishing tail at the drain surface, closest to the p-base, will still be present due to the built-in potential

Fig. 5. Simulation configuration when a small signal voltage is applied to the gate and the change in charge is calculated at the drain. The other terminals are set to common ac/dc ground, which thereby can conduct the signal.

at the pn-junction. The accumulated hole sheet in the p-base is then isolated from the drain and source. As the gate voltage increases even further, the p-base starts to deplete and finally reaches strong inversion. A continuous electron sheet will then have been formed across the entire surface underneath the gate oxide, spanning the accumulated source and drain regions and the inverted p-base [see Fig. 4(c)]. C. Small-Signal Gate Capacitance All simulations are made by applying a dc voltage at one of the terminals and superimposing a small-signal voltage. The other terminals are set to ground potential, with respect to both ac and dc. The change in charge concentration is calculated at all terminals and the capacitance is thereby extracted by the simulation software. All simulations, and also the measurements below, are done with a common dc and ac ground (see Fig. 5). The different

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Fig. 6. (a) Simulated small-signal capacitance for the four-terminal DMOS transistor test structure with a channel length of 0.3 m, f 1 MHz. The signal paths are shown underneath the graph for each voltage region: (b) V 0 V, (c) V < 0 V, and (d) V 0 V.



=



terminals can therefore lead the signal down to ground under , that certain conditions. This means, e.g., when measuring the p-base can supply the inversion layer in the drain region with positive carriers at low gate voltages under an applied ac signal. The signal at the drain, i.e., change in charge at the drain contact, is therefore unchanged and the capacitance is zero. This would not be the case if dc ground were left floating with respect to ac ground since the p-base is then allowed to follow the signal. In that case there will be no carrier transport from the p-base to the drain and consequently the signal can be measured at the drain contact. The simulated small-signal capacitance dependence on the gate voltage is shown in Fig. 6(a) for a frequency of 1 MHz. In this DMOS structure, the channel length is defined to be 0.3 m. Interpretation of the capacitance curves in Fig. 6 is given below, leading to the extraction of the channel length. : The is explained 1) Gate-Source Capacitance, is not needed for the channel length extrachere, although curve from negative to positive gate tion. Following the voltage, the gate-source capacitance starts at a low value. This corresponds to the capacitance from the gate overlap over the n -source region, plus the fringe capacitance from the gate sidewall. The capacitance will remain at this value until the p-base is inverted [see Fig. 6(d)]. When this happens there will be a conducting electron sheet underneath the whole gate, leading to an increase in capacitance. The final value at is not, however, the oxide capacitance corresponding to the total gate length. The reason for this is that a part of the signal current is collected by the drain terminal, instead of the source, . The final value of and does therefore not contribute to will then be dependent on the resistance in the signal paths, over the drain and over the source, respectively.

2) Gate-p-Base Capacitance : The curve starts at a high value since the signal current is collected by the hole sheet that spans the p-base to the drain [see Fig. 6(b)]. The signal is not, however, conducted to ground by the drain electrode due to the depletion in the drain region. When the gate voltage incurve falls rapidly as the drain leaves strong increases, the version and the signal is collected only by the accumulated hole sheet at the p-base [see Fig. 6(c)]. As the gate voltage increases further, the p-base will start depleting, leading to a successive decrease in capacitance until the p-base reaches inversion [see Fig. 6(d)]. The capacitance will reach a final value that is virtually zero since all of the signal is collected by the surface electron sheet and conducted to the drain and the source terminals. : At large negative gate 3) Gate-Drain Capacitance, curve starts at zero since the signal in this voltage, the case is conducted by the hole sheet to the p-base terminal. The capacitance will remain zero until the drain leaves inversion and the p-base cannot supply the drain with carriers through the hole sheet anymore [see Fig. 6(c)]. The capacitance rises approximately to the drain oxide capacitance in series with the drain depletion capacitance and flattens out. There will, however, be an inversion tail in the drain close to the p-base due to the built-in potential at the pn-junction, reducing the capacitance. As the gate voltage increases, the tail will vanish and the depletion will decrease, leading to an increase in the curve again. The curve will peak, as the gate voltage approaches the threshold voltage for the p-base, at a value that corresponds to the oxide capacitance over the drain region. As the p-base becomes strongly inverted [see Fig. 6(d)], a part of the signal is conducted through the electron sheet to the source. is thus dependent on the resistance in the The final value of signal paths, over the drain and over the source respectively, as curve. for the D. Channel Length Extraction Based on the previous discussion, it can be realized that the channel length is extracted by comparing the maximum values and the curves. The maximum value of is of the the same as the oxide capacitance for the drain and the p-base curve, on the other regions. The maximum value of the hand, is the same as the oxide capacitance for the drain region can therefore be extracted from only. The channel length and , which the difference in maximum capacitance for corresponds to the geometrical capacitance over the p-base. The is expression for (1) is the gate oxide thickness and is the channel width where of the transistor. Since both curves have a minimum capacitance of zero Farad, it is easy to extract the p-base oxide capacitance in measurements as well, even if the curves have different offsets due to calibration errors. Another way of extracting the channel length can be derived from the discussion of the capacitance curves. The channel curve around the same length can be extracted from the

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Fig. 7. Simulated capacitance for a four-terminal DMOS transistor test structure with a 0.6 m channel length. Fig. 8. Measurement setup when using an HP4280A CV-meter. The dc ground is connected to the ac ground shield.

gate voltage as the inflection point on the curve. At this point the inversion layer has vanished, except for the inversion tail in the drain close to the p-base. The capacitance on the curve then correspond to the oxide capacitance over the channel region. This is however only a coarse estimation of since the electric field in the oxide underneath the gate is not homogeneous and the inversion tail in the drain will effect the result. The voltage is also close to the flatband voltage of the is lower than the oxide capacitance. p-base and therefore III. RESULTS This section presents the results of channel length extraction from simulated and measured capacitance data of four-terminal DMOS structures. A. Simulation Fig. 6(a) shows capacitance data from a simulation of a structure with a defined channel length of 0.3 m. A channel length m was extracted from the difference in maxof and , which is very close to the defined imum values of value. The data from a structure with a defined channel length of 0.6 m is shown in Fig. 7. From the capacitance values a channel m is extracted. length of Other structures, having higher and/or lower doping levels in the drain and the p-base, were also simulated, as well as structures with different gate oxide thickness. The extracted channel lengths were in all cases within 5% of the defined channel lengths. Thus, the simulation results confirm the extraction method. B. Measurements The double-sided, four terminal test structures, manufactured in a DMOS process for high voltage and high frequency transistors [10], were mounted in ceramic packages. The test structure consists of several gate fingers connected in parallel. The gate length is 4 m and the finger width is 50 m. The structures

=

Fig. 9. Measured capacitance for a double-sided test structure with L = 14 976 m. The extracted channel length was 0.30 m. 4 m and W

have a total channel width of 14 976 m as calculated from the perimeter of the drawn gate width and the gate oxide thickness is 350 , as measured from process monitor wafers. These values are well known and do not significantly contribute to the total error of the measurements. The measurements were carried out with a HP4280A CV-meter at 1 MHz. The ac signal and the dc voltage were applied on the high output connected to the gate. The low output was connected either to the drain, to the source or to the p-base, while the remaining two terminals were connected to a common ac/dc-ground. Fig. 8 shows the measurement setup, in . this case for measurement of Measured capacitance data are shown in Fig. 9. Since the structure does not allow for complete calibration of parasitic capacitance associated with the package, the data contain systematic offsets. However, these errors can be corrected for in this extraction procedure since it relies on differential values of the

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channel length, given by process simulation, was also 0.32 m for the test structure. V. DISCUSSION

Fig. 10. Combined SCM and topography image of a DMOS transistor structure with gate length of 2 m.

Fig. 11. Close-up SCM image of the channel region. The channel length is measured to be 0.32 m.

capacitance, as explained by the numerical simulations. The extraction of the channel length is in this case given by

(2) The extracted channel length from the measured data is m. IV. PHYSICAL VERIFICATION The low doping level of the p-base region makes it difficult to measure the channel length using methods such as doping selective etching and SEM of transistor cross sections. Recently some new methods have been developed, mainly for determination of channel length and doping profiles of submicrometer MOS transistors. These methods are scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy (SSRM) [11], [12]. In order to verify the extraction technique presented in this paper, SCM measurements were carried out on an SEM test structure. Fig. 10 shows an image of such a structure with 2- m gate length. This image was obtained by subtracting the SCM information from the topography information. In this way, the different implanted regions are observed and positioned in reference to the polysilicon gate. Fig. 11 shows a close-up of the channel region. From the SCM data a channel length of 0.32 m was measured. The estimated

The error in this extraction method is estimated from a number of measurements to be less than 10%. This error value was obtained when the measured data were compared to SCM data. The samples in this investigation were mounted in ceramic packages in order to get more accurate capacitance measurements. On-wafer measurement is the most desired and convenient method if that is possible. However, the structures in this investigation need to be modified in order to allow on-wafer evaluation. The total area has to be increased and the metal-pad pattern optimized in order to calibrate the measurements. Apart from the channel length, other parameters can be extracted from this type of measurements. The maximum value corresponds to the length of the drain region under the gate. This is only true if the structure is double-sided, since for a single-sided fringe capacitance would contribute to structure. With the use of numerical device simulations the restriction of the channel length extraction method have been investigated. It was found that the threshold voltages of the p-base and the drain are important. For example, if the p-base threshold voltage is decurve creased (by lowering of the p-base doping level) the is premight not reach its maximum value and extraction of vented. However, this is not likely to occur in a DMOS process since the doping levels of the p-base and drain regions, and the gate oxide thickness are to a large extent determined by the required breakdown voltage of the transistor. Consequently, for n-channel, normally-off, devices the p-base threshold voltage is always positive (around 1–3 V) and the drain threshold voltage always negative. This separation of the threshold voltages is in most cases sufficient for extraction of the channel length. VI. CONCLUSION In conclusion, the method presented here allows the extraction of submicrometer channel lengths for both vertical and lateral DMOS transistors with an estimated error of less than 10%. The method has the advantage of being independent of absolute values of the capacitance, instead it is relying on differential values. One other advantage is that it is not being affected by gate sidewall fringe capacitance. ACKNOWLEDGMENT The authors would like to thank Mitel Semiconductor AB, Järfälla, Sweden, for manufacturing of the wafers. REFERENCES [1] A. Wood, C. Dragon, and W. Burger, “High performance silicon LDMOS technology for 2 GHz RF power amplifier applications,” in IEDM Tech. Dig., 1996, pp. 87–90. [2] P. Perugupalli, M. Trivedi, K. Shenai, and S. K. Leong, “Modeling and characterization of an 80 V silicon LDMOSFET for emerging RFIC applications,” IEEE Trans. Electron Devices, vol. 45, pp. 1468–1478, July 1998.

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[3] B. J. Baliga and D. Y. Chen, Power Transistors: Device Design and Applications. New York: IEEE Press, 1984. [4] Y. Taur, “MOSFET channel length: Extraction and interpretation,” IEEE Trans. Electron Devices, vol. 47, no. 1, pp. 160–170, 2000. [5] K. K. Ng and J. R. Brews, “Measuring the effective channel length of MOSFET’s,” IEEE Circuits Devices Mag., vol. 6, no. 6, pp. 33–38, 1990. [6] K. Terada and H. Muta, “A new method to determine effective MOSFET channel length,” Jpn. J. Appl. Phys., vol. 18, no. 5, pp. 953–959, 1979. [7] J. G. J. Chern, P. Chang, R. F. Motta, and N. Godinho, “A new method to determine MOSFET channel length,” IEEE Electron Device Lett., vol. EDL-1, pp. 170–173, 1980. [8] Y. Taur, D. S. Zicherman, D. R. Lombardi, P. J. Restle, C. H. Hsu, H. I. Hanafi, M. R. Wordeman, B. Davari, and G. G. Shahidi, “A new shift and ratio method for MOSFET channel length extraction,” IEEE Electron Device Lett., vol. 13, pp. 267–269, May 1992. [9] J. Kim, B. Ihn, B. Kim, K. Lee, W. Lee, and S. Lee, “Extraction of lateral device parameters and channel doping profile of vertical double-diffused MOS transistors,” Solid-State Electron., vol. 39, no. 4, pp. 541–546, 1996. [10] A. Söderbärg, B. Edholm, J. Olsson, F. Masszi, and K. H. Eklund, “Integration of a Novel High-Voltage Giga-Hertz DMOS Transistor into a Standard CMOS Process,” in IEDM Tech. Dig., 1995, pp. 975–978. [11] P. de Wolf, R. Stephenson, S. Biesemans, Ph Jansen, G. Badenes, K. De Meyer, and W. Vandervorst, “Direct measurement of L and channel profile in MOSFET’s using 2-D carrier profiling techniques,” in IEDM Tech. Dig., 1998, pp. 559–562. [12] W. Timp, M. L. O’Malley, R. N. Kleiman, and J. P. Garno, “Two-dimensional dopant profiling of a 60 nm gate length n-MOSFET using scanning capacitance microscopy,” in IEDM Tech. Dig., 1998, pp. 555–558.

Roger Valtonen (S’97) was born in Gävle, Sweden, in 1969. He revieved the M.Sc. degree in electronic engineering from Uppsala University, Sweden, in 1997, and is currently pursuing the Ph.D. degree at the Ångström Laboratory, Uppsala University. Since January 2001, he has been at Proximion Fiber Optics, Kista, Sweden. His research includes high-frequency behavior of silicon substrates and MOS devices.

Jörgen Olsson (S’93–S’95–M’96) was born in Uddevalls, Sweden, in 1966. He received a University Certificate in electronics and the Ph.D. degree in electronics from Uppsala University, Sweden, in 1990 and 1996, respectively. He is currently Head of the Solid-State Device Group at the Ångström Laboratory, Uppsala University, acting as the research leader of several projects and supervisor of a group of Ph.D. students. His research interests are primarily in the fields of high-frequency MOS-based devices and processes, high-voltage smart power devices, SOI-technology, and transistor modeling. During the summer of 1997, he was a Visiting Researcher at Digital Semicondocutor, Hudson MA, responsible for development and calibration of models for transient enhanced diffusion. He is author and coauthor of about 50 scientific articles in international journals and conferences.

Peter De Wolf, photograph and biography not available at the time of publication.