Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~
2010, John Wiley. 6-1. Chapter 6: Hierarchical Structural. Modeling. Department
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Chapter 6: Hierarchical Structural Modeling
Chapter 6: Hierarchical Structural Modeling Prof. Ming-Bo Lin
Department of Electronic Engineering National Taiwan University of Science and Technology
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Syllabus Objectives Module
Module definitions Parameters Module instantiation Module parameter values Hierarchical path names
Generate statements Generate-loop statement Generate-conditional statement Generate-case statement Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Syllabus Objectives Module Generate statements
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Objectives After completing this chapter, you will be able to: Describe the features of hierarchical structural modeling in Verilog HDL Describe the features of Verilog modules Describe how to define and override the parameters within a module Describe the port connection rules Describe how to write a parameterized module Describe how to use generate block statements Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Syllabus Objectives Module
Module definitions Parameters Module instantiation Module parameter values Hierarchical path names
Generate statements
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Module Definitions // port list style module module_name [#(parameter_declarations)][port_list]; parameter_declarations; // if no parameter ports are used port_declarations; other_declaration; statements; endmodule // port list declaration style module module_name [#(parameter_declarations)][port_declarations]; parameter_declarations; // if no parameter ports are used other_declarations; statements; endmodule Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Port Declarations Three types input output inout
net variable
net
net
net
net variable
net
module adder(x, y, c_in, sum, c_out); input [3:0] x, y; input c_in; output reg [3:0] sum; output reg c_out; Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Syllabus Objectives Module
Module definitions Parameters Module instantiation Module parameter values Hierarchical path names
Generate statements
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Types of Parameters module parameters parameter localparam
specify parameters parameter SIZE = 7; parameter WIDTH_BUSA = 24, WIDTH_BUSB = 8; parameter signed [3:0] mux_selector = 4’b0;
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Constants Specified Options `define compiler directive `define BUS_WIDTH 8 Parameter parameter BUS_WIDTH = 8; localparam localparam BUS_WIDTH = 8;
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Parameter Ports module module_name #(parameter SIZE = 7, parameter WIDTH_BUSA = 24, WIDTH_BUSB = 8, parameter signed [3:0] mux_selector = 4’b0 ) (port list or port list declarations) ... endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Syllabus Objectives Module
Module definitions Parameters Module instantiation Module parameter values Hierarchical path names
Generate statements
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Module Instantiation Syntax module_name [#(parameters)] instance_name [range]([ports]); module_name [#(parameters)] instance_name [{,instance_name}]([ports]);
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Port Connection Rules Named association .port_id1(port_expr1),..., .port_idn(port_exprn)
Positional association port_expr1, ..., port_exprn
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Syllabus Objectives Module
Module definitions Parameters Module instantiation Module parameter values Hierarchical path names
Generate statements
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Parameterized Modules An example module adder_nbit(x, y, c_in, sum, c_out); parameter N = 4; // set default value input [N-1:0] x, y; input c_in; output [N-1:0] sum; output c_out; assign {c_out, sum} = x + y + c_in; endmodule
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Module Parameters Values Ways to change module parameters values defparam statement module instance parameter value assignment
Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley
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Chapter 6: Hierarchical Structural Modeling
Overriding Parameters Using the defparam statement
module counter_nbits (clock, clear, qout); parameter N = 4; // define counter size … always @(negedge clock or posedge clear) begin // qout
